Kyushu University Academic Staff Educational and Research Activities Database
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Yusuke Matsunaga Last modified date:2017.07.13

Associate Professor / Advanced Information & Communication Technology
Department of Advanced Information Technology
Faculty of Information Science and Electrical Engineering


Graduate School
Undergraduate School
Other Organization


Academic Degree
Doctor of Engineering
Field of Specialization
Design Automation for VLSI
Outline Activities
Research interests: EDA for VLSI, esspecially logic synthesis and verification, high-level synthesis, test

Asia/South Pacific representative of Design Automation Conference Executive Committee
Secretary of VLD research group of IEICE
Asia South-Pacific Design Automation Conference technical program committee vice-chair
Research
Research Interests
  • Research on design automation for VLSI systems
    keyword : VLSI, Sytem on a Chip, EDA, CAD
    2001.04Developping a methodolgy and EDA algorithms for designing large and complex System LSI's correctly and efficiently..
Current and Past Project
  • To research and develop fundamental technologies for the VLSI system than can guarantee high reliability and high security.
Academic Activities
Papers
1. 松永 裕介, An Accelerating Technique for SAT-based ATPG, IPSJ Trans. System LSI Design Methodology, 10, 2017.03.
2. 松永 裕介, Accelerating SAT-Based Boolean Matching for Heterogeneous FPGAs Using One-Hot Encoding and CEGAR Technique
, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E99-A, 7, 2016.07.
3. 松永 裕介, A test pattern compaction method using SAT-based fault grouping, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E99-A, 12, 2015.12.
4. 松永 裕介, Synthesis Algorithm for Parallel Index Generator, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E97, 12, 2014.12.
5. Taeko Matsunaga, Shinji Kimura, 松永 裕介, An Exact Approach for GPC-Based Compressor Tree Synthesis, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E96, 12, 2013.12.
6. 髙田 大河, Yoshimura Masayoshi, 松永 裕介, Efficient Fault Simulation Algorithms for Analyzing Soft Error Propagation in Sequential Circuits, IPSJ Trans. System LSI Design Methodology, 6, 127-134, 2013.08.
7. Masayoshi Yoshimura, Yusuke Akamine and Yusuke Matsunaga, An Exact Estimation Algorithm of Error Propagation Probability for Sequential Circuits, IPSJ Trans. System LSI Design Methodology, 5, 63-70, 2012.02.
8. Taiga Takata and Yusuke Matsunaga, "A Robust Algorithm for Pessimistic Analysis of Logic Masking Effects in Combinational Circuits, IPSJ Trans. System LSI Design Methodology, 5, 55-62, 2012.02.
9. Taeko Matsunaga, Shinji Kimura and Yusuke Matsunaga,, "Multi-Operand Adder Synthesis Targeting FPGAs, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E94, 12, 2011.12.
10. Taiga Takata, Yusuke Matsunaga, Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 96, 12, 3268-3275, 2009.12.
11. Taeko Matsunaga, Shinji Kimura and Yusuke Matsunaga, Framework for Parallel Prefix Adder Synthesis Considering Switching Activities, IPSJ Transactions on System LSI Design Methodology, Vol. 2, pp.212-221, 2009.09.
12. Taiga Takata and Yusuke Matsunaga, Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs, IPSJ Transactions on System LSI Design Methodology, Vol. 2, pp.200-211, 2009.09.
13. Sho Kodama and Yusuke Matsunaga, Binding Refinement for Multiplexer Reduction, IPSJ Transaction on System LSI Design Methodology, 2009.02.
14. Tsuyoshi Sadakata and Yusuke Matsunaga, A Behavioral Synthesis Method with Special Functional Units, IEICE Trans. on Fundamentals, Vol. E91-A, No. 4, pp. 1084-1091, 2008.04.
15. Taeko Matsunaga and Yusuke Matsunaga, Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders, IEICE Trans. on Fundamentals, Vol. E90-A, No. 12, pp.2770-2777, 2007.12.
16. Tsuyoshi Sadakata and Yusuke Matsunaga, A Simultaneous Module Selection, Scheduling, and Allocation Method Considering Operation Chaining with Multi-Functional Units, IEICE Trans. on Fundamentals, Vol. E90-A, No. 4, pp.729-799, 2007.04.
17. On boolean mathing algorithm for LUT-type FPGA based on functional decomposition.
18. Yusuke Matsunaga, An Efficient Algorithm Finding Simple Disjoint Decompositions Using BDDs, IEICE Trans. on Fund., E85A, 12, E85-A, No. 12, pp. 2715-2724, 2002.12.
Presentations
1. 松永 裕介, Accelerating SAT-based Boolean Matching for Heterogeneous FPGAs Using One-Hot Encoding and CEGAR Technique, ASPDAC 2015, 2015.01.19, [URL].
2. 松永 裕介, Synthesis Algorithm of Parallel Index Generation Units, Design, Automation & Test in Europe (DATE-2014), 2014.03.28, [URL].
3. 松永 裕介, An Efficient Implementation of The Index Generation Functions, International Workshop on Logic and Synthesis (IWLS2013), 2013.06.08, [URL].
4. 髙田 大河, Yusuke Matsunaga, A Quantitative Analysis of Soft Error Propagation in Sequential Circuits, (th Workshop on Silicon Errors in Logic - System Effects (SELESE8), 2012.03.27.
5. 髙田 大河, Yoshimura Masayoshi, Yusuke Matsunaga, An Efficient Fault Simulation Algorithm for Analyzing Incorrect State Transitions induced by Soft Errors in Sequential Circuits, International Workshop on Logic and Synthesis (IWLS2012), 2012.06.03, [URL].
6. Y. Matsunaga, An Exact and Efficient Algorithms for Disjunctive Decomposition, Synthesis And System Integration of Mixed Technologies (SASMI'98), Oct. 1998.
Educational