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Yoshimura Masayoshi Last modified date：2013.5.16

Assistant Professor / Advanced Information & Communication Technology / Department of Advanced Information Technology / Faculty of Information Science and Electrical Engineering


Papers
1. Yamazaki Hiroshi, Wakazono Motohiro, Hosokawa Toshinori, Yoshimura Masayoshi,A Don't Care Identification Method for Test Compaction,16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems,2013.04.
2. Yoshimura Masayoshi, Yusuke Matsunaga,Bridging the Gap Between Device Level Modeling and Register Transfer Level Modeling,The 1st RIIF Workshop,2013.03.
3. Masayoshi Yoshimura, Amy Ogita, Toshinori Hosokawa,An Estimation of Trojan Circuits on AES Encryption Circuits,IEEE Twelfth Workshop on RTL and high level testing (WRTLT'12),Session 1.3,2012.11.
4. Toshinori Hosokawa, Akihiko Takahashi, Hiroshi Yamazaki, Masayoshi Yoshimura,A Test Point Insertion Method Using Don't Care Identification and Test Compaction Techniques to Reduce Test Application Time for Transition Faults,IEEE Twelfth Workshop on RTL and high level testing (WRTLT'12),Session 2.4,2012.11.
5. 髙田 大河, Yoshimura Masayoshi, Yusuke Matsunaga,An Efficient Fault Simulation Algorithm for Analyzing Incorrect State Transitions by Soft Errors in Sequential Circuits,IEEE Twelfth Workshop on RTL and high level testing (WRTLT'12),Session 1.3,2012.11.
6. Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Shintaro Izumi, Hiroshi Kawaguchi, and Masahiko Yoshimoto,Neutron-Induced Soft Error Rate Estimation for SRAM using PHITS,2012 IEEE 18th International On-Line Testing Symposium (IOLTS 2012),pp.pp. 138-141,2012.06. .
7. Takata Taiga, Masayoshi Yoshimura, and Yusuke Matsunaga,An Efficient Fault Simulation Algorithm for Analyzing Incorrect State Transitions Induced by Soft Errors in Sequential Circuits,The 21st International Workshop on Logic and Synthesis,pp.pp.146--151,2012.06.
8. Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto,Neutron-Induced Soft Error Rate Estimation for SRAM Using PHITS,The 2012 IEEE 18th International On-Line Testing Symposium (IOLTS),pp.pp. 138--141,2012.06. .
9. Masayoshi Yoshimura, Yusuke Akamine and Yusuke Matsunaga,An Exact Estimation Algorithm of Error Propagation Probability for Sequential Circuits,IPSJ Transactions on System LSI Design Methodology,No.5,pp.63-70,2012.02.
10. Hiroshi YAMAZAKI, Motohiro WAKAZONO, Toshinori HOSOKAWA, and Masayoshi YOSHIMURA,A Test Compaction Oriented Don't Care Identification Method,IEEE Twelfth Workshop on RTL and high level testing (WRTLT'11),2011.11.
11. Masayoshi Yoshimura, Yusuke Akamine and Yusuke Matsunaga,A Soft Error Tolerance Estimation Method for Sequential Circuits,IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems 2011 (DFT 2011),pp.pp. 268-276,2011.10.
12. Shusuke Yoshimoto, Takuro Amashita, Daisuke Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi and Masahiko Yoshimoto,Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure,2011 IEEE 17th International On-Line Testing Symposium (IOLTS 2011),pp.pp. 151-156,2011.07.
13. Masayoshi Yoshimura, Yusuke Akamine and Yusuke Matsunaga,An SER Analysis Method for Sequential Circuits,7th Workshop on Silicon Errors in Logic - System Effects (SELSE7),2011.03.
14. Shusuke Yoshimoto, Takuro Amashita, Daisuke Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi and Masahiko Yoshimoto,A Multiple-Bit-Upset Tolerant 8T SRAM Cell Layout with Divided Wordline Structure,7th Workshop on Silicon Errors in Logic - System Effects (SELSE7),2011.03.
15. Toshinori Hosokawa, Teppei Hayakawa and Masayoshi Yoshimura,A Comprehensive Functional Time Expansion Model Generation Method for Datapaths Using Controllers,IEEE Eleventh Workshop on RTL and High Level Testing (WRTLT'10),pp.pp. 131-138,2010.12.
16. Toshinori Hosokawa, Yun Chen, LingLing Wan, Motohiro Wakazono, Masayoshi Yoshimura
,A test pattern matching method on BAST architecture using don't care identification for random pattern resistant faults
,The 10th International Symposium on Communications and Information Technologies,pp.pp. 738-743,2010.10.
17. Masayoshi Yoshimura, Yuma Ito, Hiroto Yasuura
,An estimation of encryption LSI testability against scan-based attack

,The 10th International Symposium on Communication and Information Technologies,pp.pp. 727-731 ,2010.10.
18. Shoji Harada, Masayoshi Yoshimura, and Yusuke Matsunaga,TMR based Error Correction Method Considering Trade-off between Area and Soft-Error Tolerance,The 19th International Workshop on Logic and Synthesis,pp.pp.69--75,2010.06.
19. Masayoshi Yoshimura, Hiroshi Ogawa, Toshinori Hosokawa, and Koji Yamazaki,Evaluation of Transition Untestable Faults Using a Multi Cycle Capture Test Generation Method,The 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems,pp.pp.273-276,2010.04.
20. LingLing Wan, Motohiro Wakazono, Toshinori Hosokawa, and Masayoshi Yoshimura,A Bit flipping Reduction Method for Pseudo-random Patterns Using Don’t Care Identification on BAST Architecture,The Ninth IEEE Workshop on RTL and High Level Testing (WRTLT’08),2008.11.
21. Kazuya Sugiki, Toshinori Hosokawa, and Masayoshi Yoshimura,A Test Generation Method for Datapath Circuits Using Functional Time Expansion Models,The Ninth IEEE Workshop on RTL and High Level Testing (WRTLT’08),2008.11.
22. Masayoshi YOSHIMURA and Yusuke MATSUNAGA ,Development of practical ATPG tool with flexible interface ,The fifteenth Asian Test Symposium,pp.129 ,2006.11.
23. Masayoshi Yoshimura, Toshinori Hosokawa, and Mitsuyasu Ohta,A Test Point Insertion Method to Reduce the Number of Test Patterns,The 11th Asian Test Symposium,2002.11.
24. Toshinori Hosokawa, Masayoshi Yoshimura, and Mitsuyasu Ohta,Novel DFT Strategies Using Full/Partial Scan Designs and Test Point Insertion to Reduce Test Application Time,IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences,,Vol.E84-A, NO.11, pp.2722-2730,2001.11.
25. Toshinori Hosokawa, Masayoshi Yoshimura, and Mitsuyasu Ohta,Design for Testability Strategies Using Full/Partial Scan Designs and Test Point Insertions to Reduce Test Application Times,6th Asian and South Pacific Design Automation Conference,2001.02.
26. Toshinori Hosokawa, Masayoshi Yoshimura, and Mitsuyasu Ohta,RTL Partial Scan Design System: REPS,The 1st Workshop on RTL ATPG ＆ DFT,2000.09.


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