九州大学-研究者情報 [山本圭介 (准教授) 総合理工学研究院エネルギー科学部門]

Ge応用デバイス
キーワード：GeスピンMOSFET, フレキシブルGe TFT, Ge-on-Insulator
2019.04.

SiGeプロセス技術・評価技術
キーワード：SiGe, コンタクト, 歪み, 欠陥
2019.12.

SiCパワーデバイスに関する基礎研究
キーワード：3C-SiC, ゲートスタック, オーミックコンタクト, FET
2011.10.

Ge-CMOSデバイスに関する基礎研究
キーワード：Geチャネル, Ge-on-Insulator, high-k/Ge, メタルゲート, 金属/Geコンタクト, メタルS/D
2010.04.

主要原著論文

1.	Hajime Kuwazuru, Taisei Aso, Dong Wang, Keisuke Yamamoto, Low Temperature (210 °C) Fabrication of Ge MOS Capacitor and Controllability of Its Flatband Voltage, Materials Science in Semiconductor Processing, 178, 108427, 2024.08, [URL].
2.	Noboru Shimizu, Dong Wang, Hiroshi Nakashima, and Keisuke Yamamoto, Development of Ge Isotropic Wet Etching Solution and its Application to High Quality Ge-on-Insulator Fabrication through the Etchback Method, ECS Journal of Solid State Science and Technology, 10.1149/2162-8777/ad384b, 13, 4, 044001, 2024.04, [URL].
3.	Keisuke Yamamoto, Dong Wang, Roger Loo, Clement Porret, Jinyoun Cho, Kristof Dessein, Valerie Depauw, Ge-on-Insulator Fabrication based on Ge-on-Nothing Technology, Japanese Journal of Applied Physics, 10.35848/1347-4065/ad2d07, 63, 04SP32, 2024.04, [URL], Ge-on-Insulator (GOI) is considered to be a necessary structure for novel Ge-based devices. This paper proposes an alternative approach for fabricating GOI based on the Ge-on-Nothing (GeON) template. In this approach, a regular macropore array is formed by lithography and dry etching. These pores close and merge upon annealing, forming a suspended monocrystalline Ge membrane on one buried void. GOI is fabricated by direct bonding of GeON on Si carrier substrates, using an oxide bonding interface, and subsequent detachment. The fabricated GOI shows uniform physical properties as demonstrated using micro-photoluminescence measurements. Its electrical characteristics and cross-sectional structure are superior to those of Smart-CutTM GOI. To demonstrate its application potential, back-gate GOI capacitors and MOSFETs are fabricated. Their characteristics nicely agree with the theoretically calculated one and show typical MOSFET operations, respectively, which indicates promising Ge crystallinity. This method, therefore, shows the potential to provide high-quality GOI for advanced Ge application devices..
4.	Linyu Huang, Kenta Moto, Kota Igura, Takamitsu Ishiyama, Kaoru Toko, Dong Wang, Keisuke Yamamoto, Low-temperature process design for inversion mode n-channel thin-film-transistor on polycrystalline Ge formed by solid-phase crystallization, Japanese Journal of Applied Physics, 10.35848/1347-4065/ad13a1, 63, 2, 02SP42, 2024.01, [URL].
5.	Kenta Moto, Kaoru Toko, Tomonari Takayama, Toshifumi Imajo, Takamitsu Ishiyama, and Keisuke Yamamoto, Rectifying Schottky Contact in ZrN/polycrystalline p-Ge, IEEE Journal of the Electron Devices Society, 10.1109/JEDS.2023.3323776, 11, 553-558, 2023.10, [URL].
6.	Keisuke Yamamoto, Takuro Matsuo, Michihiro Yamada, Youya Wagatsuma, Kentaro Sawano, Kohei Hamaya, Electrical properties of a low-temperature fabricated Ge-based top-gate MOSFET structure with epitaxial ferromagnetic Heusler-alloy Schottky-tunnel source and drain, Materials Science in Semiconductor Processing, https://doi.org/10.1016/j.mssp.2023.107763, 167, 15, 107763, 2023.08, [URL].
7.	Wei-Chen Wen, Dong Wang, Hiroshi Nakashima, Keisuke Yamamoto, Fabrication and Characterization of Germanium n-MOS and n-MOSFET with Thermally Oxidized Yttrium Gate Insulator: Formation of underlying Germanium Oxide and Its Electrical Characteristics, Materials Science in Semiconductor Processing, 10.1016/j.mssp.2023.107504, 162, 1, 107504, 2023.04, [URL].
8.	Keisuke Yamamoto, Dong Wang, Hiroshi Nakashima, Shigeomi Hishiki, Hiroki Uratani, Yoshiki Sakaida, Keisuke Kawamura , High channel mobility of 3C-SiC n-MOSFETs with gate stacks formed at low temperature - the importance of Coulomb scattering suppression, Applied Physics Express, 10.35848/1882-0786/ac7846, 15, 7, 071008, 2022.06, [URL].
9.	Kenta Moto, Keisuke Yamamoto, Toshifumi Imajo, Takashi Suemasu, Hiroshi Nakashima, Kaoru Toko, Sn concentration effects on polycrystalline GeSn thin film transistors, IEEE Electron Device Letters, 10.1109/LED.2021.3119014, 2021.12, [URL].
10.	Keisuke Yamamoto, Dong Wang, Hiroshi Nakashima, (Invited) Fabrication of Ge-on-Insulator By Epitaxial Growth and Ion-Implanted Exfoliation for Electronics and Opt-Electronics Applications, ECS Transactions, 10.1149/10404.0157ecst, 104, 4, 157-166, 2021.10, [URL].
11.	Keisuke Yamamoto, Dong Wang, Hiroshi Nakashima, (Invited) Schottky Barrier Height Control at Metal/Ge Interface by Insertion of Nitrogen Contained Amorphous Layer, ECS Transactions, 10.1149/10204.0063ecst, 102, 4, 63-71, 2021.05, [URL].
12.	Hiroshi Nakashima, Wei-Chen Wen, Keisuke Yamamoto, Dong Wang, Border-Trap Characterization for Ge Gate Stacks with Thin GeO_X layer Using Deep-Level Transient Spectroscopy, ECS Transactions, 10.1149/09805.0395ecst, 98, 5, 395-404, 2020.10, [URL].
13.	Wei-Chen Wen, Yuta Nagatomi, Hiroshi Akamine, Keisuke Yamamoto, Dong Wang, Hiroshi Nakashima, Interface trap and border trap characterization for Al₂O₃/GeO_x/Ge gate stacks and influence of these traps on mobility of Ge p-MOSFET, AIP advances, 10.1063/5.0002100, 10, 6, 065119-1-065119-7, 2020.06, [URL].
14.	Ryusei Oka, Keisuke Yamamoto, Hiroshi Akamine, Dong Wang, Hiroshi Nakashima, Sigeomi Hishiki, Keisuke Kawamura, High interfacial quality metal-oxide-semiconductor capacitor on (111) oriented 3C-SiC with Al₂O₃ interlayer and its internal charge analysis, Japanese Journal of Applied Physics, 10.35848/1347-4065/ab6862, 59, SG, SGGD17 1-SGGD17 10, 2020.04, [URL].
15.	Keisuke Yamamoto, Kohei Nakae, Hiroshi Akamine, Dong Wang, Hiroshi Nakashima, Md. M Alam, Kentarou Sawano, Zhongying Xue, Miao Zhang, and Zengfeng Di, Conduction Type Control of Ge-on-Insulator: Combination of Smart-Cut^TM and Defect Elimination, ECS Transactions, 10.1149/09301.0073ecst, 93, 1, 73-77, 2019.10, [URL].
16.	Kenta Moto, Keisuke Yamamoto, Toshifumi Imajo, Takashi Suemasu, Hiroshi Nakasima, Kaoru Toko, Polycrystalline thin-film transistors fabricated on high-mobility solid-phase-crystallized Ge on glass, Applied Physics Letters, 10.1063/1.5093952, 114, 21, 212107, 2019.05, [URL].
17.	Keisuke Yamamoto, Kohei Nakae, Dong Wang, Hiroshi Nakasima, Zhongying Xue, Miao Zhang, Zengfeng Di , Ge field-effect transistor with asymmetric metal source/drain fabricated on Ge-on-Insulator: Schottky tunneling source mode operation and conventional mode operation , Japanese Journal of Applied Physics, 10.7567/1347-4065/ab02e3, 58, SB, SBBA14, 2019.03, [URL].
18.	Keisuke Yamamoto, Ryutaro Noguchi, Masatoshi Mitsuhara, Minoru Nishida, Toru Hara, Dong Wang, Hiroshi Nakashima , Wide range control of Schottky barrier heights at metal/Ge interfaces with nitrogen-contained amorphous interlayers formed during ZrN sputter deposition, Semiconductor Science and Technology, 10.1088/1361-6641/aae4bd, 33, 11, 114011, 2018.10, [URL].
19.	Keisuke Yamamoto, Hayato Okamoto, Dong Wang, Hiroshi Nakashima, Fabrication of asymmetric Ge Schottky tunneling source n-channel field-effect transistor and its characterization of tunneling conduction, Materials Science in Semiconductor Processing, 10.1016/j.mssp.2016.09.024, 70, 1, 283-287, 2016.10, [URL].
20.	Keisuke Yamamoto, Ryutaro Noguchi, Mitsuhara Masatoshi, Minoru Nishida, Toru Hara, Dong Wang, Hiroshi Nakashima, Electrical and structural properties of group-4 transition-metal nitride (TiN, ZrN, and HfN) contacts on Ge, Journal of Applied Physics, 10.1063/1.4930573, 118, 11, 115701-1-115701-12, 2015.09, [URL].
21.	Keisuke Yamamoto, Mitsuhara Masatoshi, Keisuke Hiidome, Ryutaro Noguchi, Minoru Nishida, DONG WANG, Hiroshi Nakashima, Role of an interlayer at a TiN/Ge contact to alleviate the intrinsic Fermi-level pinning position toward the conduction band edge , Applied Physics Letters, 10.1063/1.4870510, 104, 14, 132109-1-132109-5, 2014.04, [URL].
22.	Yamamoto Keisuke, DONG WANG, Hiroshi Nakashima, Fabrication of Metal-Nitride/Si Contacts with Low Electron Barrier Height, ECS Transactions, 10.1149/05809.0053ecst, 58, 9, 53, 2013.10, [URL].
23.	Yamamoto Keisuke, Takahiro Sada, DONG WANG, Hiroshi Nakashima, Dramatic enhancement of low electric-field hole mobility in metal source/drain Ge p-channel metal-oxide-semiconductor field-effect transistors by introduction of Al and Hf into SiO₂/GeO₂ gate stack, Applied Physics Letters, 10.1063/1.4821546, 103, 12, 122106, 2013.09, [URL].
24.	K. Yamamoto, K. Harada, H. Yang, D. Wang, H. Nakashima, Fabrication of TiN/Ge Contact with Extremely Low Electron Barrier Height, Japanese Journal of Applied Physics, 10.1143/JJAP.51.070208, 51, 7, 070208, 2012.07, [URL].
25.	K. Yamamoto, T. Yamanaka, K. Harada, T. Sada, K. Sakamoto, S. Kojima, H. Yang, D. Wang, H. Nakashima, Schottky Source/Drain Ge Metal-Oxide-Semiconductor Field-Effect Transistors with Directly Contacted TiN/Ge and HfGe/Ge Structures, Applied Physics Express, 10.1143/APEX.5.051301, 5, 5, 051301, 2012.05, [URL].
26.	K. Yamamoto, T. Yamanaka, R. Ueno, K. Hirayama, H. Yang, D. Wang, H. Nakashima, Source/drain junction fabrication for Ge metal-oxide-semiconductor field-effect transistors, Thin Solid Films, 10.1016/j.tsf.2011.10.047, 520, 8, 3382, 2012.02, [URL].
27.	K. Yamamoto, R. Ueno, T. Yamanaka, K. Hirayama, H. Yang, D. Wang, H. Nakashima, High-Performance Ge Metal-Oxide-Semiconductor Field-Effect Transistors with a Gate Stack Fabricated by Ultrathin SiO₂/GeO₂ Bilayer Passivation, Applied Physics Express, 10.1143/APEX.4.051301, 4, 5, 051301, 2011.04, [URL].

主要学会発表等

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1.	H. Kuwazuru, D. Wang, and K. Yamamoto, Fabrication of a Ge gate stack using plasma irradiation and low-temperature annealing for Ge applications, 14th International WorkShop on New Group IV Semiconductor Nanoelectronics, 2023.12.
2.	K. Yamamoto, W.-C. Wen, D. Wang, and H. Nakashima, Electrical and Structural Characterization of Thermally Oxidized Yttrium Oxide on Germanium, 14th International WorkShop on New Group IV Semiconductor Nanoelectronics, 2023.12.
3.	L. Huang, K. Moto, K. Igura, T. Ishiyama, K. Toko, D. Wang, K. Yamamoto, Inversion Mode n-channel TFT Fabricated on Solid-Phase Crystallized Polycrystalline Ge at Low Temperature Improved by Metal Induced Dopant Activation, 14th International WorkShop on New Group IV Semiconductor Nanoelectronics, 2023.12.
4.	H. Kuwazuru, D. Wang, K. Yamamoto , Low Temperature (~210 °C) Fabrication of Ge MOS Capacitor using Plasma Oxidation and Oxi-Nitridation for the Interlayer Formation, 2023 International Workshop on DIELECTRIC THIN FILMS FOR FUTURE ELECTRON DEVICES: SCIENCE AND TECHNOLOGY, 2023.10.
5.	K. Yamamoto, D. Wang, R. Loo, C. Porret, J. Cho, K. Dessein, V. Depauw, Fabrication and Electrical Characterization of Ge-on-Insulator based on Ge-on-Nothing Technology, 2023 International Workshop on DIELECTRIC THIN FILMS FOR FUTURE ELECTRON DEVICES: SCIENCE AND TECHNOLOGY, 2023.10, Ge-on-Insulator (GOI) is considered to be a necessary structure for novel Ge-based devices. This paper proposes an alternative approach for fabricating GOI based on the Ge-on-Nothing (GeON) template. In this approach, a regular macropore array is formed by lithography and dry etching. These pores close and merge upon annealing, forming a suspended monocrystalline Ge membrane on one buried void. GOI is fabricated by direct bonding of GeON on Si carrier substrates, using an oxide bonding interface, and subsequent detachment. The fabricated GOI shows uniform physical properties as demonstrated using micro-photoluminescence measurements. Its electrical characteristics and cross-sectional structure are superior to those of Smart-CutTM GOI. To demonstrate its application potential, back-gate GOI capacitors and MOSFETs are fabricated. Their characteristics nicely agree with the theoretically calculated one and show typical MOSFET operations, respectively, which indicates promising Ge crystallinity. This method, therefore, shows the potential to provide high-quality GOI for advanced Ge application devices..
6.	L. Huang, K. Moto, T. Ishiyama, K. Toko, D. Wang, K. Yamamoto, Fabrication of Inversion Mode n-channel TFT on Solid-Phase Crystallized Polycrystalline Ge, 2023年第84回応用物理学会秋季学術講演会, 2023.09.
7.	鍬釣一、王冬、山本圭介, ﾘｾｽﾁｬﾈﾙ化によるメタルS/D 型Ge n-MOSFET の電流駆動力向上(III), 2023年第84回応用物理学会秋季学術講演会, 2023.09.
8.	L. Huang, K. Moto, T. Ishiyama, K. Toko, D. Wang, and K. Yamamoto, Inversion Mode n-channel TFT on Polycrystalline Ge Formed by Solid-Phase Crystallization, 2023 International Conference on Solid State Device and Materials (SSDM 2023), 2023.09.
9.	K. Moto, K. Toko, T. Takayama, T. Ishiyama, K. Yamamoto, Various Metal Contacts on Polycrystalline Ge with Amorphous Interlayer Formed by ZrN Sputter-Deposition, 2023 International Conference on Solid State Device and Materials (SSDM 2023), 2023.09.
10.	K. Yamamoto, W.-C. Wen, D. Wang, and H. Nakashima, Thermally oxidized Yttrium Oxide on Germanium for n-MOS Capacitor and Field-Effect Transistor, 244th ECS meeting, 2023.10, Germanium (Ge) has many exciting material characteristics, such as high carrier mobility and narrow bandgap in the near-infrared range. Thus it is suitable for various applications. A high-quality insulating film on Ge is required to apply Ge to novel electronic devices successfully. It is well known that GeO2 on Ge has good electrical characteristics as a gate insulator or interlayer (IL), similar to SiO2 on Si [1]. Unlike SiO2, however, GeO2 is thermodynamically unstable under atmospheric pressure at typical oxidation temperatures (~400 °C) and volatilizes as GeO [2,3]. Several methods have been developed to suppress GeO volatilization from the surface. For example, transition metals such as yttrium (Y) have been introduced into GeO2. Yttrium (Y)-doped GeO2 has excellent thermal, chemical, and electrical characteristics. In the capacitance–voltage measurement, it shows a low interface state density (Dit) and a narrow hysteresis corresponding to the border trap (BT) density (Nbt) of gate insulators [4]. Based on the above studies, we focused on metal Y deposition with subsequent thermal oxidation as an efficient alternative method to deposit Y-oxide as a gate insulator on Ge. This method has been studied to deposit Y2O3 as a gate insulator on Si [5]. Moreover, metal oxidation has been used to form various gate insulators on Ge, such as Al [6] and Hf [7]. In this study, we expect a capping layer of Y and oxidized Y to suppress GeO volatilization and stabilize the interface. We fabricated and evaluated metal-oxide-semiconductor (MOS) capacitors and MOS field-effect transistors (FETs) with either a thermally oxidized Y or a thermally oxidized Ge oxide layer. The structural analysis found that the insulator was divided into three layers: Y2O3, YGeO3, and GeOx from the top. The oxidation temperature affected only the thickness of the bottom GeOx layer. We found that the Y-oxide gate stack had better electrical characteristics and a lower Dit and Nbt than the thermally oxidized GeOx insulator. In contrast, the Dit–energy distribution and Nbt temperature dependence of the Y-oxide gate insulator were similar to those of the GeOx gate insulator. We examined these observations, including the structural analysis results. We found that thermally oxidized Y had a distinct advantage over thermally oxidized Ge oxide: the possibility of controlling the structure and electrical characteristics of the Ge gate stack, such as the GeOx thickness and the BT signal origin..
11.	K. Moto, K. Toko, T. Takayama, T. Ishiyama, and K. Yamamoto, Control of schottky barrier height at metal/polycrystalline Ge interfaces with fermi-level pinning alleviation, International Conference on Silicon Epitaxy and Heterostructures and International SiGe Technology and Device Meeting 2023 (ISTDM-ICSI 2023), 2023.05.
12.	K. Yamamoto, D. Wang, R. Loo, C. Porret, J. Cho, K. Dessein, and V. Depauw, Evaluation of the physical properties of Ge-on-insulator based on Ge-on-Nothing and layer transfer, International Conference on Silicon Epitaxy and Heterostructures and International SiGe Technology and Device Meeting 2023 (ISTDM-ICSI 2023), 2023.05.
13.	H. Kuwazuru, S. Nasu, D. Wang, and K. Yamamoto, Study on the Performance of Metal S/D Ge n-MOSFET with Recessed Channel Structure, 13th International WorkShop on New Group IV Semiconductor Nanoelectronics, 2023.01.
14.	L. Huang, K. Moto, T. Ishiyama, K. Toko, D. Wang, and K. Yamamoto, Inversion Mode n-channel TFT on Polycrystalline Ge Formed by Solid-Phase Crystallization, 13th International WorkShop on New Group IV Semiconductor Nanoelectronics, 2023.01.
15.	K. Yamamoto, D. Wang, R. Loo, C. Porret, J. Cho, K. Dessein, and V. Depauw, Ge-on-Insulator from Ge-on-Nothing and Layer Transfer, 13th International WorkShop on New Group IV Semiconductor Nanoelectronics, 2023.01.
16.	高山智成、茂藤健太、都甲薫、王冬、山本圭介, 金属/多結晶Ge界面におけるフェルミレベルピニングの緩和とショットキー障壁制御, 2022年第83回応用物理学会秋季学術講演会, 2022.09.
17.	茂藤健太、都甲薫、高山智成、今城利文、山本圭介, 多結晶p型Ge上におけるショットキー整流性コンタクトの形成, 2022年第83回応用物理学会秋季学術講演会, 2022.09.
18.	那須新悟、王冬、山本圭介, リセスチャネル化によるメタルS/D型Ge n-MOSFETの電流駆動力向上(II), 2022年第83回応用物理学会秋季学術講演会, 2022.09.
19.	山本圭介, 3C-SiCへの高品質ゲートスタック形成とMOSFET応用, （公財）科学技術交流財団　第4回「厳環境下IoTワイドギャップ素子研究会」, 2022.07.
20.	K. Moto, K. Toko, T. Takayama, T. Imajo, K. Yamamoto , First Demonstration of Rectifying Schottky Contact on Polycrystalline P-Type Ge Using ZrN Electrode, 2022 International Conference on Solid State Device and Materials (SSDM 2022), 2022.09.
21.	W.-C. Wen, K. Yamamoto, D. Wang, H. Nakashima, Fabrication and Characterization of Ge n-MOS and n-MOSFET with Thermally Oxidized Yttrium Gate Insulator, 9th International Symposium on Control of Semiconductor Interfaces (ISCSI-IX), 2022.09.
22.	T. Takayama, K. Moto, K. Yamamoto, T. Imajo, K. Toko, Fabrication and evaluation of polycrystalline Ge-based thin-film transistors on glass, The 5th International Union of Materials Research Societies International Conference of Young Researchers on Advanced Materials (IUMRS-ICYRAM 2022), 2022.08.
23.	S. Nasu, T. Matsuo, K. Yamamoto, D. Wang, Fabrication of Ge MOSFET at low temperature (~250°C) for spintronics application, The 5th International Union of Materials Research Societies International Conference of Young Researchers on Advanced Materials (IUMRS-ICYRAM 2022), 2022.08.
24.	K. Yamamoto, T. Matsuo, D. Wang, K. Moto, K. Toko, H. Nakashima, Novel group IV semiconductor materials and devices for beyond Si technology, The 5th International Union of Materials Research Societies International Conference of Young Researchers on Advanced Materials (IUMRS-ICYRAM 2022), 2022.08.
25.	清水昇、王一、山本圭介、張師宇、中塚理、王冬 , 電子・光デバイス応用に向けた金属/GeSn 接合の低温形成, 2022年第69回応用物理学会春季学術講演会, 2022.03.
26.	山本圭介、王冬、中島寛、菱木繁臣、浦谷泰基、坂井田佳紀、川村啓介 , 高移動度3C-SiC n-MOSFET の作製と高温動作実証, 2022年第69回応用物理学会春季学術講演会, 2022.03.
27.	Keisuke Yamamoto, Dong Wang, Hiroshi Nakashima, Shigeomi Hishiki, Hiroki Uratani, Yoshiki Sakaida, Keisuke Kawamura , Achievement of High Channel Mobility of 3C-SiC n-MOSFET with the Gate Stack Formed at Low Temperature, 2021 International Workshop on DIELECTRIC THIN FILMS FOR FUTURE ELECTRON DEVICES: SCIENCE AND TECHNOLOGY, 2021.11.
28.	Keisuke Yamamoto, Dong Wang, Hiroshi Nakashima, Fabrication of Ge-on-Insulator By Epitaxial Growth and Ion-Implanted Exfoliation for Electronics and Opt-Electronics Applications, 240th ECS meeting, 2021.10.
29.	茂藤健太、山本圭介、今城利文、末益崇、中島寛、都甲薫, 固相成長GeSn薄膜トランジスタにおけるSn組成の影響, 2021年第82回応用物理学会秋季学術講演会, 2021.09.
30.	松尾拓朗、山本圭介、王冬, リセスチャネル化によるメタルS/D型Ge n-MOSFETの電流駆動力向上, 2021年第82回応用物理学会秋季学術講演会, 2021.09.
31.	松尾拓朗、山本圭介、王冬, GeスピンMOSFETのための低温（～250°C）デバイスプロセスの構築, 2021年第82回応用物理学会秋季学術講演会, 2021.09.
32.	Kenta Moto, Keisuke Yamamoto, Toshifumi Imajo, Takashi Suemasu, Hiroshi Nakashima, Kaoru Toko , Sn Doping Effects on Polycrystalline Germanium Thin-Film Transistors on Glass, 2021 International Conference on Solid State Device and Materials (SSDM 2021), 2021.09.
33.	Keisuke Yamamoto, Kento Iseri, Dong Wang, Hiroshi Nakashima, Low-Temperature Fabrication of Ge MOS Capacitor with Wet Oxidized Yttrium Interlayer, 2021 International Conference on Solid State Device and Materials (SSDM 2021), 2021.09.
34.	Keisuke Yamamoto, Dong Wang, Hiroshi Nakashima, Schottky Barrier Height Control at Metal/Ge Interface by Insertion of Nitrogen Contained Amorphous Layer, 239th ECS meeting, 2021.05.
35.	清水昇、山本圭介、王冬、中島寛, エッチバック法を用いたGe-on-Insulator作製に向けたウェットエッチング法の検討, 第68回応用物理学会春季学術講演会, 2021.03.
36.	Kenta Moto, Keisuke Yamamoto, Takashi Suemasu, Hiroshi Nakashima, Kaoru Toko , Sn Doping Effects in Solid-Phase Crystallized Ge Thin-Film Transistors, PRiME 2020, 2020.10.
37.	Hiroshi Nakashima, Wei-Chen Wen, Keisuke Yamamoto, Dong Wang, Border-Trap Characterization for Ge Gate Stacks with Thin GeO_X layer Using Deep-Level Transient Spectroscopy, PRiME 2020, 2020.10.
38.	Noboru Shimizu, Keisuke Yamamoto, Dong Wang, Hiroshi Nakashima, Isotropic Wet Etching and Improving Surface Flatness of Ge for Etchback Ge-on-Insulator Fabrication, PRiME 2020, 2020.10.
39.	Hiroki Kanakogi, Wei-Chen Wen, Keisuke Yamamoto, Dong Wang, Hiroshi Nakashima, Thermally Oxidized Yttrium and Scandium Gate Dielectrics on Germanium with High Interfacial and Film Qualities, 2020 International Conference on Solid State Device and Materials (SSDM 2020), 2020.09.
40.	Wei-Chen Wen, Keisuke Yamamoto, Dong Wang, Hiroshi Nakashima, Study on Position of Border Traps in Al₂O₃/GeO_X/p-Ge Gate Stacks Using Deep-Level Transient Spectroscopy, 8th International Symposium on Control of Semiconductor Interfaces (ISCSI-VIII), 2019.11.
41.	井芹健人、温偉辰、山本圭介、王冬、中島寛, 新規電子デバイス応用に向けたGeゲートスタックの低温(
42.	山本圭介、岡龍誠、王冬、中島寛、菱木繁臣、川村啓介, SiO₂/Al₂O₃絶縁膜を有する3C-SiC n-MOSキャパシタとn-MOSFET動作, 第80回応用物理学会秋季学術講演会, 2019.09.
43.	岡龍誠、山本圭介、王冬、中島寛、菱木繁臣、川村啓介, SiO₂/Al₂O₃絶縁膜を有する3C-SiC n-MOSキャパシタの固定電荷と界面ダイポール解析, 第80回応用物理学会秋季学術講演会, 2019.09.
44.	Kento Iseri, Wei-Chen Wen, Keisuke Yamamoto, Dong Wang, Hiroshi Nakashima , Low temperature (oC) Fabrication of Ge MOS Structure for Advanced Electronic Devices, 2019 International Conference on Solid State Device and Materials (SSDM 2019), 2019.09.
45.	Ryusei Oka, Keisuke Yamamoto, Dong Wang, Hiroshi Nakashima, Sigeomi Hishiki, Keisuke Kawamura, Demonstration of n-MOSFET operation and charge analysis of SiO₂/Al₂O₃ gate dielectric on (111) oriented 3C-SiC, 2019 International Conference on Solid State Device and Materials (SSDM 2019), 2019.09.
46.	K. Yamamoto, K. Nakae, H. Akamine, D. Wang, H. Nakashima, Md. M. Alam, K. Sawano, Z. Xue, M. Zhang, Z. Di , Conduction Type Control of Ge-on-Insulator: Combination of Smart-Cut and Defect Elimination, 2nd Joint ISTDM / ICSI 2019 Conference 10th International SiGe Technology and Device Meeting (ISTDM) 12th International Conference on Silicon Epitaxy and Heterostructures, 2019.06.
47.	Keisuke Yamamoto, Kentaro Akiyama, Kento Iseri, Wei-Chen Wen, Dong Wang, Hiroshi Nakashima , Fabrication of Ge MOS Capacitor with Metal Yttrium Oxidation, 12th International WorkShop on New Group IV Semiconductor Nanoelectronics, 2018.12.
48.	仲江航平、薛飛達、山本圭介、王冬、中島寛、Miao Zhang、Zhongying Xue、Zenfeng Di, Smart-Cut法を用いて作製したGe-on-Insulatorの極性変化, 第79回応用物理学会秋季学術講演会, 2018.09.
49.	Wei-Chen Wen、Keisuke Yamamoto、Dong Wang、Hiroshi Nakashima, Low-temperature fabrication of Ge MOS capacitors for spintronics and flexible electronics application, 第79回応用物理学会秋季学術講演会, 2018.09.
50.	秋山健太郎、井芹健人、温偉辰、山本圭介、王冬、中島寛, 電子ビーム蒸着によるGe上へのY酸化物系ゲート絶縁膜形成, 第79回応用物理学会秋季学術講演会, 2018.09.
51.	K. Yamamoto, K. Nakae, D. Wang, H. Nakashima, Z. Xue, M. Zhang, Z. Di, Ambipolar operation of asymmetric Ge Schottky tunneling source field-effect transistor fabricated on Ge-on-Insulator, 2018 International Conference on Solid State Device and Materials (SSDM 2018), 2018.09.
52.	K. Yamamoto, D. Wang, H. Nakashima, S. Hishiki, K. Kawamura, Impact of Al₂O₃ interlayer for metal-oxide-semiconductor capacitor on (111) oriented 3C-SiC for electronic device application, 2018 International Conference on Solid State Device and Materials (SSDM 2018), 2018.09.
53.	山本圭介、光原昌寿、王冬、中島寛 , 遷移金属窒化物を用いた金属/Geコンタクトの障壁制御 , 第65回応用物理学会春季学術講演会, 2018.03.
54.	板屋航, 仲江航平, 山本圭介, 王冬, 中島寛, 非晶質Ge界面層とNによるGeコンタクトの外因性準位とSファクターの変調(Ⅱ), 第78回応用物理学会秋季学術講演会, 2017.09.
55.	岡本隼人, 山本圭介, 王冬, 中島寛, [講演奨励賞受賞記念講演] 非晶質Zr-Ge-N層上への金属堆積による低抵抗Geコンタクトの形成 , 第64回応用物理学会春季学術講演会, 2017.03.
56.	Keisuke Yamamoto, Hayato Okamoto, DONG WANG, Hiroshi Nakashima, Achievement of Ultralow Contact Resistivity of Metal/Ge Contacts with Zr-N-Ge Amorphous Interlayer, 10th International Workshop on New Group IV Semiconductor Nanoelectronics and JSPS Core-to Core Program Joint Seminar "Atomically Controlled Processing for Ultralarge Scale Integration", 2017.02.
57.	Hayato Okamoto, Keisuke Yamamoto, Dong Wang, Hiroshi Nakashima, Achievement of Ultralow Contact Resistivity of Metal/Ge Contacts with Zr-N-Ge Amorphous Interlayer, 2016 International Conference on Solid State Device and Materials (SSDM 2016), 2016.09, [URL].
58.	岡本隼人, 山本圭介, 王冬, 中島寛, 非晶質Zr-Ge-N層上への金属堆積による低抵抗Geコンタクトの形成, 第77回応用物理学会秋季学術講演会, 2016.09.
59.	Keisuke Yamamoto, Hayato Okamoto, DONG WANG, Hiroshi Nakashima, Characterization of Ge Tunnel FET with Metal/Ge Junction, 7th International Symposium on Control of Semiconductor Interfaces / International SiGe Technology and Device Meeting, 2016.06, [URL].
60.	山本圭介, 岡本隼人, 王冬, 中島寛, 金属/Ge接合及びn⁺/Ge接合を用いたGeトンネルFETの作製と評価, 第63回応用物理学会春季学術講演会, 2016.03.
61.	Keisuke Yamamoto, Ryutaro Noguchi, Masatoshi Mitsuhara, Minoru Nishida, Toru Hara, Dong Wang, Hiroshi Nakashima, Barrier Height Modulation for Metal/Ge Contacts with Nitrogen-Contained Amorphous Interlayers, 9th International Conference on Silicon Epitaxy and Heterostructures (ICSI-9), 2015.05, [URL].
62.	山本圭介, 王冬, 中島寛, 非晶質Ge界面層とNによるGeコンタクトの外因性準位とSファクターの変調, 第75回応用物理学会秋季学術講演会, 2014.09.
63.	Yamamoto Keisuke, DONG WANG, Hiroshi Nakashima, Fermi level pinning alleviation at the TiN, ZrN, and HfN/Ge interfaces, 7th International Silicon-Germanium Technology and Device Meeting (ISTDM 2014), 2014.06, [URL].
64.	山本圭介, 光原昌寿, 吹留佳祐, 野口竜太郎, 西田稔, 王冬, 中島寛, TiN/Geコンタクトにおける低電子障壁発現機構の解明（Ⅱ）, 第61回応用物理学会春季学術講演会, 2014.03.
65.	Keisuke Yamamoto, WANG DONG, Nakashima Hiroshi, Noguchi Ryutaro, Nishida Minoru, Mitsuhara Masatoshi, Hara Toru, Electrical Properties of Metal/Ge contacts with Nitrogen-Contained Amorphous Interlayers, 8th International Workshop on New Group IV Semiconductor Nanoelectronics and JSPS Core-to Core Program Joint Seminar "Atomically Controlled Processing for Ultralarge Scale Integration", 2014.01.
66.	Keisuke Yamamoto, WANG DONG, Nakashima Hiroshi, Fabrication of Metal-Nitride/Ge Contacts with Extremely Low Electron Barrier Height and Its Clarification of the Physical Origin, 7th International Workshop on New Group IV Semiconductor Nanoelectronics and JSPS Core-to Core Program Joint Seminar "Atomically Controlled Processing for Ultralarge Scale Integration", 2014.01.
67.	Yamamoto Keisuke, DONG WANG, Hiroshi Nakashima, Fabrication of Metal-Nitride/Si Contactswith Low Electron Barrier Height, 224th ECS Meeting, 2013.10, [URL].
68.	山本圭介, 佐田隆宏, 王冬, 中島寛, ゲートスタックへのHf導入によるメタル・ソース/ドレインGe p-MOSFETの高移動度化, 電子情報通信学会シリコン材料・デバイス研究会 (応用物理学会、シリコンテクノロジー分科会との合同開催）, 2013.06.
69.	Yamamoto Keisuke, Takahiro Sada, DONG WANG, Hiroshi Nakashima, Metal Source/Drain Ge p-MOSFET with HfGe/Ge Contact, 8th International Conference on Silicon Epitaxy and Heterostructures(ICSI-8) 2013, 2013.06.
70.	Yamamoto Keisuke, Asakawa Kojiro, DONG WANG, Hiroshi Nakashima, Fabrication of TiN/Si Contact with Low Electron Barrier Height and Its Application to Back-Gate MOSFET, 6th International Symposium on Control of Semiconductor Interfaces (ISCSI-VI) 2013, 2013.06.
71.	山本圭介, 光原昌寿, 西田稔, 王冬, 中島寛, TiN/Geコンタクトにおける低電子障壁発現機構の解明, 第60回応用物理学会春季学術講演会, 2013.03.
72.	山本圭介, 王冬, 中島寛, 整流性TiN/p-Geコンタクトに於ける表面パッシベーションの重要性, 第73回応用物理学会学術講演会, 2012.09.
73.	山本圭介, 井餘田昌俊, 王冬, 中島寛, TiN/Geコンタクトに於けるフェルミレベルピンニング変調とMOSデバイスへの応用, 電子情報通信学会シリコン材料・デバイス研究会 (応用物理学会、シリコンテクノロジー分科会との合同開催）, 2012.06.
74.	山本圭介, 原田健司, 楊海貴, 王冬, 中島寛, 低障壁TiN/n-Ge コンタクトの形成とコンタクト抵抗評価, 第59回応用物理学関係連合講演会, 2012.03.
75.	山本圭介, 山中武, 原田健司, 佐田隆宏, 坂本敬太, 小島秀太, 王冬, 中島寛, TiN ショットキー・ソース/ドレインGe n-MOSFET の作製, 第59回応用物理学関係連合講演会, 2012.03.
76.	山本圭介, 佐田隆宏, 山中武, 坂本敬太, 小島秀太, 楊海貴, 王冬, 中島寛, HfGe_x ショットキー・ソース/ドレインGe p-MOSFET の作製, 第59回応用物理学関係連合講演会, 2012.03.
77.	K. Yamamoto, R. Ueno, T. Yamanaka, K. Hirayama, H. Yang, D. Wang, H. Nakashima, High Performance of Ge MOSFETs with Bilayer-Passivated MOS Interface, 7th International Conference on Si Epitaxy and Heterostructures (ICSI7), 2011.08.
78.	山本圭介, 上野隆二, 山中武, 平山佳奈, 楊海貴, 王冬, 中島寛, 2層パッシベーション法で作製したGe-MOSFETの電気特性, 第58回応用物理学関係連合講演会, 2011.03.

所属学会名

アメリカ電気化学会

応用物理学会

学会大会・会議・シンポジウム等における役割

2023.10.23～2023.10.25, 2023 International Workshop on DIELECTRIC THIN FILMS FOR FUTURE ELECTRON DEVICES (IWDTF2023), 座長.

2023.09.19～2023.09.23, 2023年第84回応用物理学会秋季学術講演会, 座長（Chairmanship）.

2023.09.05～2023.09.08, 2023 International Conference on Solid State Device and Materials (SSDM 2023), 座長.

2023.09.05～2023.09.08, 2023 International Conference on Solid State Device and Materials (SSDM 2023), 論文委員.

2022.11.26～2022.11.27, 2022年度応用物理学会九州支部学術講演会, 座長（Chairmanship）.

2022.09.26～2022.09.29, 2022 International Conference on Solid State Device and Materials (SSDM 2022), 座長.

2022.09.26～2022.09.29, 2022 International Conference on Solid State Device and Materials (SSDM 2022), 論文委員.

2022.09.20～2022.09.23, 2022年第83回応用物理学会秋季学術講演会, 座長（Chairmanship）.

2021.12.04～2021.12.05, 2021年度応用物理学会九州支部学術講演会, 座長（Chairmanship）.

2021.09.10～2021.09.23, 2021年第82回応用物理学会秋季学術講演会, 座長（Chairmanship）.

2021.05.30～2021.06.03, 239th ECS Meeting, 座長(moderator).

2021.09.06～2021.09.09, 2021 International Conference on Solid State Device and Materials (SSDM 2021), 論文委員.

2020.09.27～2020.09.30, 2020 International Conference on Solid State Device and Materials (SSDM 2020), 座長（Chairmanship）.

2020.09.27～2020.09.30, 2020 International Conference on Solid State Device and Materials (SSDM 2020), 論文委員.

2019.09.02～2019.09.05, 2019 International Conference on Solid State Device and Materials (SSDM 2019), 座長（Chairmanship）.

2019.09.02～2019.09.05, 2019 International Conference on Solid State Device and Materials (SSDM 2019), 論文委員.

2018.12.08～2018.12.09, 平成30年度応用物理学会九州支部学術講演会, 座長（Chairmanship）.

2018.09.18～2018.09.21, 2018年第79回応用物理学会秋季学術講演会, 座長（Chairmanship）.

2018.09.09～2018.09.13, 2018 International Conference on Solid State Device and Materials (SSDM 2018), 座長（Chairmanship）.

2017.12.01～2017.12.03, 平成29年度応用物理学会九州支部学術講演会, 座長（Chairmanship）.

2017.09.19～2017.09.22, 2017 International Conference on Solid State Device and Materials (SSDM 2017), 座長（Chairmanship）.

2016.12.03～2016.12.04, 平成28年度応用物理学会九州支部学術講演会, 座長（Chairmanship）.

2016.09.26～2016.09.29, 2016 International Conference on Solid State Device and Materials (SSDM 2016), 座長（Chairmanship）.

2015.12.05～2015.12.06, 平成27年度応用物理学会九州支部学術講演会, 座長（Chairmanship）.

2018.09.09～2018.09.13, 2018 International Conference on Solid State Device and Materials (SSDM 2018), 論文委員.

2017.09.19～2017.09.22, 2017 International Conference on Solid State Device and Materials (SSDM 2017), 論文委員.

2016.09.26～2016.09.29, 2016 International Conference on Solid State Device and Materials (SSDM 2016), 論文委員.

学会誌・雑誌・著書の編集への参加状況

2022.12～2024.07, Japanese Journal of Applied Physics, IWDTF2023特集号, 国際, 責任編集委員.

2021.01～2021.12, Japanese Journal of Applied Physics, SSDM2021特集号, 国際, 編集委員.

2020.01～2020.12, Japanese Journal of Applied Physics, SSDM2020特集号, 国際, 編集委員.

2019.01～2019.12, Japanese Journal of Applied Physics, SSDM2019特集号, 国際, 編集委員.

2018.01～2018.12, Japanese Journal of Applied Physics, SSDM2018特集号, 国際, 編集委員.

学術論文等の審査

年度	外国語雑誌査読論文数	国際会議録査読論文数	合計
2024年度	2		2
2023年度	5	50	55
2022年度	3	42	45
2021年度	3	37	40
2020年度	4	31	35
2019年度	7	58	65
2018年度	3	91	94
2017年度	2	31	33
2016年度	5	38	43
2015年度	1		1
2014年度	1		1
2013年度	2		2

海外渡航状況, 海外での教育研究歴

imec, Belgium, 2019.10～2019.12.

IWDTF Best Paper Award, 2023.10.

科学研究費補助金の採択状況(文部科学省、日本学術振興会)

2024年度～2026年度, 基盤研究(C), 代表, 中空ゲルマニウム構造に基づく高性能電子・光デバイス集積化技術の開発.

2024年度～2028年度, 基盤研究(S), 分担, シリコンゲルマニウム光スピントロニクスの開拓.

2023年度～2025年度, 基盤研究(C), 分担, Ge-On-Insulator基板を利用したMIS型近赤外発光素子の研究開発.

2019年度～2023年度, 基盤研究(S), 分担, ゲルマニウムスピンMOSFETの実証.

2019年度～2020年度, 若手研究, 代表, Ge-on-Insulator基板上のSteep SlopeトンネルFETの実現.

2018年度～2020年度, 国際共同研究強化(B), 分担, 材料界面の複合顕微解析―結晶構造と電磁気特性の多元定量解析技術の開発と応用―.

2013年度～2014年度, 研究活動スタート支援, 代表, MOS界面の電荷補償による高移動度Ge MOSFETの実現.

競争的資金(受託研究を含む)の採択状況

2022年度～2023年度, JSPS二国間交流事業・共同研究（ベルギー(FWO)との共同研究）, 代表, 中空Ge基板を用いた高品質Ge-on-Insulator作製プロセスの新規開発（A new fabrication scheme for Ge on Insulator with improved material properties）.

2021年度～2023年度, 令和3-5年度東北大学電気通信研究所共同プロジェクト研究, 代表, Si・Ge混合プラットフォーム上への異種機能混載集積回路の実現.

2020年度～2025年度, NEDO・未踏チャレンジ2050, 分担, 低消費電力フレキシブルCMOSの創製.

共同研究、受託研究(競争的資金を除く)の受入状況

2020.01～2021.12, 代表, A new fabrication scheme for Ge on Insulator (NEW GOI).

学内資金・基金等への採択状況

2019年度～2020年度, 2019 年度 Progress 100 （世界トップレベル研究者招へいプログラム）・若手研究者グローバルリーダー育成型, 代表, 卓越研究員制教員（総合理工学研究院）の海外派遣.

2018年度～2018年度, 九州大学QRプログラム・わかばチャレンジ, 代表, 電子・光デバイス応用に向けたIV族半導体の高品質ヘテロエピタキシー.

2015年度～2015年度, 九州大学教育研究プログラム・研究拠点形成プロジェクト(P&P), 代表, 超低消費電力GeトンネルFET実現に向けた基盤研究.


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