Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1109/vlsicircuits18222.2020.9162826

Language：English   Publishing type：Research paper (international conference proceedings)  

Language：Japanese  

量子ハードウェアは高いエラー率を示すため，量子誤り訂正技術の実現が不可欠である．特に，表面符号は高いエラー訂正性能を持つ誤り訂正符号として注目されている．本研究では，極低温環境で動作可能なNanoBridge-FPGAへの実装を目指し，iterative greedyアルゴリズムを用いた表面符号復号器のRTL設計を行った．設計した復号器は，先行研究と同じ誤りシミュレータを用いて動作検証を行い，レイテンシ・使用リソース量の評価も行った．さらに，NanoBridge-FPGAへの論理合成・配置配線も行い，使用リソース量を確認した．
Since the error rates of existing quantum devices are high, it is essential to realize quantum error correction (QEC) techniques. In particular, surface code (SC) has attracted attention as one of the most promising error-correcting codes. In this study, we have designed an RTL surface code decoder using the iterative greedy algorithm to implement on NanoBridge-FPGA that can operate in cryogenic environments. The designed decoder was verified using the same error simulator as in the previous study, and latency and resource usage were also evaluated. In addition, we performed logic synthesis, placement and routing targeting NanoBridge-FPGA and confirmed the resource usage.

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：Institute of Electrical and Electronics Engineers (IEEE)  

The bandwidth limit between cryogenic and room-temperature environments is a critical bottleneck in superconducting noisy intermediate-scale quantum computers. This paper presents the first trial of algorithm-aware system-level optimization to solve this issue by targeting the quantum approximate optimization algorithm. Our counter-based cryogenic architecture using single-flux quantum logic shows exponential bandwidth reduction and decreases heat inflow and peripheral power consumption of inter-temperature cables, which contributes to the scalability of superconducting quantum computers.

DOI： 10.1109/lca.2023.3322700

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Language：English   Publishing type：Research paper (scientific journal)  

Language：Others   Publishing type：Research paper (scientific journal)   Publisher：Institute of Electrical and Electronics Engineers (IEEE)  

We demonstrate the functioning of a high-throughput, gate-level-pipelined floating-point adder and multiplier over 50 GHz. The gate-level-pipelined floating-point adder and multiplier requires dedicated circuit blocks to wait until other circuit blocks complete calculations because of the dependence between their sign, exponent, and significand parts. We revealed that the resultant delay difference of the waiting circuit blocks hinders high-frequency operation if the predesigned circuit blocks with the fixed clock distribution are connected in a simple manner. We showed that clock distribution needs to synchronize with every pipeline stage regardless of the circuit blocks to minimize the delay difference between the circuit blocks for circuits containing the waiting circuit blocks (e.g., the floating-point adder and multiplier). We designed a 5-bit floating-point adder and multiplier to demonstrate the effectiveness of the clock distribution experimentally. The test chips were fabricated using AIST 10-kA/cm$\boldsymbol{^{2}}$ Advanced Process 2. We verified the high-speed operation at over 50 GHz in the floating-point adder and multiplier. The maximum clock frequency and throughput of the floating-point adder were 56 GHz and 56 GFLOPS, respectively. The corresponding values for the floating-point multiplier were 63 GHz and 63 GFLOPS, respectively.

DOI： 10.1109/tasc.2023.3250614

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Language：English   Publishing type：Research paper (international conference proceedings)  

Language：English   Publishing type：Research paper (scientific journal)   Publisher：Information Processing Society of Japan  

<p>This paper analyzes the impact of input sparsity and DFS/DVFS configurations for single-board computers on the execution time, power, and energy of each VGG16 layer as the first step towards efficient CNN inference on single-board computers. For this purpose, we first develop a power and execution time measurement environment and perform experiments using Raspberry Pi 4 and NVIDIA Jetson Nano. Our results show that clock frequency strongly correlates with execution time and power. Inversely, input sparsity has a weak correlation with execution time and power. Then, we show that a coarse-grained DVFS model can explain over 96% of the variations in the power of each VGG16 layer even when sets of clock frequency and voltage on the single-board computer are unavailable.</p>

DOI： 10.2197/ipsjjip.31.478

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Publishing type：Research paper (international conference proceedings)   Publisher：Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC  

Large error rates of quantum bits (qubits) are one of the main difficulties in the development of quantum computing. Performing quantum error correction (QEC) with surface codes is considered the most promising approach to reduce the error rates of qubits effectively. To perform error correction, we need an error-decoding unit, which estimates errors in the noisy physical qubits repetitively, to create a robust logical qubit. While complicated graph-matching problems must be solved within a strict time restriction for the error decoding, several hardware implementations that satisfy the restriction at a large code distance have been proposed. However, the existing decoder designs are still challenging in reducing the logical error rate. This is because they assume that the error rates of physical qubits are uniform while they have large variations in practice. According to our numerical simulation based on the quantum chip with the largest qubit number, neglecting the non-uniform error properties of a real quantum chip in the decoding process induces significant degradation of the logical error rate and spoils the benefit of QEC. To take the non-uniformity into account, decoders need to solve matching problems on a weighted graph, but they are difficult to solve using the existing designs without exceeding the time limit of decoding. Therefore, a decoder that can treat both the non-uniform physical error rates and the large surface code is strongly demanded. In this paper, we propose a hardware design of decoding units for the surface code that can treat the non-identical error properties with small latency at a large code distance. The key idea of our design is 1) constructing a look-up table for calculating the shortest paths between nodes in a weighted graph and 2) enabling parallel processing during decoding. The implementation results in field programmable gate array (FPGA) indicate that our design scales up to code distance 11 within a microsecond-level delay, which is comparable to the existing state-of-the-art designs, while our design can treat non-identical errors.

DOI： 10.1145/3566097.3567933

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Other Link： https://dblp.uni-trier.de/db/conf/aspdac/aspdac2023.html#LiaoSTUT23

Language：Others   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

Recently IoT edge devices have become more diverse and lower cost. In addition, small low-power single-board computers' computing performance has significantly increased. These conditions make it possible to process locally without communicating to the cloud. Since the advantages of in-edge processing are security and privacy, we applied in-edge IoT to smart homes with rich private information to be secured. In in-edge processing, conventional cloud-managed abnormality monitoring and system maintenance cannot be involved. We developed a lamp control system with in-edge processing. It detects failures using camera image processing and recovers from the failure. The abnormalities of the image processing are detected by monitoring cyclic outdoor brightness change observed on windows captured with the same camera. We have developed a prototype system with Python with OpenCV and FastAPI, etc., over PHP-based lamp timer control while keeping source code size small and considering validation easiness. The camera detectors work at 10 FPS on Python with as small as 1607 total source code lines (three times of code lines against the original lamp control timer).

DOI： 10.1109/wf-iot54382.2022.10152281

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Publisher：Proceedings - IEEE International Symposium on Circuits and Systems  

This paper presents the design of an ultra-high-speed, low-power arithmetic unit that supports variable bit-width operations with single flux quantum (SFQ) technology. Because of the high-speed nature of superconductor devices, we can achieve extremely high power-performance efficiency that cannot be achieved by state-of-the-art CMOS devices. To implement the complex function to support the variable bit-width feature, we introduce a novel circuit architecture to maintain the high-speed operation over 50GHz. Our prototype chip design successfully demonstrated 53.5GHz 1.59mW operations.

DOI： 10.1109/ISCAS48785.2022.9937317

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Publishing type：Research paper (international conference proceedings)   Publisher：Proceedings - International Symposium on Computer Architecture  

10+K qubit quantum computer is essential to achieve a true sense of quantum supremacy. With the recent effort towards the large-scale quantum computer, architects have revealed various scalability issues including the constraints in a quantum control processor, which should be holistically analyzed to design a future scalable control processor. However, it has been impossible to identify and resolve the processor's scalability bottleneck due to the absence of a reliable tool to explore an extensive design space including microarchitecture, device technology, and operating temperature. In this paper, we present XQsim, an open-source cross-technology quantum control processor simulator. XQsim can accurately analyze the target control processors' scalability bottlenecks for various device technology and operating temperature candidates. To achieve the goal, we frst fully implement a convincing control processor microarchitecture for the Fault-tolerant Quantum Computer (FTQC) systems. Next, on top of the microarchitecture, we develop an architecture-level control processor simulator (XQsim) and thoroughly validate it with post-layout analysis, timing-accurate RTL simulation, and noisy quantum simulation. Lastly, driven by XQsim, we provide the future directions to design a 10+K qubit quantum control processor with several design guidelines and architecture optimizations. Our case study shows that the fnal control processor architecture can successfully support ~59K qubits with our operating temperature and technology choices.

DOI： 10.1145/3470496.3527417

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Other Link： https://dblp.uni-trier.de/db/conf/isca/isca2022.html#ByunKMNFITTIK22

Authorship：Last author   Publishing type：Research paper (international conference proceedings)   Publisher：Proceedings of the Annual International Symposium on Microarchitecture, MICRO  

Demonstrating small error rates by integrating quantum error correction (QEC) into an architecture of quantum computing is the next milestone towards scalable fault-tolerant quantum computing (FTQC). Encoding logical qubits with superconducting qubits and surface codes is considered a promising candidate for FTQC architectures. In this paper, we propose an FTQC architecture, which we call Q3DE, that enhances the tolerance to multi-bit burst errors (MBBEs) by cosmic rays with moderate changes and overhead. There are three core components in Q3DE: in-situ anomaly DEtection, dynamic code DEformation, and optimized error DEcoding. In this architecture, MBBEs are detected only from syndrome values for error correction. The effect of MBBEs is immediately mitigated by dynamically increasing the encoding level of logical qubits and re-estimating probable recovery operation with the rollback of the decoding process. We investigate the performance and overhead of the Q3DE architecture with quantum-error simulators and demonstrate that Q3DE effectively reduces the period of MBBEs by 1000 times and halves the size of their region. Therefore, Q3DE significantly relaxes the requirement of qubit density and qubit chip size to realize FTQC. Our scheme is versatile for mitigating MBBEs, i.e., temporal variations of error properties, on a wide range of physical devices and FTQC architectures since it relies only on the standard features of topological stabilizer codes.

DOI： 10.1109/MICRO56248.2022.00079

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Other Link： https://dblp.uni-trier.de/db/conf/micro/micro2022.html#SuzukiSALIT22

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1109/isvlsi49217.2020.00060

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1109/isvlsi49217.2020.00059

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1145/3368474.3368491

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1587/transfun.e102.a.758

Language：English   Publishing type：Research paper (scientific journal)  

The dependence graph model of out-of-order (OoO) instruction execution is a powerful representation used for the critical path analysis. However, most, if not all, of the previous models are out-of-date and lack enough detail to model modern OoO processors, or are too specific and complicated which limit their generality and applicability. In this paper, we propose an enhanced dependence graph model which remains simple but greatly improves the accuracy over prior models. The evaluation results using the gem5 simulator with configurations similar to Intel’s Haswell and Silvermont architecture show that the proposed enhanced model achieves CPI errors of 2.1% and 4.4% which are 90.3% and 77.1% improvements from the state-of-the-art model.

DOI： 10.2197/ipsjjip.25.983

Language：English   Publishing type：Research paper (other academic)  

CPCI Stack: Metric for Accurate Bottleneck Analysis on OoO Microprocessors

DOI： 10.1109/CANDAR.2017.60

Language：English   Publishing type：Research paper (international conference proceedings)  

Language：English   Publishing type：Research paper (scientific journal)  

The dependence graph model of out-of-order (OoO) instruction execution is a powerful representation used for the critical path analysis. However most, if not all, of the previous models are out-of-date and lack enough detail to model modern OoO processors, or are too specific and complicated which limit their generality and applicability. In this paper, we propose an enhanced dependence graph model which remains simple but greatly improves the accuracy over prior models. The evaluation results using the gem5 simulator show that the proposed enhanced model achieves CPI error of 2.1 percent which is a 90.3 percent improvement against the state-of-the-art model.

DOI： 10.1109/LCA.2017.2684813

Language：English   Publishing type：Research paper (scientific journal)  

Designing and optimizing computer systems require deep understanding of the underlying system behavior. Historically many important observations that led to the development of essential hardware and software optimizations were driven by empirical observations about program behavior. In this paper, we report an interesting property of program structures by viewing dynamic program execution as a changing network. By analyzing the communication network created as a result of dynamic program execution, we find that communication patterns follow heavy-tailed distributions. In other words, a few instructions have consumers that are orders of magnitude larger than most instructions in a program. Surprisingly, these heavy-tailed distributions follow the iconic power law previously seen in man-made and natural networks. We provide empirical measurements based on the SPEC CPU2006 benchmarks to validate our findings as well as perform semantic analysis of the source code to reveal the causes of such behavior.

DOI： 10.1109/LCA.2016.2574350

Language：English   Publishing type：Research paper (scientific journal)  

Big data analysis and a data storing applications require a huge volume of storage and a high I/O performance. Applications can achieve high level of performance and cost efficiency by exploiting the high I/O performance of direct attached storages (DAS) such as internal HDDs. With the size of stored data ever increasing, it will be difficult to replace servers since internal HDDs contain huge amounts of data. Generally, the data is copied via Ethernet when transferring the data from the internal HDDs to the new server. However, the amount of data will continue to rapidly increase, and thus, it will be hard to make these types of transfers through the Ethernet since it will take a long time. A storage area network such as iSCSI can be used to avoid this problem because the data can be shared with the servers. However, this decreases the level of performance and increases the costs. Improving the flexibility without incurring I/O performance degradation is required in order to improve the DAS architecture. In response to this issue, we propose FlexDAS, which improves the flexibility of direct attached storage by using a disk area network (DAN) without degradation the I/O performance. A resource manager connects or disconnects the computation nodes to the HDDs via the FlexDAS switch, which supports the SAS or SATA protocols. This function enables for the servers to be replaced in a short period of time. We developed a prototype FlexDAS switch and quantitatively evaluated the architecture. Results show that the FlexDAS switch can disconnect and connect the HDD to the server in just 1.16 seconds. We also confirmed that the FlexDAS improves the performance of the data intensive applications by up to 2.84 times compared with the iSCSI.

DOI： 10.1587/transinf.2015PAP0029

Language：English   Publishing type：Research paper (international conference proceedings)  

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Venue：Echigoyuzawa   Country：Japan  

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Venue：和光市   Country：Japan  

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Type：Peer review 

Number of peer-reviewed articles in foreign language journals：3

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Number of participants：50

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Number of peer-reviewed articles in foreign language journals：1

Proceedings of International Conference Number of peer-reviewed papers：6