Faculty Profiles - CHEN OLIVIA

写真a

CHEN OLIVIA

Organization

Faculty of Information Science and Electrical Engineering Department of Advanced Information Technology Associate Professor
Joint Graduate School of Mathematics for Innovation （Concurrent）
School of Engineering Department of Electrical Engineering and Computer Science（Concurrent）
Graduate School of Information Science and Electrical Engineering Department of Information Science and Technology（Concurrent）

Contact information

Homepage

https://oliviachen.info

External link

Research Areas

Informatics / Computer system
Manufacturing Technology (Mechanical Engineering, Electrical and Electronic Engineering, Chemical Engineering) / Electron device and electronic equipment

Degree

Ph.D.

Research History

University of California, Riverside Department of Electrical and Computer Engineering Visiting Associate Professor

2024.5 - Present

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Country：United States

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Kyushu University Faculty of Information Science and Electrical Engineering

2024.4 - Present

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Yokohama National University Institute of Advanced Sciences Visiting Associate Professor

2021.4 - Present

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Tokyo City University Department of Computer Sciences Associate Professor

2021.4 - 2024.3

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Research Interests・Research Keywords

Research theme： Beyond CMOS

Keyword： Beyond CMOS

Research period： 2024
Research theme： EDA

Keyword： EDA

Research period： 2024
Research theme： Superconducting electronics

Keyword： Superconducting electronics

Research period： 2024
Research theme： VLSI

Keyword： VLSI

Research period： 2024

Awards

2023 Van Duzer Prize Award

2024.9 IEEE Council on Superconductivity

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優秀研究賞

2023.9 東京都市大学
優秀研究賞

2023.9 東京都市大学

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外部資金獲得研究者表彰

2020.6 横浜国立大学
米低温学会2019年度若手プロフェッショナル

2019.3 米低温学会 2019 Young Professional by Cryogenic Society of America
SNF Contest for Best ASC 2016 Contributed Preprints

2017.1 IEEE CSC SNF Contest for Best ASC 2016 Contributed Preprints
日揮・実吉奨学金

2013.4 日揮・実吉奨学会

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Papers

SuperSIM: A comprehensive benchmarking framework for neural networks using superconductor josephson devices

Guangxian Zhu, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima, Wenhui Luo, Naoki Takeuchi, Nobuyuki Yoshikawa, Olivia Chen

Superconductor Science and Technology 37 ( 9 ) 2024.9 （ ISSN:0953-2048 eISSN:1361-6668 ）

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Publishing type：Research paper (scientific journal) Publisher：IOP Publishing

Abstract

This paper introduces SuperSIM, a benchmarking framework tailored for neural networks using superconducting Josephson devices, specifically focusing on Adiabatic Quantum Flux Parametron (AQFP) based Processing-in-Memory (PIM) architectures. Our framework offers in-depth architecture-level simulations and performance assessments to enhance AQFP PIM chip development. It supports single and multi-bit PIM designs, various AQFP memory cell types, and diverse clocking methods. Additionally, it integrates circuit-level models for precise energy, delay, and area measurements, ensuring accurate performance evaluation. The framework includes application, device, and architectural layers for versatile configurations and cycle-accurate energy, latency, and area simulations. Experiments validate our framework, with case studies on algorithm and architecture-level features, examining data precision, crossbar size, operating frequency and clocking scheme impacts on computational accuracy, energy use, overall latency and hardware cost.

DOI： 10.1088/1361-6668/ad6d9e

Web of Science

Scopus

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Other Link： https://iopscience.iop.org/article/10.1088/1361-6668/ad6d9e/pdf
Dual-mode neuron design with deterministic and non-deterministic operations using adiabatic superconductor devices

Tomoharu Yamauchi, Naoki Takeuchi, Nobuyuki Yoshikawa, Hao San, Olivia Chen

Superconductor Science and Technology 37 ( 9 ) 095027 - 095027 2024.8 （ ISSN:0953-2048 eISSN:1361-6668 ）

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Publishing type：Research paper (scientific journal) Publisher：IOP Publishing

Abstract

In this research, we unveil an innovative strategy in neuromorphic computing by developing a neuron model tailored for the energy-efficient Adiabatic Quantum-Flux-Parametron (AQFP) logic. This model is particularly aimed at enhancing neural network accelerators. Our design of the AQFP-based neuron operates effectively in both deterministic and non-deterministic modes. In deterministic mode, the design relies on superconducting inductive coupling to activate neurons by comparing the sum of AQFP signal currents against a tunable threshold. For non-deterministic operation, we demonstrate how altering specific circuit parameters can correlate these aggregated currents with the non-deterministic operational range of an AQFP current comparator. We verified its versatility and functionality by fabricating varied circuits and conducting extensive tests, confirming its practical application potential. Our work not only showcases the practical implementation of AQFP in neuromorphic computing but also sets a foundation for future advancements in energy-efficient AI hardware.

DOI： 10.1088/1361-6668/ad55ce

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Other Link： https://iopscience.iop.org/article/10.1088/1361-6668/ad55ce/pdf
The ATLAS experiment at the CERN Large Hadron Collider: a description of the detector configuration for Run 3

Amerl M., Filmer E.K., Jackson P., Kong A.X.Y., Potti H., Ruggeri T.A., Ting E.X.L., White M.J., Davis P.M., Gingrich D.M., Lindon J.H., Nishu N., Pinfold J.L., Soluk R., Cakir O., Duran Yildiz H., Kuday S., Turk Cakir I., Sultansoy S., Adam Bourdarios C., Ballansat J., Bellachia F., Berger N., Bouedo T., Cap S., Chevillot N., Costanza F., David P., Delebecque P., Delmastro M., Di Ciaccio L., Dumont Dayot N., Elles S., Fragnaud J.C., Gantel L.M., Goy C., Guillemin T., Hryn'ova T., Jézéquel S., Koletsou I., Lafrasse S., Levêque J., Lewis D.J., Little J.D., Lorenzo Martinez N., Massol N., Perrot G., Poddar G., Rossi E., Sanchez Pineda A., Sauvan E., Selem L., Todorov T., Wingerter-Seez I., Bernardi G., Bomben M., Bouquet R., Di Gregorio G., Li A., Marchiori G., Shen Q., Zhang Y., Chekanov S., Darmora S., Hopkins W.H., Hoya J., Kourlitis E., LeCompte T., Love J., Luz R.J., Metcalfe J., Mete A.S., Paramonov A., Proudfoot J., Trovato M., Van Gemmeren P., Wang R., Zhang J., Armijo C.E., Berlendis S., Cheu E., Cui Z., Ghosh A., Gigliotti K., Johns K.A., Lampl W., Lindley R.E., Loch P., Rutherfoord J.P., Sardain J., Scott G.J., Solis M.A., Tompkins D., Varnes E.W., Walker R.W., Zhou H., Zhou Y., Abdallah J., Bakshi Gupta D., Burghgrave B.

Journal of Instrumentation 19 ( 5 ) 2024.5

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Publisher：Journal of Instrumentation

The ATLAS detector is installed in its experimental cavern at Point 1 of the CERN Large Hadron Collider. During Run 2 of the LHC, a luminosity of ℒ = 2 × 1034 cm-2 s-1 was routinely achieved at the start of fills, twice the design luminosity. For Run 3, accelerator improvements, notably luminosity levelling, allow sustained running at an instantaneous luminosity of ℒ = 2 × 1034 cm-2 s-1, with an average of up to 60 interactions per bunch crossing. The ATLAS detector has been upgraded to recover Run 1 single-lepton trigger thresholds while operating comfortably under Run 3 sustained pileup conditions. A fourth pixel layer 3.3 cm from the beam axis was added before Run 2 to improve vertex reconstruction and b-tagging performance. New Liquid Argon Calorimeter digital trigger electronics, with corresponding upgrades to the Trigger and Data Acquisition system, take advantage of a factor of 10 finer granularity to improve triggering on electrons, photons, taus, and hadronic signatures through increased pileup rejection. The inner muon endcap wheels were replaced by New Small Wheels with Micromegas and small-strip Thin Gap Chamber detectors, providing both precision tracking and Level-1 Muon trigger functionality. Trigger coverage of the inner barrel muon layer near one endcap region was augmented with modules integrating new thin-gap resistive plate chambers and smaller-diameter drift-tube chambers. Tile Calorimeter scintillation counters were added to improve electron energy resolution and background rejection. Upgrades to Minimum Bias Trigger Scintillators and Forward Detectors improve luminosity monitoring and enable total proton-proton cross section, diffractive physics, and heavy ion measurements. These upgrades are all compatible with operation in the much harsher environment anticipated after the High-Luminosity upgrade of the LHC and are the first steps towards preparing ATLAS for the High-Luminosity upgrade of the LHC. This paper describes the Run 3 configuration of the ATLAS detector.

DOI： 10.1088/1748-0221/19/05/P05063

Scopus
Buffer and Splitter Insertion for Adiabatic Quantum-Flux-Parametron Circuits

Fu R., Wang M., Kan Y., Chen O., Yoshikawa N., Yu B., Ho T.Y.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2024 （ ISSN:02780070 ）

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Publisher：IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

The extremely low-bit energy characteristic of the adiabatic quantum-flux-parametron (AQFP) circuit makes it a promising candidate for highly energy-efficient computing systems. However, by contrast with conventional circuit design, general logic synthesis tools can not make sure that the circuit functionality of generated AQFP circuits is correct. AQFP circuits require buffer and splitter insertion for dataflow synchronization at all clock phases of the circuit and multi-fan-out driving. Notably, buffers and splitters inserted take up much area and delay in AQFP circuits, also causing a significant increase in energy dissipation. To address this problem, this paper analyzes in detail why buffer and splitter insertion is necessary for AQFP circuits and proposes a global optimization framework for this purpose. This framework consists of three parts: (i) logic level assignment, (ii) splitter tree generation, and (iii) buffer insertion. An integer linear programming algorithm is proposed for the logic level assignment to estimate the globally optimal number of inserted buffers and splitters. Subsequently, a dynamic programming-based multi-way search tree generation algorithm is proposed to construct an optimal splitter tree for each net of the input circuit. Moreover, three optimization strategies are proposed to further enhance the effectiveness and efficiency of our framework. Experimental results on ISCAS'85 and EPFL benchmarks demonstrate the effectiveness and efficiency of our proposed framework compared with the state-of-the-art, particularly with significant advantages on large circuits.

DOI： 10.1109/TCAD.2024.3461573

Scopus
Design and Implementation of Energy-Efficient Binary Neural Networks Using Adiabatic Quantum-Flux-Parametron Logic

Tomoharu Yamauchi, Hao San, Nobuyuki Yoshikawa, Olivia Chen

IEEE Transactions on Applied Superconductivity 33 ( 5 ) 1 - 5 2023.8 （ ISSN:1051-8223 eISSN:1558-2515 ）

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Language：Others Publishing type：Research paper (scientific journal) Publisher：Institute of Electrical and Electronics Engineers (IEEE)

DOI： 10.1109/tasc.2023.3243180

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A Global Optimization Algorithm for Buffer and Splitter Insertion in Adiabatic Quantum-Flux-Parametron Circuits.

Rongliang Fu, Mengmeng Wang, Yirong Kan, Nobuyuki Yoshikawa, Tsung-Yi Ho, Olivia Chen

Proceedings of the 28th Asia and South Pacific Design Automation Conference(ASP-DAC) 769 - 774 2023 （ ISBN:9781450397834 ）

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Publishing type：Research paper (international conference proceedings) Publisher：ACM

DOI： 10.1145/3566097.3567936

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Other Link： https://dblp.uni-trier.de/rec/conf/aspdac/2023
A Life-Cycle Energy and Inventory Analysis of Adiabatic Quantum-Flux-Parametron Circuits.

Masoud Zabihi, Yanyue Xie, Zhengang Li, Peiyan Dong, Geng Yuan, Olivia Chen, Massoud Pedram, Yanzhi Wang

CoRR abs/2307.12216 2023

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Publishing type：Research paper (scientific journal)

DOI： 10.48550/arXiv.2307.12216

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BOMIG: A Majority Logic Synthesis Framework for AQFP Logic.

Rongliang Fu, Junying Huang, Mengmeng Wang, Nobuyuki Yoshikawa, Bei Yu 0001, Tsung-Yi Ho, Olivia Chen

Design(DATE) 1 - 2 2023 （ ISBN:9783981926378 ）

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Publishing type：Research paper (international conference proceedings) Publisher：IEEE

DOI： 10.23919/DATE56975.2023.10137075

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Other Link： https://dblp.uni-trier.de/db/conf/date/date2023.html#FuHWYYHC23
Design and Implementation of an FFT-Based Neural Network Accelerator Using Rapid Single-Flux-Quantum Technology.

Olivia Chen, Yanzhi Wang, Fei Ke, Nobuyuki Yoshikawa

NEWCAS 1 - 5 2023

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Publishing type：Research paper (international conference proceedings)

DOI： 10.1109/NEWCAS57931.2023.10198178

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Other Link： https://dblp.uni-trier.de/db/conf/newcas/newcas2023.html#ChenWKY23
Invited: Algorithm-Software-Hardware Co-Design for Deep Learning Acceleration.

Zhengang Li, Yanyue Xie, Peiyan Dong, Olivia Chen, Yanzhi Wang

DAC 1 - 4 2023

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Publishing type：Research paper (international conference proceedings)

DOI： 10.1109/DAC56929.2023.10247939

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Other Link： https://dblp.uni-trier.de/db/conf/dac/dac2023.html#LiXDCW23
Performance Assessment of an Extremely Energy-Efficient Binary Neural Network Using Adiabatic Superconductor Devices.

Olivia Chen, Zhengang Li, Tomoharu Yamauchi, Yanzhi Wang, Nobuyuki Yoshikawa

AICAS 1 - 5 2023

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Publishing type：Research paper (international conference proceedings)

DOI： 10.1109/AICAS57966.2023.10168607

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Other Link： https://dblp.uni-trier.de/db/conf/aicas/aicas2023.html#ChenLYWY23
Sigmoid function generator using stochastic adiabatic superconductor logic

Luo, W., Chen, O., Yoshikawa, N., Takeuchi, N.

Applied Physics Letters 122 ( 24 ) 2023 （ ISSN:0003-6951 ）

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Publishing type：Research paper (scientific journal)

DOI： 10.1063/5.0154712

Scopus

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Scalable true random number generator using adiabatic superconductor logic. International journal

Wenhui Luo, Olivia Chen, Nobuyuki Yoshikawa, Naoki Takeuchi

Scientific reports 12 ( 1 ) 20039 - 20039 2022.11

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Language：English Publishing type：Research paper (scientific journal)

Alternative computing such as stochastic computing and bio-inspired computing holds promise for overcoming the limitations of von Neumann computers. However, one difficulty in the implementation of such alternative computing is the need for a large number of random bits at the same time. To address this issue, we propose a scalable true-random-number generating scheme that we refer to as XORing shift registers (XSR). XSR generates multiple uncorrelated true random bitstreams using only two true random number generators as entropy sources and can thus be implemented by a variety of logic devices. Toward superconducting alternative computing, we implement XSR using an energy-efficient superconductor logic family, adiabatic quantum-flux-parametron (AQFP) logic. Furthermore, to demonstrate its performance, we design and observe an AQFP-based XSR circuit that generates four random bitstreams in parallel. The results of the experiment confirm that the bitstreams generated by the XSR circuit exhibit no autocorrelation and that there is no correlation between the bitstreams.

DOI： 10.1038/s41598-022-24230-5

PubMed

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A Global Buffer and Splitter Insertion Algorithm in AQFP Circuits Reviewed

Rongliang Fu, Mengmeng Wang, Yirong Kan, Olivia Chen, Nobuyuki Yoshikawa, Tsung-Yi Ho

Proc. The 24th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2022) 85 - 90 2022.10

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A Global Buffer and Splitter Insertion Algorithm in AQFP Circuits
A Neural Network Processing Unit Using Adiabatic Quantum-Flux-Parametron Superconducting Technology Invited Reviewed

Mengmeng Wang, Olivia Chen, Nobuyuki Yoshikawa

Proc. of IEEE GCCE 2022 2022.10

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A Neural Network Processing Unit Using Adiabatic Quantum-Flux-Parametron Superconducting Technology
A Study on the Efficient Design of Adders Adiabatic Quantum-Flux-Parametron Circuits Reviewed

Tomoharu Yamauchi, Hao San, Nobuyuki Yoshikawa, Olivia Chen

Proc. of IEEE GCCE 2022 2022.10

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A Study on the Efficient Design of Adders Adiabatic Quantum-Flux-Parametron Circuits
A Global Buffer and Splitter Insertion Algorithm in AQFP Circuits Reviewed

Rongliang Fu, Mengmeng Wang, Yirong Kan, Olivia Chen, Nobuyuki Yoshikawa, Tsung-Yi Ho

Proc. The 24th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2022) 85 - 90 2022.10

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A Neural Network Processing Unit Using Adiabatic Quantum-Flux-Parametron Superconducting Technology Invited Reviewed

Mengmeng Wang, Olivia Chen, Nobuyuki Yoshikawa

Proc. of IEEE GCCE 2022 2022.10

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Authorship：Corresponding author

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A Study on the Efficient Design of Adders Adiabatic Quantum-Flux-Parametron Circuits Reviewed

Tomoharu Yamauchi, Hao San, Nobuyuki Yoshikawa, Olivia Chen

Proc. of IEEE GCCE 2022 2022.10

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Authorship：Last author,　Corresponding author

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A Study on In-Memory Binary Neural Networks Using Adiabatic Quantum-Flux-Parametron Logic

Tomoharu Yamauchi, Hao San, Nobuyuki Yoshikawa, Olivia Chen

Proc. 14th Superconducting SFQ VLSI Workshop (SSV 2022) 2022.9

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A Study on In-Memory Binary Neural Networks Using Adiabatic Quantum-Flux-Parametron Logic
A Study on In-Memory Binary Neural Networks Using Adiabatic Quantum-Flux-Parametron Logic

Tomoharu Yamauchi, Hao San, Nobuyuki Yoshikawa, Olivia Chen

Proc. 14th Superconducting SFQ VLSI Workshop (SSV 2022) 2022.9

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Design and Implementation of Stochastic Neural Networks Using Superconductor Quantum-Flux-Parametron Devices.

Olivia Chen, Yanzhi Wang, Renyuan Zhang, Nobuyuki Yoshikawa

SOCC 1 - 6 2022

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Authorship：Lead author,　Corresponding author Publishing type：Research paper (international conference proceedings)

DOI： 10.1109/SOCC56010.2022.9908075

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Other Link： https://dblp.uni-trier.de/db/conf/socc/socc2022.html#ChenWZY22
TAAS: a timing-aware analytical strategy for AQFP-capable placement automation.

Peiyan Dong, Yanyue Xie, Hongjia Li, Mengshu Sun, Olivia Chen, Nobuyuki Yoshikawa, Yanzhi Wang

DAC 1321 - 1326 2022

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Publishing type：Research paper (international conference proceedings)

DOI： 10.1145/3489517.3530487

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Other Link： https://dblp.uni-trier.de/db/conf/dac/dac2022.html#DongXLSCYW22
Low-Autocorrelation Random Number Generator Based on Adiabatic Quantum-Flux-Parametron Logic Reviewed

Wenhui Luo, Naoki Takeuchi, Olivia Chen, Nobuyuki Yoshikawa

IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY 31 ( 5 ) 2021.8

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Language：English Publishing type：Research paper (scientific journal)

We propose a true random number generator (TRNG) based on adiabatic quantum-flux-parametron (AQFP) logic. This AQFP TRNG corresponds to an AQFP buffer chain with the input current removed, which enables the generation of random bits via thermal fluctuation. To realize ultralow autocorrelation, several isolation inductors are inserted between adjacent buffers in the AQFP TRNG, thereby reducing the impact of the back action between buffers. We design and fabricate an AQFP TRNG using the AIST 10 kA/cm(2) Nb high-speed standard process and evaluate the quality of the generated random bit streams. For a 217-bit random stream obtained from the AQFP TRNG at 100 kHz, the autocorrelation function is 5.00x10(-3). Furthermore, we evaluate a 220-bit random stream from the AQFP TRNG using a statistical test suite provided by the National Institute of Standards and Technology. The bit stream passed 14 out of 15 tests, which suggests that the proposed AQFP TRNG can be used for applications such as stochastic computing and stochastic local search algorithms.

DOI： 10.1109/TASC.2021.3070460
Demonstration of a 47.8 GHz High-Speed FFT Processor Using Single-Flux-Quantum Technology Reviewed

Fei Ke, Olivia Chen, Yanzhi Wang, Nobuyuki Yoshikawa

IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY 31 ( 5 ) 2021.8

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Language：English Publishing type：Research paper (scientific journal)

A fast Fourier transform (FFT) is an algorithm that computes the discrete Fourier transform (DFT) of a sequence at high speed. FFT can convert a signal from time domain to frequency domain, and is wildly used in digital signal processing field. In this paper, a high-speed, low-power FFT processor is demonstrated up to 47.8GHz with the measured power consumption of 5.3mW, using single-flux quantum (SFQ) logic. This is the first complete FFT processor implementation using superconducting technology, performing 8-point 7-bit FFT in a bit-serial computing manner. The test chip fabricated using a 1.0 mu m 9-layer process consists of 17 455 Nb/AlOx/Nb Josephson junctions (JJs), rendering itself the largest superconducting digital circuit capable of iterative data computing. The correct operation of the chip has been experimentally confirmed at a maximum operating frequency of 47.8GHz (word speed 8GHz) by conducting on-chip high-speed testing.

DOI： 10.1109/TASC.2021.3059984
Logic Synthesis of Sequential Logic Circuits for Adiabatic Quantum-Flux-Parametron Logic Reviewed

Ro Saito, Christopher L. Ayala, Olivia Chen, Tomoyuki Tanaka, Tomohiro Tamura, Nobuyuki Yoshikawa

IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY 31 ( 5 ) 2021.8

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Language：English Publishing type：Research paper (scientific journal)

The adiabatic quantum-flux-parametron (AQFP) superconductor logic family has the potential to be the electronics groundwork for energy-efficient large-scale computing. To this end, we have been developing an AQFP top-down design flow, and our design efficiency has improved recently for combinational logic circuits. As a next step, we establish a methodology to synthesize sequential logic circuits which we previously did not consider. In this paper, we describe our sequential logic circuit model and how it can be used to map the sequential elements of an RTL (register transfer level) behavioral design. Next we discuss the structure of sequential circuits in more detail using a benchmark of N-bit counters. Lastly, we show some preliminary results of a synthesized 16 bit MIPS microprocessor. During this study, we also developed an architectural retiming methodology to reduce the number of synchronization buffers needed for microprocessor pipeline stage balancing.

DOI： 10.1109/TASC.2021.3061636
Towards AQFP-Capable Physical Design Automation Reviewed

Hongjia Li, Mengshu Sun, Tianyun Zhang, Olivia Chen, Nobuyuki Yoshikawa, Bei Yu, Yanzhi Wang, Yibo Lin

2021 Design, Automation & Test in Europe Conference & Exhibition (DATE) 954 - 959 2021.5

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Study of clock synchronization for high-level synthesis of adiabatic quantum-flux-parametron sequential logic circuits

R. Saito, C. L. Ayala, O. Chen, T. Tanaka, T. Tamura, and N. Yoshikawa

ASC 2020 2020.10

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Study of clock synchronization for high-level synthesis of adiabatic quantum-flux-parametron sequential logic circuits
Improvement for autocorrelation of adiabatic quantum-flux-parametron based random number generator

Wenhui Luo, Naoki Takeuchi, Olivia Chen, Nobuyuki Yoshikawa

120 ( 153 ) 17 - 20 2020.8

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A semi-custom design methodology and environment for implementing superconductor adiabatic quantum-flux-parametron microprocessors Reviewed

Ayala Christopher L, Saito Ro, Tanaka Tomoyuki, Chen Olivia, Takeuchi Naoki, He Yuxing, Yoshikawa Nobuyuki

SUPERCONDUCTOR SCIENCE & TECHNOLOGY 33 ( 5 ) 2020.5

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Language：English Publishing type：Research paper (scientific journal)

A semi-custom design methodology and environment for implementing superconductor adiabatic quantum-flux-parametron microprocessors

DOI： 10.1088/1361-6668/ab7ec3
Design of SFQ convolutional computation processor for convolutional neural network

Fei Ke, Ao Ren, Yanzhi Wang, Olivia Chen, Yuki Yamanashi, Nobuyuki Yoshikawa

119 ( 369 ) 11 - 13 2020.1

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Methodology for Au- tomating Data Feedback Circuit Synthesis for a 4- bit Counter in Adiabatic Quantum- Flux-Parametron Logic

R. Saito, C. L. Ayala, O. Chen, T. Tanaka, N. Yoshikawa

Proc. The 13th Superconducting SFQ VLSI Workshop (SSV) 2020 119 ( 369 ) 117 - 119 2020.1

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Methodology for Automating Data Feedback Circuit Synthesis for a 4-bit Counter in Adiabatic Quantum-Flux-Parametron Logic
Development of Majority- Logic-Based Top-Down Environment for Adiabatic Quantum-FluxParametron Circuits

R. Saito, C. L. Ayala, O. Chen, T. Tanaka, N. Yoshikawa

Proc. 32nd International Symposium on Superconductivity (ISS2019) 2019.11

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Development of Majority- Logic-Based Top-Down Environment for Adiabatic Quantum-FluxParametron Circuits
A Feedback-Friendly Large-Scale Clocking Scheme for Adiabatic Quantum-Flux-Parametron Logic Datapaths Reviewed

Takeuchi Naoki, Ayala Christopher Lawrence, Chen Olivia, Yoshikawa Nobuyuki

IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY 29 ( 5 ) 2019.8

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Language：Japanese Publishing type：Research paper (scientific journal)

DOI： 10.1109/TASC.2019.2904480
Quality of Results of Adi- abatic Quantum-Flux-Parametron Integrated Circuits Placed by the Genetic Algorithm

T. Tanaka, C. L. Ayala, O. Chen, R. Saito, N. Yoshikawa

Proc. International Superconductive Electronics Conference(ISEC) 2019 2019.7

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Quality of Results of Adi- abatic Quantum-Flux-Parametron Integrated Circuits Placed by the Genetic Algorithm
Adiabatic Quantum-Flux-Parametron: Towards Building Extremely Energy-Efficient Circuits and Systems Reviewed

Olivia Chen, Ruizhe Cai, Yanzhi Wang, Fei Ke, Taiki Yamae, Ro Saito, Naoki Takeuch, Nobuyuki Yoshikawa

Scientific Reports Vol.9 ( 1 ) 2019.7

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Language：English Publishing type：Research paper (scientific journal)

Adiabatic Quantum-Flux-Parametron: Towards Building Extremely Energy-Efficient Circuits and Systems

DOI： 10.1038/s41598-019-46595-w
Development of Topdown Environment for Adiabatic Quantum Flux Parametron Circuits

RO SAITO, Christopher AYALA, Olivia CHEN, TOMOYUKI TANAKA, NOBUYUKI YOSHIKAWA

電気学会研究会資料 ( MC-19-001-012/ASC-19-007-018 ) 9 - 12 2019.7

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Design of Adiabatic Quantum-Flux-Parametron Register Files Using a Top-Down Design Flow Reviewed

Olivia Chen, Ro Saito, Tomoyuki Tanaka, Christopher L. Ayala, Naoki Takeuchi, Nobuyuki Yoshikawa

IEEE Transactions on Applied Superconductivity Vol.29 ( 5 ) 2019.3

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Language：English Publishing type：Research paper (scientific journal)

Design of Adiabatic Quantum-Flux-Parametron Register Files Using a Top-Down Design Flow
ISSN Information:<br />
Print ISSN: 1051-8223<br />
Electronic ISSN: 1558-2515<br />
CD: 2378-7074

DOI： 10.1109/TASC.2019.2908277
AQFP-SYNTH: A Per- formance Evaluation Framework for Adiabatic Quantum-Flux-Parametron Based Circuits and Systems

Proc. 12th Superconducting SFQ VLSI Workshop (SSV 2019)

2019.1

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Measurement Result of Adiabatic Quantum-Flux-Parametron 4bit Shifter-Rotator Circuit Designed by Automatic Placementt

T. Tanaka, C. L. Ayala, O. Chen, R. Saito, N. Yoshikaw

Proc. The 12th Superconducting SFQ VLSI Workshop (SSV) 2018 2019.1

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Execution units for a RISC-based adiabatic quantum-flux-parametron microprocessor data path

C. L. Ayala, Q. Xu, R. Saito, T. Tanaka, N. Yoshikawa

Applied Superconductivity Conference (ASC) 2018 2018.10

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Design of Adiabatic Quantum-Flux-Parametron Integrated Circuits Using an Automated Placement Tool Based on Genetic Algorithms Reviewed

T. Tanaka, C.L. Ayala, Q. Xu, R. Saito, N. Yoshikawa

IEICE Tech. Rep. 118 ( 178 ) 53 - 57 2018.8

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Design of Adiabatic Quantum-Flux-Parametron Integrated Circuits Using an Automated Placement Tool Based on Genetic Algorithms
A Large-Scale Design Flow for Adiabatic Quantum-Flux-Parametron Circuits with Retiming and Fan-out Deconstruction Reviewed

C. L. Ayala, Q. Xu, Y. Murai, R. Saito, N. Takeuchi, Y. Yamanashi, T. Ortlepp, N. Yoshikawa

Proc. of International Superconductive Electronics Conference (ISEC 2017) 2017.7

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A Large-Scale Design Flow for Adiabatic Quantum-Flux-Parametron Circuits with Retiming and Fan-out Deconstruction
Synthesis flow for cell-based adiabatic quantum-flux-parametron structural circuit generation with HDL back-end verification Reviewed

Qiuyun Xu, Christopher L. Ayala, Naoki Takeuchi, Yuki Murai, Yuki Yamanashi, Nobuyuki Yoshikawa

IEEE Transactions on Applied Superconductivity 27 ( 4 ) 1301905 2017.6

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Adiabatic quantum-flux-parametron (AQFP) logic is a very energy-efficient platform to perform computing with superconductivity. In AQFP logic, dynamic energy dissipation can be drastically reduced due to the adiabatic switching operations using ac excitation currents. During the past few years, the AQFP logic family has been investigated and implemented into various operational circuits. Experimental results prove the robustness of building large-scale integrated AQFP circuits. In this paper, an AQFP very large scale integration (VLSI) design flow is introduced and detailed with a 16-b decoder as an example circuit. By including logic synthesis and automatic routing tools, this AQFP VLSI design flow is capable of converting a high-level description of a system into a physical layout. Analysis suggests that a reduction of more than 40% in circuit area and a much higher design efficiency can be obtained, compared to a previous design done manually.

DOI： 10.1109/TASC.2017.2662017
Performance Analysis of Synthesized Benchmark Circuits Implemented in Adiabatic Superconductor Logic Reviewed

Q. Xu, R. Saito, Y. Murai, C. L. Ayala, N. Takeuchi, Y. Yamanashi, N. Yoshikawa

The 16th International Superconductive Electronics Conference (ISEC 2017) 2017.6

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Performance Analysis of Synthesized Benchmark Circuits Implemented in Adiabatic Superconductor Logic
単一磁束量子回路を用いた高性能超伝導演算システムに関する研究 Reviewed

徐秋韵

2017.3

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単一磁束量子回路を用いた高性能超伝導演算システムに関する研究
HDL-Based Modeling Approach for Digital Simulation of Adiabatic Quantum Flux Parametron Logic Reviewed

Qiuyun Xu, Christopher L. Ayala, Naoki Takeuchi, Yuki Yamanashi, Nobuyuki Yoshikawa

IEEE Transactions on Applied Superconductivity 26 ( 8 ) 2016.12

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Adiabatic quantum-flux-parametron (AQFP) circuits are currently verified by analog-based simulation, which would be an obstacle for large-scale circuits design. In this paper, we present a logic simulation model for AQFP logic. We made a functional model based on a finite-state machine approach using a hardware description language, which enables the simulation of large-scale AQFP circuits using commercially available logic simulation tools. We have developed a library for logic simulation and implemented an 8-bit carry look-ahead adder, which is composed of over 1000 Josephson junctions. We also include timing information in our logic simulation models for timing analysis. Since the library is based on a parameterized approach, it can be easily modified for different fabrication technologies and low-level circuit parameters.

DOI： 10.1109/TASC.2016.2615123
HDL-based Modelling Approach for Adiabatic Superconductor Logic Simulation

Q. Xu, C.L. Ayala, Y. Yamanashi, N. Yoshikawa

IEICE Tech. Rep. 115 ( 412 ) 11 - 15 2016.1

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HDL-based Modelling Approach for Adiabatic Superconductor Logic Simulation
Timing Extraction for Logic Simulation of VLSI Adiabatic Quantum-Flux-Parametron Circuits

C.L. Ayala, N. Takeuchi, Q. Xu, T. Narama, Y. Yamanashi, T. Ortlepp, N. Yoshikawa

IEICE Tech. Rep. 115 ( 242 ) 7 - 12 2015.10

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Timing Extraction for Logic Simulation of VLSI Adiabatic Quantum-Flux-Parametron Circuits
High-speed demonstration of bit-serial floating-point adders and multipliers using single-flux-quantum circuits Reviewed

Xizhu Peng, Qiuyun Xu, Taichi Kato, Yuki Yamanashi, Nobuyuki Yoshikawa, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi, Mutsuo Hidaka

IEEE Transactions on Applied Superconductivity 25 ( 3 ) 1301106 2015.6

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We have been developing a large-scale reconfigurable data path (LSRDP) based on single-flux-quantum (SFQ) circuit technology for high-performance computing systems. In the SFQ LSRDP, a large number of SFQ floating-point adders (FPAs) and floating-point multipliers (FPMs) are directly connected to each other through routing networks to reduce a memory access rate. In this paper, we show our recent results about the SFQ FPAs and FPMs. Utilization of the National Institute of Advanced Industrial Science and Technology's 10-kA/cm2 Nb process makes it possible to accelerate the clock frequency to more than 50 GHz. We successfully demonstrated the high-speed operation of single-precision FPAs and FPMs, whose clock frequency is beyond 50 GHz, by on-chip high-speed tests. We estimate the performance and energy efficiency of SFQ FPAs and FPMs based on the designed circuits.

DOI： 10.1109/TASC.2014.2382973
Demonstration of bit-serial SFQ-based computing for integer iteration algorithms Reviewed

Qiuyun Xu, Xizhu Peng, Thomas Ortlepp, Yuki Yamanashi, Nobuyuki Yoshikawa

IEEE Transactions on Applied Superconductivity 25 ( 3 ) 1300704 2015.6

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The Collatz conjecture asserts that by a repeated iteration rule, the operation starting from any positive integer n, eventually produces the value of '1.' The main contribution of this paper is to demonstrate a single-flux-quantum (SFQ)-based hardware algorithm that performs an exhaustive search to verify the Collatz conjecture. The circuit consists of a 16-bit integer register, a high-frequency clock generator, and a central processor. This design can perform at up to a maximum clock frequency of 90 GHz with a total power consumption of about 0.85 mW in simulation, based on the AIST 10 kA/cm2 advanced Nb process. An LR-biasing approach further reduces the power consumption, whereas the computing speed can be accelerated by a factor of 20 when accelerating approaches are adopted. The assessments show that our design can process 2 × 107 numbers every second with an energy efficiency of about 5 × 1010 numbers per Joule.

DOI： 10.1109/TASC.2014.2374454
単一磁束量子回路を用いた3n+1問題のための整数型ハードウェアアルゴリズムの研究

徐秋韵

2014.3

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単一磁束量子回路を用いた3n+1問題のための整数型ハードウェアアルゴリズムの研究

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Therapeutic proteins : methods and protocols

Sullivan Millicent O., Chackerian Bryce, Chen Wilfred

Humana Press 2024 （ ISBN:9781071634684 ）

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CRISPR : biology and applications

Barrangou Rodolphe, Sontheimer Erik J., Marraffini Luciano A.

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Presentations

Non-Linear Function Generator Using Stochastic Superconductive Circuits

Olivia Chen, Wenhui Luo, Naoki Takeuchi, Yanzhi Wang, Nobuyuki Yoshikawa

Applied Superconductivity Conference 2022 2022.10

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Design and Implementation of High-Performance Binary Neural Network Using Adiabatic Quantum- Flux-Parametron Logic

T. Yamauchi, H. San, N. Yoshikawa, O. Chen

Applied Superconductivity Conference (ASC 2022) 2022.10

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Design and Implementation of High-Performance Binary Neural Network Using Adiabatic Quantum- Flux-Parametron Logic
Non-Linear Function Generator Using Stochastic Superconductive Circuits

Olivia Chen, Wenhui Luo, Naoki Takeuchi, Yanzhi Wang, Nobuyuki Yoshikawa

Applied Superconductivity Conference 2022 2022.10

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Presentation type：Oral presentation (general)

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Design and Implementation of High-Performance Binary Neural Network Using Adiabatic Quantum- Flux-Parametron Logic

T. Yamauchi, H. San, N. Yoshikawa, O. Chen

Applied Superconductivity Conference (ASC 2022) 2022.10

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A Study on In-Memory Binary Neural Networks Using Adiabatic Quantum-Flux-Parametron Logic

T. Yamauchi, H. San, N. Yoshikawa, O. Chen

SSV2022&QCCC2022 2022.9

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A Study on In-Memory Binary Neural Networks Using Adiabatic Quantum-Flux-Parametron Logic
A Study on In-Memory Binary Neural Networks Using Adiabatic Quantum-Flux-Parametron Logic

T. Yamauchi, H. San, N. Yoshikawa, O. Chen

SSV2022&QCCC2022 2022.9

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Implementation of an FFT-Based Convolutional Processing Element Using Single-Flux-Quantum Technology

Olivia Chen, Fei Ke, Yanzhi Wang, Nobuyuki Yoshikawa

Applied Superconductivity Conference 2020.10

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Implementation of an FFT-Based Convolutional Processing Element Using Single-Flux-Quantum Technology
Design and Evaluation of a Multi-Output True Random Number Generator Based on Adiabatic Quantum-Flux-Parametron Logic

W. Luo, N. Takeuchi, O. Chen, N. Yoshikawa

14th Superconducting SFQ VLSI Workshop 2021.11

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Design and Evaluation of a Multi-Output True Random Number Generator Based on Adiabatic Quantum-Flux-Parametron Logic
Multi-Output True Random Number Generator Based on Adiabatic Quantum-Flux-Parametron Logic

W. Luo, N. Takeuchi, O. Chen, N. Yoshikawa

15th European Conference on Applied Superconductivity 2021.9

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Multi-Output True Random Number Generator Based on Adiabatic Quantum-Flux-Parametron Logic
AQFP 回路のための N-Phase Clock- ing に関する研究

齋藤蕗生, C. L. Ayala, O. Chen, 田中智之, 吉川信行

電子情報通信学会ソサイエティ大会 2020.9

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AQFP 順序回路設計のための論理合成自動化法

齋藤蕗生, C. L. Ayala, O. Chen, 田中智之, 田村智大, 吉川信行

電子情報通信学会総合大会 2020.3

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Adiabatic Quantum- Flux-Parametron Logic のためのフィードバック回路の自動合成

齋藤蕗生, C. L. Ayala, O. Chen, 田中智之, 田村智大, 吉川信行

低温工学・超電導学会研究発表会 2020.5

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An AQFP-Based Neural Network Accelerator with On-Chip Stochastic Number Generation

Olivia Chen, Wenhui Luo, Yanzhi Wang, Naoki Takeuchi, Nobuyuki Yoshikawa

Applied Superconductivity Conference 2020 2020.10

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An AQFP-Based Neural Network Accelerator with On-Chip Stochastic Number Generation
Glitter チャネル配線アルゴリズムによる断熱量子磁束パラメトロン集積回路の信号線のインダクタンス最適化

田中智之, C. L. Ayala, O. Chen, 齋藤蕗生, 吉川信行

電子情報通信学会総合大会 2020.3

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Low-Autocorrelation Random Number Generator using Adiabatic Quantum-Flux-Parametron Logic

Wenhui Luo, Naoki Takeuchi, Olivia Chen, Nobuyuki Yoshikawa

Applied Superconductivity Conference 2020 2020.10

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Low-Autocorrelation Random Number Generator using Adiabatic Quantum-Flux-Parametron Logic
Low Latency Adiabatic Quantum-Flux-Parametron (AQFP) 3-to-8 Decoder Excited by Microwave Power Dividers

Yuxing He, Olivia Chen, Nobuyuki Yoshikawa

Applied Superconductivity Conference 2020 2020.10

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Low Latency Adiabatic Quantum-Flux-Parametron (AQFP) 3-to-8 Decoder Excited by Microwave Power Dividers
Adiabatic Quantum Flux Parametron 回路のための TopDown 環境の開発

齋藤蕗生, C. L. Ayala, O. Chen, 田中智之, 吉川信行

金属・セラミックス超電導機器合同研究会 2019.11

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Adiabatic Quantum Flux Parametron 回路のための Majority-Logic TopDown 環境の開発

齋藤蕗生, C. L. Ayala, O. Chen, 田中智之, 山田剛久, 吉川信行

電子情報通信学会ソサイエティ大会 2019.9

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Computer Aided Design for Superconducting Electronics Panel Invited International conference

Olivia Chen

2019 Design Automation Conference (DAC'2019) 2019.6

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Computer Aided Design for Superconducting Electronics Panel
断熱型量子磁束パラメトロン集積回路の自動配置プログラムによる回路設計とその測定

田中智之, C. L. Ayala, O. Chen, 齋藤蕗生, 吉川信行

超伝導エレクトロニクス研究会 2019.1

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断熱的量子磁束パラメトロン 16-bit 桁上げ先読み加算器の誤動作原因の解析

田中智之, C. L. Ayala, O. Chen, 齋藤蕗生, 吉川信行

超伝導エレクトロニクス研究会 2019.10

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断熱量子磁束パラメトロン 16-bit 桁上げ先読み加算器の設計と評価

田中智之, C. L. Ayala, O. Chen, 齋藤蕗生, 吉川信行

電子情報通信学会ソサイエティ大会 2019.6

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A feedback-friendly large-scale clocking scheme for adiabatic quantum-flux-parametron logic datapaths

N. Takeuchi, C.L. Ayala, Q. Xu, N. Yoshikawa

2018 Applied Superconductivity Conference (ASC 2018) 2018.10

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A feedback-friendly large-scale clocking scheme for adiabatic quantum-flux-parametron logic datapaths
ColdFlux Superconducting EDA and TCAD Tools Project: Overview and Progress Invited

C. Fourie, M. Botha, P. Febvre, C.L. Ayala, Q. Xu, N. Yoshikawa, E. Patrick, M. Law, Y. Wang, M. Annavaram, P. Beerel, S. Gupta, S. Nazarian, M. Pedram

2018 Applied Superconductivity Conference (ASC 2018) 2018.11

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ColdFlux Superconducting EDA and TCAD Tools Project: Overview and Progress
Comprehensive Automated Timing Extraction Methodology for Characterizing an Adiabatic Quantum-Flux-Parametron Logic Cell Library

C.L. Ayala, O. Chen, Q. Xu, N. Yoshikawa

IEICE Society Conference 2018 2018.9

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Comprehensive Automated Timing Extraction Methodology for Characterizing an Adiabatic Quantum-Flux-Parametron Logic Cell Library
Design and Evaluation of Deep Learning Accelerator using Superconductor Logic Families

Q. Xu, Y. Wang, N. Takeuchi, N. Yoshikawa

IEICE Society Conference 2018 2018.9

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Design and Evaluation of Deep Learning Accelerator using Superconductor Logic Families
Design and implementation of an extremely energy-efficient deep learning accelerator using superconducting logic

Q. Xu, X. Ma, Y. Wang, N. Takeuchi, N. Yoshikawa

2018 Applied Superconductivity Conference (ASC 2018) 2018.11

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Design and implementation of an extremely energy-efficient deep learning accelerator using superconducting logic
Design of Adiabatic-Quantum-Flux-Parametron Register Files Using a Top-Down Design Flow

Q. Xu, T. Tanaka, C.L. Ayala, N. Takeuchi, N. Yoshikawa

2018 Applied Superconductivity Conference (ASC 2018) 2018.11

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Design of Adiabatic-Quantum-Flux-Parametron Register Files Using a Top-Down Design Flow
Execution units for a RISC-based adiabatic quantum-flux-parametron microprocessor datapath

C.L. Ayala, Q. Xu, R. Saito, T. Tanaka, N. Takeuchi, Y. Yamanashi, N. Yoshikawa

2018 Applied Superconductivity Conference (ASC 2018) 2018.10

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Execution units for a RISC-based adiabatic quantum-flux-parametron microprocessor datapath
Fabrication of Adiabatic Quantum-Flux-Parametron Integrated Circuits Using an Automatic Placement Tool Based on Genetic Algorithms

Tanaka, C.L. Ayala, Q. Xu, R. Saito, N. Yoshikawa

2018 Applied Superconductivity Conference (ASC 2018) 2018.11

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Fabrication of Adiabatic Quantum-Flux-Parametron Integrated Circuits Using an Automatic Placement Tool Based on Genetic Algorithms
Superconducting microwave delay network for adiabatic quantum-flux-parametron logic

Y. He, N. Takeuchi, Q. Xu, N. Yoshikawa

2018 Applied Superconductivity Conference (ASC 2018) 2018.10

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Superconducting microwave delay network for adiabatic quantum-flux-parametron logic
Young Scientist Plenaries Invited

Qiuyun (Olivia) Xu

2018 Applied Superconductivity Conference (ASC 2018) 2018.10

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Young Scientist Plenaries
遺伝的アルゴリズムを用いた断熱型量子磁束パラメトロン集積回路の自動設計

田中智之, Christopher Ayala, 徐秋韵, 吉川信行

IEICE Society Conference 2018 2018.9

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遺伝的アルゴリズムを用いた断熱型量子磁束パラメトロン集積回路の自動設計
遺伝的アルゴリズムを用いた断熱型量子磁束パラメトロン集積回路の自動設計

田中智之, C. L. Ayala, O. Chen, 齋藤蕗生, 吉川信行

電子情報通信学会ソサイエティ大会 2018.9

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遺伝的アルゴリズムによる自動配置ツールを用いた断熱型量子磁束パラメトロン集積回路の設計

田中智之, C. L. Ayala, O. Chen, 齋藤蕗生, 吉川信行

超伝導エレクトロニクス研究会 2018.8

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Current Progress in Adiabatic Quantum Flux Parametron Invited

N. Takeuchi, C. Ayala, Q. Xu, Y. Yamanashi, N. Yoshikawa

The 30th International Symposium on Superconductivity (ISS 2017) 2017.12

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Current Progress in Adiabatic Quantum Flux Parametron
Design and implementation of AQFP-based register files for an AQFP 4-bit RISC microprocessor prototype

Q. Xu, C. L. Ayala, N. Takeuchi, N. Yoshikawa

2017 Europe Conference on Applied Superconductivity (EUCAS 2017) 2017.9

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Design and implementation of AQFP-based register files for an AQFP 4-bit RISC microprocessor prototype
A Review of Current Progress of Adiabatic Quantum-Flux-Parametron Logic

N. Takeuchi, C. L. Ayala, Q. Xu, F. China, N. Tsuji, T. Ando, Y. Murai, K. Fang, T. Ortlepp, Y. Yamanashi, N. Yoshikawa

The 9th Superconducting SFQ VLSI Workshop (SSV2016) 2016.8

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A Review of Current Progress of Adiabatic Quantum-Flux-Parametron Logic
Recent Progress towards Energy-Efficient Microprocessors Using AQFP Logic Invited

N. Takeuchi, C. Ayala, Q. Xu, F. China, N. Tsuji, T. Narama, T. Ortlepp, Y. Yamanashi, N. Yoshikawa

The 5th International Conference on Superconductivity and Magnetism (ICSM 2016) 2016.4

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Recent Progress towards Energy-Efficient Microprocessors Using AQFP Logic
Synthesis Flow for Cell-Based Adiabatic Quantum-Flux-Parametron Structural Circuit Generation with HDL Backend Verification

Q. Xu, C. L. Ayala, Y. Murai, N. Takeuchi, Y. Yamanashi, T. Ortlepp, N. Yoshikawa

2016 Applied Superconductivity Conference (ASC 2016) 2016.8

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Synthesis Flow for Cell-Based Adiabatic Quantum-Flux-Parametron Structural Circuit Generation with HDL Backend Verification
Creation of a Logic Simulation Model for Adiabatic Quantum Flux Parametron Logic

Q. Xu, C. L. Ayala, N. Takeuchi, Y. Yamanashi, T. Ortlepp, N. Yoshikawa

2015 Europe Conference on Applied Superconductivity (EUCAS 2015) 2015.8

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Creation of a Logic Simulation Model for Adiabatic Quantum Flux Parametron Logic
High-speed Demonstration of Bit-serial SFQ-based Computing for Integer Iteration Algorithms

Q. Xu, Y. Yamanashi, T. Ortlepp, N. Yoshikawa

Cryogenics and Superconductivity Society of Japan 2014.12

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High-speed Demonstration of Bit-serial SFQ-based Computing for Integer Iteration Algorithms
High-speed Demonstration of a Single-Flux-Quantum Processor for Solving the 3n + 1 Problem,

Q. Xu, Y. Yamanashi, T. Ortlepp, N. Yoshikawa

27th International Symposium on Superconductivity 2014.11

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High-speed Demonstration of a Single-Flux-Quantum Processor for Solving the 3n + 1 Problem,
Demonstration of bit-serial SFQ-based computing for integer iteration algorithms

Q. Xu, Y. Yamanashi, T. Ortlepp, N. Yoshikawa

2014 Applied Superconductivity Conference (ASC 2014) 2013.8

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Demonstration of bit-serial SFQ-based computing for integer iteration algorithms

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CSSJ

2024.4 - Present

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ACM

2020 - Present

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IEEE
IEICE
ACM
CSSJ
IEEE

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IEICE

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2024 Design, Automation and Test in Europe Conference (DATE) TPC Member

2023.8 - Present

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2024 Applied Superconductivity Conference (ASC24) Program Committee Member

2023.8 - Present

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IEICE 超伝導エレクトロニクス(SCE)研究専門委員会委員

2022.6 - Present

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IEEE GCCE Session Co-chair

2022.4

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2022 Great Lakes Symposium on VLSI Technical Program Committee Member

2022.2 - 2022.3

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2022 Applied Superconductivity Conference Program Committee Member

2021 - 2022

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2021 Great Lakes Symposium on VLSI Technical Program Committee Member

2021

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第99回低温工学・超電導学会研究発表会運営委員会

2020.3

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2020 Great Lakes Symposium on VLSI Technical Program Committee Member

2020

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European Conference on Applied Superconductivity Session Moderator

2019.9

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2019 国際超伝導電子大会プログラム委員会委員

2019.7

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Research Projects

High-Performance Machine Learning Computing Using Non-deterministic Superconducting Circuits

Grant number：23K28055 2023.4 - 2028.3

Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)

陳オリビア

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本研究は、エネルギー効率の高い超伝導技術を利用して、従来の計算方法とは異なる、高性能な機械学習計算基盤の開発を目指し、低消費電力のハードウェア技術、ビットレベルで並列化が可能なアナログ計算機構、そしてゼロ電力で情報を保持できる不揮発性超伝導多値メモリを活用したインメモリ型計算アーキテクチャを統合することで、非常に効率的な機械学習向けハードウェアを実現する。さらに、システムのスケーラビリティ分析、多値論理の応用範囲と将来性の探究、従来デジタル方式に原理的に相性が悪いCMOSアナログ計算機構を新デバイス・新材料でのリビジットなど、数多くの未解明課題を明らかにする。

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高性能非ノイマン型超伝導SoCの開発

Grant number：JPMJFR226W 2023 - 2029

Japan Society for the Promotion of Science Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (C)

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非決定性超伝導回路を用いた高性能機械学習計算基盤の創出

Grant number：23H03365 2023 - 2027

Japan Society for the Promotion of Science Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (C)

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Construction of stochastic superconductor neural networks towards ultra-low-power machine learning

Grant number：22H00220 2022 - 2026

Japan Society for the Promotion of Science Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (C)

竹内尚輝, 吉川信行, 陳オリビア

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人工知能が中核をなすSociety 5.0の実現には、従来コンピュータに比べて革新的にエネルギー効率の優れた機械学習用ハードウェアの開発が緊要である。そこで本研究は、低エネルギー超伝導集積回路技術をベースに、超伝導ニューロン回路、不揮発性超伝導メモリ、In-memory計算アーキテクチャ、確率的演算手法を融合させて、超低電力ニューラルネットワーク回路の基盤技術の創出を目指す。

CiNii Research
アルゴリズム・ソフトウェア・ハードウェアの融合による超低電力ニューラルネットワークの構築

2019 - 2022

Japan Society for the Promotion of Science Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (C)

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Grant type：Scientific research funding
超伝導断熱磁束量子パラメトロンを用いた低電力深層学習専用チップの開発

2019 - 2021

Japan Society for the Promotion of Science Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (C)

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Grant type：Scientific research funding

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