2025/06/12 更新

お知らせ

 

写真a

ベン イルグオン
BYUN ILKWON
ILKWON BYUN
所属
システム情報科学研究院 情報知能工学部門 准教授
マス・フォア・イノベーション連係学府 (併任)
工学部 電気情報工学科(併任)
システム情報科学府 情報理工学専攻(併任)
職名
准教授
連絡先
メールアドレス
電話番号
092-802-3659

研究分野

  • 情報通信 / 計算機システム

  • ものづくり技術(機械・電気電子・化学工学) / 制御、システム工学

学位

  • Ph.D., Electrical and Computer Engineering ( 2024年2月 )

経歴

  • 九州大学  特任助教 

    2024年3月 - 2024年12月

学歴

  • Seoul National University   Department of Electrical and Computer Engineering   Ph.D.

    2018年9月 - 2024年2月

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    国名:大韓民国

  • Seoul National University   Department of Electrical and Computer Engineering   B.S.

    2012年3月 - 2018年8月

      詳細を見る

    国名:大韓民国

研究テーマ・研究キーワード

  • 研究テーマ: Next-Generation Computer System Architecture

    研究キーワード: Quantum Computing, Superconductor Computing, Cryogenic Computing, Artificial Intelligence Accelerator, Processor, Memory

    研究期間: 2018年9月 - 現在

論文

  • Approximate SFQ-based Computing Architecture Modeling with Device-level Guidelines 査読 国際誌

    Pratiksha Mundhe, Yuta Hano, Satoshi Kawakami, Teruo Tanimoto, Masamitsu Tanaka, Koji Inoue, and Ilkwon Byun

    IEEE Computer Architecture Letters   2025年   ISSN:15566056

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    担当区分:責任著者   記述言語:英語   掲載種別:研究論文(学術雑誌)   出版者・発行元:IEEE Computer Architecture Letters  

    Single-flux-quantum (SFQ) logic has emerged as a promising post-Moore technology thanks to its ultra-fast and lowenergy operation. However, despite progress in various fields, its feasibility is questionable due to the prohibitive cooling cost. Proven conventional ideas, such as approximate computing, may help to resolve this challenge. However, introducing such ideas has been impossible due to the complex performance, power, and error trade-offs originating from the unique SFQ device characteristics. This work introduces approximate SFQ-based computing (AxSFQ) with an architecture modeling framework and essential design guidelines. Our optimized device-level AxSFQ showcases 30˜ 100 times energy efficiency improvement, which motivates further circuit and architecture-level exploration

    DOI: 10.1109/LCA.2025.3573740

    Scopus

  • SuperCore: An Ultra-Fast Superconducting Processor for Cryogenic Applications 査読 国際共著

    Junhyuk Choi, Ilkwon Byun, Juwon Hong, Dongmoon Min, Junpyo Kim, Jungmin Cho, Hyeonseong Jeong, Masamitsu Tanaka, Koji Inoue, and Jangwoo Kim

    IEEE/ACM International Symposium on Microarchitecture (MICRO)   57th   1532 - 1547   2024年11月   ISSN:1072-4451

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    担当区分:筆頭著者   記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

    Superconductor single-flux-quantum (SFQ) logic family has been recognized as a promising technology for cryogenic applications (e.g., quantum computing, astronomy, metrology) thanks to its ultra-fast and low-energy characteristics. Therefore, recent efforts in SFQ-based computing have focused on developing fast and low-power SFQ processors for cryogenic applications. However, there still has been little progress toward a convincing SFQ processor design due to the critical performance challenges originating from its extremely deep pipeline.

    In this paper, we propose a super-fast and low-power in-order SFQ processor by tackling the challenges from the deep pipeline. First, we develop a minimal-depth SFQ processor pipeline with novel architecture-level ideas. Next, we conduct in-depth performance analyses and identify three real performance bottlenecks in the deeply pipelined SFQ processors (i.e., stall/flush logic, RAW stall, fetch unit). Finally, we propose SuperCore, our superfast SFQ-based processor architecture, with three SFQ-friendly solutions that effectively resolve the identified bottlenecks. With our solutions applied, SuperCore achieves 11 times speedup over the SFQ processor baseline. In addition, SuperCore achieves six times speed-up and consumes up to 193 times less power compared to in-order CMOS processors running at 4K.

    DOI: 10.1109/MICRO61859.2024.00112

  • CoolDC: A Cost-Effective Immersion-Cooled Datacenters with Workload-Aware Temperature Scaling 査読

    Dongmoon Min, Ilkwon Byun, Gyuhyeon Lee, and Jangwoo Kim

    ACM Transactions on Architecture and Code Optimization (TACO)   21 ( 3 )   1 - 27   2024年9月   ISSN:1544-3566

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    記述言語:英語   掲載種別:研究論文(学術雑誌)  

    DOI: 10.1145/3664925

    DOI: 10.1145/3664925

  • A Fault-Tolerant Million Qubit-Scale Distributed Quantum Computer 査読

    Junpyo Kim, Dongmoon Min, Jungmin Cho, Hyeonseong Jeong, Ilkwon Byun, Junhyuk Choi, Juwon Hong, and Jangwoo Kim

    ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)   29th   1 - 19   2024年4月   ISBN:979-8-4007-0385-0

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

    A million qubit-scale quantum computer is essential to realize the quantum supremacy. Modern large-scale quantum computers integrate multiple quantum computers located in dilution refrigerators (DR) to overcome each DR’s unscaling cooling budget. However, a large-scale multi-DR quantum computer introduces its unique challenges (i.e., slow and erroneous inter-DR entanglement, increased qubit scale), and they make the baseline error handling mechanism ineffective by increasing the number of gate operations and the inter-DR communication latency to decode and correct errors. Without resolving these challenges, it is impossible to realize a fault-tolerant large-scale multi-DR quantum computer.

    In this paper, we propose a million qubit-scale distributed quantum computer which uses a novel error handling mechanism enabling fault-tolerant multi-DR quantum computing. First, we apply a low overhead multi-DR error syndrome measurement (ESM) sequence to reduce both the number of gate operations and the error rate. Second, we apply a scalable multi-DR error decoding unit (EDU) architecture to maximize both the decoding speed and accuracy. Our multi-DR error handling SW-HW co-design improves the ESM latency, ESM errors, EDU latency, and EDU accuracy by 3.7 times, 2.4 times, 685 times, and 6.1 · 1010 times, respectively. With our scheme applied to assumed voltage-scaled CMOS and mature ERSFQ technologies, we successfully build a fault-tolerant million qubit-scale quantum computer.

    DOI: 10.1145/3620665.3640388

  • Fast, Light-Weight, and Accurate Performance Evaluation using Representative Datacenter Behavior 査読

    Jaewon Lee, Dongmoon Min, Ilkwon Byun, Hanhwi Jang, and Jangwoo Kim

    ACM/IFIP/USENIX International Middleware Conference (MIDDLEWARE)   24th   220 - 233   2023年11月   ISBN:979-8-4007-0177-1

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

    DOI: 10.1145/3590140.3629117

  • QIsim: Architecting 10+K Qubit QC Interfaces Toward Quantum Supremacy 査読 国際共著

    Dongmoon Min, Junpyo Kim, Junhyuk Choi, Ilkwon Byun, Masamitsu Tanaka, Koji Inoue, and Jangwoo Kim

    IEEE/ACM International Symposium on Computer Architecture (ISCA)   50th   1 - 16   2023年6月   ISBN:979-8-4007-0095-8

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

    A 10+K qubit Quantum-Classical Interface (QCI) is essential to realize the quantum supremacy. However, it is extremely challenging to architect scalable QCIs due to the complex scalability trade-offs regarding operating temperatures, device and wire technologies, and microarchitecture designs.Therefore, architects need a modeling tool to evaluate various QCI design choices and lead to an optimal scalable QCI architecture.

    In this paper, we propose (1) QIsim, an open-source QCI simulation framework, and (2) novel architectural optimizations for designing 10+K qubit QCIs toward quantum supremacy. To achieve the goal, we first implement detailed QCI microarchitectures to model all the existing temperature and technology candidates. Next, based on the microarchitectures,we develop our scalability-analysis tool (QIsim) and thoroughly validate it using previous works, postlayout analyses, and real quantum machine experiments. Finally, we successfully develop our 60,000+ qubit-scale QCI designs by applying eight architectural optimizations driven by QIsim.

    DOI: 10.1145/3579371.3589036

  • XQsim: Modeling Cross-technology Control Processors for 10+K Qubit Quantum Computers 査読 国際共著

    Ilkwon Byun, Junpyo Kim, Dongmoon Min, Ikki Nagaoka, Kosuke Fukumitsu, Iori Ishikawa, Teruo Tanimoto, Masamitsu Tanaka, Koji Inoue, and Jangwoo Kim

    IEEE/ACM International Symposium on Computer Architecture (ISCA)   49th   366 - 382   2022年6月   ISBN:978-1-4503-8610-4

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    担当区分:筆頭著者   記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

    10+K qubit quantum computer is essential to achieve a true sense of quantum supremacy. With the recent effort towards the large-scale quantum computer, architects have revealed various scalability issues including the constraints in a quantum control processor, which should be holistically analyzed to design a future scalable control processor. However, it has been impossible to identify and resolve the processor’s scalability bottleneck due to the absence of a reliable tool to explore an extensive design space including microarchitecture, device technology, and operating temperature.

    In this paper,we present XQsim, an open-source cross-technology quantum control processor simulator. XQsim can accurately analyze the target control processors’ scalability bottlenecks for various device technology and operating temperature candidates. To achieve the goal, we first fully implement a convincing control processor microarchitecture for the Fault-tolerant Quantum Computer (FTQC) systems. Next, on top of the microarchitecture, we develop an architecture-level control processor simulator (XQsim) and thoroughly validate it with post-layout analysis, timing-accurate RTL simulation, and noisy quantum simulation. Lastly, driven by XQsim, we provide the future directions to design a 10+K qubit quantum control processor with several design guidelines and architecture optimizations. Our case study shows that the final control processor architecture can successfully support ~59K qubits with our operating temperature and technology choices.

    DOI: 10.1145/3470496.3527417

    DOI: 10.1145/3470496.3527417

  • CryoWire: Wire-driven Microarchitecture Designs for Cryogenic Computing 査読

    Dongmoon Min, Yujin Chung, Ilkwon Byun, Junpyo Kim, and Jangwoo Kim

    ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)   27th   903 - 917   2022年2月   ISBN:978-1-4503-9205-1

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

    Cryogenic computing, which runs a computer device at an extremely low temperature, is promising thanks to its significant reduction of wire resistance as well as leakage current. Recent studies on cryogenic computing have focused on various architectural units including the main memory, cache, and CPU core running at 77K. However, little research has been conducted to fully exploit the fast cryogenic wires, even though the slow wires are becoming more serious performance bottleneck in modern processors.

    In this paper, we propose a CPU microarchitecture which extensively exploits the fast wires at 77K. For this goal, we first introduce our validated cryogenic-performance models for the CPU pipeline and network on chip (NoC), whose performance can be significantly limited by the slow wires. Next, based on the analysis with the models, we architect CryoSP and CryoBus as our pipeline and NoC designs to fully exploit the fast wires. Our evaluation shows that our cryogenic computer equipped with both microarchitectures achieves 3.82 times higher system-level performance compared to the conventional computer system thanks to the 96% higher clock frequency of CryoSP and five times lower NoC latency of CryoBus.

    DOI: 10.1145/3503222.3507749

  • CryoGuard: A Near Refresh-Free Robust DRAM Design for Cryogenic Computing 査読

    Gyuhyeon Lee, Seongmin Na, Ilkwon Byun, Dongmoon Min, and Jangwoo Kim

    IEEE/ACM International Symposium on Computer Architecture (ISCA)   48th   637 - 650   2021年6月   ISSN:1063-6897

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

    Cryogenic computing, which runs a computer device at an extremely low temperature, is highly promising thanks to the significant reduction of the wire latency and leakage current. A recently proposed cryogenic DRAM design achieved the promising performance improvement, but it also reveals that it must reduce the DRAM’s dynamic power to overcome the huge cooling cost at 77K. Therefore, researchers now target to reduce the cryogenic DRAM’s refresh power by utilizing its significantly increased retention time driven by the reduced leakage current. To achieve the goal, however, architects should first answer many fundamental questions regarding the reliability and then design a refresh-free, but still robust cryogenic DRAM by utilizing the analysis result.

    In this work, we propose a near refresh-free, but robust cryogenic DRAM (NRFC-DRAM), which can almost eliminate its refresh overhead while ensuring reliable operations at 77K. For the purpose, we first evaluate various DRAM samples of multiple vendors by conducting a thorough analysis to accurately estimate the cryogenic DRAM’s retention time and reliability. Our analysis identifies a new critical challenge such that reducing DRAM’s refresh rate can make the memory highly unreliable because normal memory operations can now appear as rowhammer attacks at 77K. Therefore, NRFC DRAM requires a cost-effective, cryogenic-friendly protection mechanism against the new row-hammer-like “faults” at 77K.

    To resolve the challenge, we present CryoGuard, our cryogenicfriendly row-hammer protection method to ensure the NRFCDRAM’s reliable operations at 77K. With CryoGuard applied, NRFC-DRAM reduces the overall power consumption by 25.9% even with its cooling cost included, whereas the existing cryogenic DRAM fails to reduce the power consumption.

    DOI: 10.1109/ISCA52012.2021.00056

  • Superconductor Computing for Neural Networks 査読 国際共著

    Koki Ishida, Ilkwon Byun, Ikki Nagaoka, Kosuke Fukumitsu, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Jangwoo Kim, and Koji Inoue

    IEEE Micro   41 ( 3 )   19 - 26   2021年5月   ISSN:0272-1732

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    担当区分:筆頭著者   記述言語:英語   掲載種別:研究論文(学術雑誌)  

    The superconductor single-flux-quantum (SFQ) logic family has been recognized as a promising solution for the post-Moore era, thanks to the ultrafast and lowpower switching characteristics of superconductor devices. Researchers have made tremendous efforts in various aspects, especially in device and circuit design. However, there has been little progress in designing a convincing SFQbased architectural unit due to a lack of understanding about its potentials and limitations at the architectural level. This article provides the design principles for SFQ-based architectural units with an extremely high-performance neural processing unit (NPU). To achieve our goal, we developed and validated a simulation framework to identify critical architectural bottlenecks in designing a performance-effective SFQ-based NPU. We propose SuperNPU, which outperforms a conventional state-of-the-art NPU by 23 times in terms of computing performance and 1.23 times in power efficiency even with the cooling cost of the 4K environment.

    DOI: 10.1109/MM.2021.3070488

  • A Next-Generation Cryogenic Processor Architecture 査読

    Ilkwon Byun, Dongmoon Min, Gyuhyeon Lee, Seongmin Na, and Jangwoo Kim

    IEEE Micro   41 ( 3 )   80 - 86   2021年5月   ISSN:0272-1732

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    担当区分:筆頭著者   記述言語:英語   掲載種別:研究論文(学術雑誌)  

    Cryogenic computing can achieve high performance and power efficiency by dramatically reducing the device’s leakage power and wire resistance at low temperatures. Recent advances in cryogenic computing focus on developing cryogenic-optimal cache and memory devices to overcome memory capacity, latency, and power walls. However, little research has been conducted to develop a cryogenic-optimal core architecture even with its high potentials in performance, power, and area efficiency. In this article, we first develop CryoCore-Model, a cryogenic processor modeling framework that can accurately estimate the maximum clock frequency of processor models running at 77 K. Next, driven by the modeling tool, we design CryoCore, a 77 K-optimal core microarchitecture to maximize the core’s performance and area efficiency while minimizing the cooling cost. The proposed cryogenic processor architecture, in this article, achieves the large performance improvement and power reduction and, thus, contributes to the future of high-performance and power-efficient computer systems.

    DOI: 10.1109/MM.2021.3070133

  • SuperNPU: An Extremely Fast Neural Processing Unit Using Superconducting Logic Devices 査読 国際共著

    Koki Ishida, Ilkwon Byun, Ikki Nagaoka, Kosuke Fukumitsu, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Jangwoo Kim, and Koji Inoue

    IEEE/ACM International Symposium on Microarchitecture (MICRO)   53th   58 - 72   2020年10月   ISBN:978-1-7281-7384-9

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    担当区分:筆頭著者   記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

    DOI: 10.1109/MICRO50266.2020.00018

  • CryoCore: A Fast and Dense Processor Architecture for Cryogenic Computing 査読

    Ilkwon Byun, Dongmoon Min, Gyuhyeon Lee, Seongmin Na, and Jangwoo Kim

    IEEE/ACM International Symposium on Computer Architecture (ISCA)   47th   335 - 348   2020年5月   ISBN:978-1-7281-4662-1

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

    DOI: 10.1109/ISCA45697.2020.00037

  • CryoCache: A Fast, Large, and Cost-Effective Cache Architecture for Cryogenic Computing 査読

    Dongmoon Min, Ilkwon Byun, Gyuhyeon Lee, Seongmin Na, and Jangwoo Kim

    ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)   25th   449 - 464   2020年3月   ISBN:978-1-4503-7102-5

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    記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

    DOI: 10.1145/3373376.3378513

  • Cryogenic Computer Architecture Modeling with Memory-Side Case Studies 査読

    Gyu-Hyeon Lee, Dongmoon Min, Ilkwon Byun, and Jangwoo Kim

    IEEE/ACM International Symposium on Computer Architecture (ISCA)   46th   774 - 787   2019年6月   ISBN:978-1-4503-6669-4

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    担当区分:筆頭著者   記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)  

    DOI: 10.1145/3307650.3322219

▼全件表示

講演・口頭発表等

  • SuperCore: An Ultra-Fast Superconducting Processor for Cryogenic Applications 国際共著 国際会議

    Junhyuk Choi, Ilkwon Byun, Juwon Hong, Dongmoon Min, Junpyo Kim, Jungmin Cho, Hyeonseong Jeong, Masamitsu Tanaka, Koji Inoue, and Jangwoo Kim

    IEEE/ACM International Symposium on Microarchitecture (MICRO)  2024年11月 

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    開催年月日: 2024年11月

    記述言語:英語   会議種別:口頭発表(一般)  

    開催地:Austin, Texas, USA   国名:アメリカ合衆国  

    DOI: 10.1109/MICRO61859.2024.00112

  • A Fault-Tolerant Million Qubit-Scale Distributed Quantum Computer 国際会議

    Junpyo Kim, Dongmoon Min, Jungmin Cho, Hyeonseong Jeong, Ilkwon Byun, Junhyuk Choi, Juwon Hong, and Jangwoo Kim

    ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)  2024年4月 

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    開催年月日: 2024年4月 - 2024年5月

    記述言語:英語   会議種別:口頭発表(一般)  

    開催地:San Diego   国名:アメリカ合衆国  

    DOI: 10.1145/3620665.3640388

  • QIsim: Architecting 10+K Qubit QC Interfaces Toward Quantum Supremacy 国際共著 国際会議

    Dongmoon Min, Junpyo Kim, Junhyuk Choi, Ilkwon Byun, Masamitsu Tanaka, Koji Inoue, and Jangwoo Kim

    IEEE/ACM International Symposium on Computer Architecture (ISCA)  2023年6月 

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    開催年月日: 2023年6月

    記述言語:英語   会議種別:口頭発表(一般)  

    開催地:Orlando, Florida   国名:アメリカ合衆国  

    DOI: 10.1145/3579371.3589036

  • XQsim: Modeling Cross-technology Control Processors for 10+K Qubit Quantum Computers 国際共著 国際会議

    Ilkwon Byun, Junpyo Kim, Dongmoon Min, Ikki Nagaoka, Kosuke Fukumitsu, Iori Ishikawa, Teruo Tanimoto, Masamitsu Tanaka, Koji Inoue, and Jangwoo Kim

    IEEE/ACM International Symposium on Computer Architecture (ISCA)  2022年6月 

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    開催年月日: 2022年6月

    記述言語:英語   会議種別:口頭発表(一般)  

    開催地:New York   国名:アメリカ合衆国  

    DOI: 10.1145/3470496.3527417

  • CryoWire: Wire-driven Microarchitecture Designs for Cryogenic Computing 国際会議

    Dongmoon Min, Yujin Chung, Ilkwon Byun, Junpyo Kim, and Jangwoo Kim

    ACM International Conference on Architectural Support for Programming Languages and Operating System (ASPLOS)  2022年3月 

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    開催年月日: 2022年2月 - 2022年3月

    記述言語:英語   会議種別:口頭発表(一般)  

    開催地:Lausanne   国名:スイス連邦  

    DOI: 10.1145/3503222.3507749

  • CryoGuard: A Near Refresh-Free Robust DRAM Design for Cryogenic Computing 国際会議

    Gyuhyeon Lee, Seongmin Na, Ilkwon Byun, Dongmoon Min, and Jangwoo Kim

    IEEE/ACM International Symposium on Computer Architecture (ISCA)  2021年6月 

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    開催年月日: 2021年6月

    記述言語:英語   会議種別:口頭発表(一般)  

    開催地:online  

    DOI: 10.1109/ISCA52012.2021.00056

  • SuperNPU: An Extremely Fast Neural Processing Unit Using Superconducting Logic Devices 国際共著 国際会議

    Koki Ishida, Ilkwon Byun, Ikki Nagaoka, Kosuke Fukumitsu, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Jangwoo Kim, and Koji Inoue

    IEEE/ACM International Symposium on Microarchitecture (MICRO)  2020年10月 

     詳細を見る

    開催年月日: 2020年10月

    記述言語:英語   会議種別:口頭発表(一般)  

    開催地:online  

    DOI: 10.1109/MICRO50266.2020.00018

  • CryoCore: A Fast and Dense Processor Architecture for Cryogenic Computing 国際会議

    Ilkwon Byun, Dongmoon Min, Gyuhyeon Lee, Seongmin Na, and Jangwoo Kim

    IEEE/ACM International Symposium on Computer Architecture (ISCA)  2020年6月 

     詳細を見る

    開催年月日: 2020年5月 - 2020年6月

    記述言語:英語   会議種別:口頭発表(一般)  

    開催地:online  

    DOI: 10.1109/ISCA45697.2020.00037

  • CryoCache: A Fast, Large, and Cost-Effective Cache Architecture for Cryogenic Computing 国際会議

    Dongmoon Min, Ilkwon Byun, Gyuhyeon Lee, Seongmin Na, and Jangwoo Kim

    ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)  2020年3月 

     詳細を見る

    開催年月日: 2020年3月

    記述言語:英語   会議種別:口頭発表(一般)  

    開催地:online  

    DOI: 10.1145/3373376.3378513

  • Cryogenic Computer Architecture Modeling with Memory-Side Case Studies 国際会議

    Gyu-Hyeon Lee, Dongmoon Min, Ilkwon Byun, and Jangwoo Kim

    IEEE/ACM International Symposium on Computer Architecture (ISCA)  2019年6月 

     詳細を見る

    開催年月日: 2019年6月

    記述言語:英語   会議種別:口頭発表(一般)  

    開催地:Phoenix, Arizona   国名:アメリカ合衆国  

    DOI: 10.1145/3307650.3322219

  • Toward Practical Quantum Computer Systems: A Computer Architect's Perspective 招待 国際会議

    Ilkwon Byun

    International Workshop on the Art, Science, and Engineering of Quantum Programming  2025年6月 

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    開催年月日: 2025年6月

    記述言語:英語   会議種別:口頭発表(基調)  

    開催地:Prague   国名:チェコ共和国  

    Quantum computing has emerged as a promising candidate for innovating various areas with a quantum nature. However, practical applications require thousands of noiseless ideal qubits, while real-world physical qubits are very fragile. To bridge this gap, we eventually need an error-corrected quantum computer with millions of physical qubits. In this presentation, we introduced a computer architect's approach to developing a practical quantum computer system. Next, as an example of our approach, we shared our recent research on quantum computer architecture, published in top-tier architecture conferences. Lastly, we discussed a computer architect's perspective for pacing with rapidly evolving quantum computing technologies.

  • Scalable Control System Architecture for Large-scale Superconducting Quantum Computers 招待

    Ilkwon Byun

    Quantum software, middleware, and controller for near-term quantum computing systems  2024年10月 

     詳細を見る

    開催年月日: 2024年10月

    記述言語:英語   会議種別:口頭発表(招待・特別)  

    開催地:Osaka   国名:日本国  

  • Superconductor Computer Architecture: from Classical to Quantum", U.S.-Japan Collaborative Workshop: Accelerating IC Design 招待 国際会議

    Ilkwon Byun

    U.S.-Japan Collaborative Workshop: Accelerating IC Design  2024年5月 

     詳細を見る

    開催年月日: 2024年5月

    記述言語:英語   会議種別:口頭発表(招待・特別)  

    開催地:Fukuoka   国名:日本国  

  • Toward Next-Generation Computer Systems: Cryogenic, Superconductor, and Quantum Computer Architecture 招待 国際会議

    Ilkwon Byun

    Superconducting SFQ VLSI Workshop (SSV)  2022年9月 

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    開催年月日: 2022年9月

    記述言語:英語   会議種別:口頭発表(招待・特別)  

    開催地:Kyoto   国名:日本国  

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所属学協会

  • IEEE

  • ACM

  • 情報処理学会

  • The Institute of Electronics, Information and Communication Engineers (IEICE)

学術貢献活動

  • Program Committee 国際学術貢献

    役割:査読

    IEEE/ACM International Symposium on Microarchitecture (MICRO 2025)   2025年10月

  • Program Committee 国際学術貢献

    役割:査読

    IEEE International Symposium on High-Performance Computer Architecture (HPCA 2025)  2025年3月

  • External Program Committee 国際学術貢献

    役割:査読

    IEEE/ACM International Symposium on Microarchitecture (MICRO 2024)   2024年11月

共同研究・競争的資金等の研究課題

FD参加状況

  • 2025年4月   役割:参加   名称:令和7年度 第1回全学FD(新任教員FDの研修)The 1st All-University FD (training for new faculty members) in FY2025

    主催組織:全学

  • 2025年3月   役割:参加   名称:【シス情FD】卒業研究説明会:新任教員の紹介

    主催組織:部局

  • 2025年3月   役割:参加   名称:全学FD「M2B講習会」(3/7~オンデマンド配信)

    主催組織:全学

  • 2025年3月   役割:参加   名称:【シス情FD】各種表彰/フェロー称号等の戦略的獲得に向けて

    主催組織:部局

  • 2025年3月   役割:参加   名称:第56回 令和6(2024)年度 IDE大学セミナー

    主催組織:部局

  • 2025年2月   役割:参加   名称:【シス情FD】プレアドミッション・サポートデスク(PSD)による留学生のための出願前支援 〜導入のメリット〜

    主催組織:部局

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