Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.1109/icsj59341.2023.10339585

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Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.1109/icsj59341.2023.10339614

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Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.1109/biocas58349.2023.10389082

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Publishing type：Research paper (international conference proceedings)   Publisher：The Japan Society of Applied Physics  

DOI： 10.7567/ssdm.2023.g-5-02

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Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.1109/3dic57175.2023.10154930

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Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.1109/ectc51909.2023.00105

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Publishing type：Research paper (scientific journal)   Publisher：Institute of Electronics, Information and Communications Engineers (IEICE)  

DOI： 10.1587/elex.19.20220363

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Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.1109/biocas54905.2022.9948542

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Publishing type：Research paper (international conference proceedings)   Publisher：The Japan Society of Applied Physics  

DOI： 10.7567/ssdm.2022.e-7-02

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Publishing type：Research paper (international conference proceedings)   Publisher：The Japan Society of Applied Physics  

DOI： 10.7567/ssdm.2022.k-4-02

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Publishing type：Research paper (international conference proceedings)   Publisher：The Japan Society of Applied Physics  

DOI： 10.7567/ssdm.2022.d-1-03

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Publishing type：Research paper (international conference proceedings)   Publisher：The Japan Society of Applied Physics  

DOI： 10.7567/ssdm.2022.k-1-01

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Publishing type：Research paper (international conference proceedings)   Publisher：The Japan Society of Applied Physics  

DOI： 10.7567/ssdm.2022.k-1-03

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Language：Others   Publishing type：Research paper (scientific journal)   Publisher：American Vacuum Society  

In the elucidation of brain functions, neuroscience has garnered attention in the realization of brain-machine interfaces, deep brain stimulation, and artificial intelligence. Optogenetics is a biological technique used to control neural activities via optical stimulation. It is one of the most effective approaches used to investigate brain functions. This study proposed to employ the transparent recording electrode to enhance the performance of neural probes for optogenetics. Compared with conventional metal recording electrodes, the proposed transparent recording electrodes have the potential to obtain higher signal-to-noise ratios when placed over optical stimulation points. To develop transparent recording electrodes, we used ZnO-based materials with good biocompatibility and transparency for utilization as biomedical electrodes. Considering saline as one of the main components of living organisms, we investigated the fundamental electrochemical characteristics of ZnO-based electrodes in saline through electrochemical impedance spectroscopy and cyclic voltammetry. The results showed that nondoped ZnO and Al-doped ZnO, deposited by radio frequency magnetron sputtering, exhibited a broad potential window. An electrical double layer was found to strongly act on the interface between the electrodes and solution rather than a redox reaction. In addition, this study reports the effects of crystallization and dopant on the electrochemical characteristics of the ZnO-based electrodes. The transparent ZnO-based electrode developed herein is a promising candidate to enhance the performance of neural probes for optogenetics and can be effectively applied in biological devices.

DOI： 10.1116/6.0001836

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Language：Others   Publishing type：Research paper (other academic)   Publisher：IEEE  

DOI： 10.1109/iitc52079.2022.9881288

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Language：Others   Publishing type：Research paper (other academic)   Publisher：IEEE  

DOI： 10.1109/ectc51906.2022.00225

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Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/biocas49922.2021.9645034

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/3dic52383.2021.9687601

Language：Others   Publishing type：Research paper (scientific journal)  

Antiperovskite manganese nitride compounds possess the saturation characteristics of the mean free path at an approximate room temperature. Therefore, such compounds show a flat resistance-temperature curve at an approximate room temperature. In this paper, we propose a manganese nitride resistor for high-thermal-stability systems. We fabricated and evaluated the micro/nanoscale manganese nitride compound resistors using the complementary metal-oxide-semiconductor-compatible process. The thermal coefficient of the fabricated manganese nitride compound resistor was as low as that of other near-zero temperature-coefficient of resistivity materials. These results indicate that manganese nitride compounds can achieve higher thermal stability.

DOI： 10.35848/1882-0786/ac18b0

Language：Others   Publishing type：Research paper (other academic)  

The resistance of the metal wirings in the integrated circuits increases due to the decrease of the mean free path of electrons with the temperature increase. This thermal instability requires redundancy circuits. On the other hand, several materials have the saturation characteristics of the mean free path around room temperature. The anti-perovskite manganese nitride compound material is one of them. The anti-perovskite manganese nitride compounds show a flat resistance-temperature curve around room temperature. However, the flat resistance-temperature curves have been obtained with only the sintered bulk materials. It has not become clear the characteristics of the manganese nitride compounds in the micro/nanoscale. In this study, we proposed manganese nitride wiring for high-thermal-stability systems. Then, we fabricated and evaluated the micro/nanoscale manganese nitride compound wiring with the complementary metal-oxide-semiconductor compatible process.

DOI： 10.1109/IITC51362.2021.9537336

Language：Others   Publishing type：Research paper (other academic)  

In order to fabricate a wearable flexible display as a flexible hybrid electronic (FHE) device with micro-LED dies, we demonstrate multi-level metallization on an elastomer using die-first fan-out wafer-level packaging (FOWLP). The elastic substrate of this display is PDMS (polydimethylsiloxane) in which the array of 3-color micro-LEDs is embedded. In this study, we address serious issues such as die shift and stress accumulation in advanced FOWLP to integrate a self-luminescent flexible micro-LED display.

DOI： 10.1109/IITC51362.2021.9537540

Language：Others   Publishing type：Research paper (scientific journal)  

© 2020 The Authors. Journal of Polymer Science published by Wiley Periodicals LLC. Thin-film polyimides were prepared by solvent-less vapor deposition polymerization (VDP) from pyromellitic dianhydride and 4,4′-oxydianiline at 200 °C for liner dielectric formation of vertical interconnects called through-silicon vias (TSVs) used in three-dimensionally stacked integrated circuit (3DICs). FTIR, synchrotron XPS, and TDS were employed for determining the imidization ratio, and in addition, the mechanical properties, coefficient of thermal expansion and Young's modulus, of the VDP polyimide were characterized on Si wafers. The VDP polyimide exhibited extremely high conformality, beyond 75%, toward high-aspect-ratio deep Si holes, compared with conventional SiO2 prepared by plasma-enhanced chemical vapor deposition. The adhesion between the VDP polyimide and Si wafer was enhanced by an Al-chelate promotor. Remarkably, the VDP polyimide TSV liner dielectrics showed much less thermomechanical stresses applied to the Si surrounding the TSVs than the plasma-chemical vapor deposition SiO2. The small keep-out zone is expected for scaling down highly reliable 3DICs for the upcoming real artificial intelligence society.

DOI： 10.1002/pol.20200094

Language：Others   Publishing type：Research paper (scientific journal)  

© 2011-2012 IEEE. Typical die shift is beyond several tens micrometers or more, which is a serious problem on advanced fan-out wafer-level packaging (FOWLP), to give inevitable misalignment errors in the subsequent photolithography processes for fine-pitch redistributed wiring layer (RDL) formation. In particular, this problem is expected to grow all the more serious in chiplets and tiny dies less than 1 mm in a side. In this work, the use of an anchoring layer is proposed to fix these dies/chiplets on a double-side laminate thermo-release tape and drastically reduce the die shift. In addition, an on-nail photoplethysmogram (PPG) sensor module as a part of flexible hybrid electronics (FHE) is integrated with mu LED ( 270,,mu ext{m},, imes 270,,mu ext{m} ) based on a die-first FOWLP methodology using a biocompatible polydimethylsiloxane (PDMS) mold resin for real-time monitoring pulse wave and percutaneous oxygen saturation (SpO2). The repeated bendability of fan-out Au wirings formed on the PDMS and the current-voltage ( I - V ) behavior of the mu LED before and after die embedment in the PDMS is characterized.

DOI： 10.1109/TCPMT.2020.3009640

Language：Others   Publishing type：Research paper (other academic)  

© 2020 IEEE. A new flexible hybrid electronics (FHE) methodology using advanced RDL-first fan-out wafer-level packaging (FOWLP) technologies with dielets and hydrogel substrates is proposed. Hydrogels mainly consisting of water have excellent biocompatibility, high adaptability, and substance permeability, and they are expected for biomedical applications. In this work, we integrate Si LSI and mini-LED dielets in a hydrogel substrate on which fine-feature Au interconnections are formed in wafer-level processing. We characterize their electrical properties of the embedded dielets for biomedical applications.

DOI： 10.1109/ECTC32862.2020.00132

Language：Others   Publishing type：Research paper (other academic)  

© 2020 IEEE. This paper deals with multichip-to-wafer (MC2W) 3D stacking technologies based on via-last TSV integration. In this work, we verify the effectiveness of room-temperature CVD named OER (Ozone-Ethylene Radical generation)-TEOS-CVD® to deposit a TSV liner SiO2 layer. The film quality including dielectric constants is evaluated alternative to plasma-enhanced (PE)-TEOS-CVD SiO2. In addition, solid-solid inter-diffusion bonding of 3-μm-thick Sn with 0.5-μm-thick Au is demonstrated to achieve multiple multichip bonding for retinal prosthesis system fabrication with a 3D artificial retina chip. Low-temperature bonding at 190°C is realized by the Au/Sn metallurgy. Good bondability is also obtained with the Au electrodes preliminarily exposed at high temperature. There are no Sn microbump extrusion, which is highly expected to be used for 3D-ICs with fine-pitch solder microbump interconnection.

DOI： 10.1109/ECTC32862.2020.00192

Language：Others   Publishing type：Research paper (other academic)  

© 2020 IEEE. High-density interconnections are highly required for 3D IC such as FPGA and image sensor applications. Fine-pitch interconnects using conventional solder microbumps are still required. To meet this requirements, low-height Cu/Sn microbumps are evaluated in this study. The thermal compression bonding with the low-height solder microbumps makes it challenging to fulfill high-viscous capillary underfill (CUF) into extremely small gaps between the chips stacked in layers. Here, we demonstrate to apply a 7-μm-thick non-conductive film (NCF) to flip-chip bonding with the low-height solder microbumps. Compared with a CUF, the electrical characterization such as electromigration (EM) and leakage current of microbump daisy chains with the ultra-thin NCF was investigated with temperature cycle test (TCT) and unbiased HAST.

DOI： 10.1109/ECTC32862.2020.00230

Language：English   Publishing type：Research paper (other academic)  

© 2020 IEEE. Spiking neural network (SNN) has attracted much attention as next-generation neural networks. To realize SNN, the spike-timing-dependent plasticity (STDP) is one of the critical characteristics. In this study, we demonstrated the STDP of a biological synapse with non-volatile tunnel-field-effect transistor (FET) memory. Tunnel FET is a promising candidate to reduce the power consumption owing to the steep subthreshold characteristics. Therefore, non-volatile tunnel-FET memory we proposed has the possibility to realize low-power SNN. This paper reported the current-voltage characteristics, the memory window., and the STDP characteristics of the nonvolatile tunnel-FET memory.

DOI： 10.1109/EDTM47692.2020.9118027

Language：Others   Publishing type：Research paper (scientific journal)  

© 2020 The Japan Society of Applied Physics. Spiking neural networks are attracting significant attention because they can perform cognitive tasks with relatively low power. In addition, we proposed a tunnel field-effect transistor (TFET)-based charge trapping memory to reduce the power consumption of the flash memory-based neural network circuit. The current-voltage characteristics of the fabricated TFET based memory cell were typical of the charge trapping memory. We then measured the symmetric and asymmetric spike-timing-dependent plasticity (STDP) characteristics of the fabricated TFET-based memory cell. The obtained characteristics reproduce the STDP of a biological synapse. These results indicated that there is a possibility of applying the proposed devices to neural network circuits.

DOI： 10.35848/1347-4065/ab6867

Language：English   Publishing type：Research paper (scientific journal)  

© 2019 The Japan Society of Applied Physics. Thinning defects such as chipping and cracking caused by multichip lapping and chemical mechanical polishing processes were evaluated for through-silicon via formation based on via-last/backside via technologies. Two types of temporary adhesives with different Young's moduli were used in this multichip-to-wafer (MC2W) approach for comparison. Impact of the temporary bonding conditions and temporary adhesive properties on the multichip thinning failure was discussed for achieving high-yield MC2W 3D integration. When a temporary adhesive with a low Young's modulus is employed, the space between adjacent chips and the chip sidewall covered with adhesive were found to be critical parameters to the multichip thinning without chipping and cracking.

DOI： 10.7567/1347-4065/ab4f3c

Language：Others   Publishing type：Research paper (other academic)  

© 2019 IEEE. We have fabricated microbump daisy chains with a low-height solder thickness of 2.5 μm in order to evaluate flip-chip bonding capabilities. Electrical characteristics of the bonded microbumps in three-dimensionally stacked chips were compared between a very thin non-conductive film (NCF) and capillary underfill (CUF). The resulting I-V behaviors showed that the resistance of the daisy chain with the NCF was lower than that with the CUF, inDICating that the low-height solder microbumps with combination of the thin NCF can be a promising candidate for future fine-pitch inter-chip connection in 3DICs.

DOI： 10.1109/3DIC48104.2019.9058841

Language：Others   Publishing type：Research paper (other academic)  

© 2019 IEEE. In order to efficiently record the photoplethysmography (PPG) and apply it for peripheral oxygen saturation (SpO2) measurement, we developed a trans-nail pulse-wave monitoring system, which is able to record the PPG signal on nail-Tip without discomfort and any effects from sweat. This system includes PPG and SpO2 recording circuit (PPG/SpO2-RC) with ambient light cancellation (ALC) function and was fabricated in 1P6M 0.18 μm CMOS technology. It has a small area of about 1.7 mm2. The PPG/SpO2-RC mainly consists of an LED driver circuit, a PPG readout circuit, and a 500 x 500 μm2 photodiode (PD). LED driver circuit selectively drives three different wavelength LEDs. In the PPG readout circuit, an 86/96 dBΩ I/V converter, 20-80 dB programmable gain amplifiers, and LPF ensured the PPG signal being recorded using an appropriate gain for different individuals. On top of that, an ALC circuit was integrated into the PPG readout circuit to reduce noise from ambient light and preventing these signals from saturating the circuit. The PPG/SpO2-RC was evaluated, and the PPG signal and SpO2 were measured and calculated successfully, proving that it worked as it designed. In the future, the circuit will be integrated with other elements such as a Bluetooth module (BLE) in the trans-nail pulse-wave monitoring system.

DOI： 10.1109/BIOCAS.2019.8919027

Language：Others   Publishing type：Research paper (other academic)  

© 2019 IEEE. The three-dimensional (3D) integration process is a promising candidate to enhance electron-device performance. Typical 3D integration systems consist of vertically stacked several thin IC chips that are electrically connected with lots of through-Si vias (TSVs) and metal microbumps. Metal microbumps are surrounded by organic adhesive. An epoxy-based material, so-called underfill, has been widely used to fill the gap between several chips. In general, the coefficient of thermal expansion (CTE) of the underfill material is larger than that of metal microbumps. This CTE mismatch induces local bending stress in thinned IC chips. This local bending stress would affect the CMOS circuit in thinned IC chips. Therefore, we should suppress the local bending stress to realize 3D IC with high reliability. To suppress the local bending stress, we have proposed a novel underfill with negative-Thermal-expansion material. In this study, we investigated the characteristics of the negativethermal-expansion material surrounded by the matrix of the underfill.

DOI： 10.1109/3DIC48104.2019.9058838

Language：Others   Publishing type：Research paper (other academic)  

© 2019 IEEE. Through-silicon vias (TSVs) is one of the key technologies for 3D integration. To solve the issues induced by the high-Temperature process for TSV liner formation in the multichip-To-wafer (MCtW) process, we applied the low-Temperature SiO2 deposition method called OER (Ozone-Ethylene Radical generation)-TEOS-CVD®. In this study, we fabricated the MIS capacitors with the TSV liner deposited by OER-TEOS-CVD® at 150°C and room temperature (RT), and compared both the coverage and electrical characteristics with that formed by conventional plasma-enhanced chemical vapor deposition (PE-CVD) at 200°C. Furthermore, we analyzed these SiO2liners by FTIR and synchrotron XPS. These results showed that the OER-TEOS-CVD® has high potentials to realize highly-reliable TSVs and to apply to various processes in 3D integration.

DOI： 10.1109/3DIC48104.2019.9058843

Language：Others   Publishing type：Research paper (other academic)  

© 2019 IEEE. This paper describes a highly parallel analog signal processing method with three-dimensional (3-D) stacked neural network chip for convolutional and deep neural networks (CNNs and DNNs). The proposed chip has a stacked structure, which enables highly parallel mixed-signal operations like human brains with low power consumption. The product-sum operation using analog circuit in highly parallel calculation with low power supply current, but repeated calculations result in excessive noise (e.g.The offset voltage of the amplifier and 1/f noise, kT/C noise etc.) accumulation and degraded calculation accuracy. Therefore, analog signal processing with 3-D stacked multiple layers neural network chip require the noise reduction technique. In this design, correlated double sampling (CDS) is used to noise reduction technique with which reduce noise generated in the circuit. The proposed CDS circuit is designed with CMOS 0.18nm technology. As results of simulation analysis, it was confirmed that the CDS circuit reduced the offset voltage of composing amplifier and the noise voltages of the circuits placed before the CDS circuit to less than 1.25mV.

DOI： 10.1109/3DIC48104.2019.9058856

Language：Others   Publishing type：Research paper (other academic)  

© 2019 IEEE. We have fabricated a new 3D-IC embedded flexible hybrid system (FHS) based on a Fan-Out Wafer-Level Packaging (FOWLP). The unique FHS structure is consisting of PDMS as a flexible substrate in which the 3D-IC with through-Si vias (TSVs) and microbumps are embedded. The mechanical and electrical properties of the 3D-IC embedded FHS are characterized by using repeated bending test with the TSV/microbump daisy chains. The new FHS can be expected to be used as high-performance wearable device systems for biomedical applications.

DOI： 10.1109/3DIC48104.2019.9058880

Language：English   Publishing type：Research paper (other academic)  

Development of Wireless Opto-Neural Probe with Upconversion Nanoparticles (UCNP) for Optogenetics

Language：English   Publishing type：Research paper (other academic)  

Ultrasmall Area and Ultralow Frequency Ring-oscillatorUsing GIDL Currentfor IoT Edge Applications

Language：English   Publishing type：Research paper (other academic)  

Spike Timing Dependent Plasticity Characteristics of Tunnel FET based MONOS Memory for Low Power Neural Network Circuits

Language：English   Publishing type：Research paper (other academic)  

Hydrogel-based Flexible Hybrid Electronics Technology for Biomedical Application

Language：Others   Publishing type：Research paper (other academic)  

© 2019 IEEE. A new flexible trans-nail photoplethysmographic (PPG) sensor system is proposed and characterized from both aspects of mechanical and electrical properties in this study. The unique FHE (flexible hybrid electronics) structure is consisting of an elastomer as a flexible substrate in which Si LSI dielets having photodiode and LED driver circuits etc. are embedded based on a FOWLP concept. Stress buffer layers (SBLs) as a key material are inserted between interdielet wirings and the substrate to mitigate mechanical stress and enhance wire reliability. The impact of the Young's moduli of the SBLs on the repeated bendability of the FHE systems is described. In addition, we evaluate the electrical properties of the photodiode circuits between before and after bending for comparison.

DOI： 10.1109/ECTC.2019.00046

Language：English   Publishing type：Research paper (scientific journal)  

© 2019 IEEE. The effects of the external stress on memory device characteristics are numerically discussed, and experimental observations are made, based on the wafer curvature method for extraction of stress. An analysis of the interface state is then performed. The external force applied to the device was controlled by depositing a metal film on the wafer backside; then, the residual stress induced on the substrate was extracted. We observed that the dangling bond generated by the residual stress increases the trap site and deteriorates the interface properties. A resulting degradation of cell characteristics occurred, including an increase in the leakage current and degradation of the memory window, featuring a reduction in the oxide/nitride/oxide trap density, which worsens as the magnitude of stress increases. From these results, we concluded that minimizing the stress is essential for retaining the cell characteristics. Especially, our results are expected to be of great help in determining the effect of external force on the memory characteristics during the back-end-of-line processing.

DOI： 10.1109/TED.2019.2900155

Language：Others   Publishing type：Research paper (other academic)  

© 2019 IEEE. The effect of noise propagation from a digital circuit on an analog circuit was evaluated using an actual mixed-signal 3D-IC, which has a stacked structure of digital and analog IC chips. The noise propagation through the TSV was measured with a ring-oscillator as a noise source. To investigate in detail, TSV-liner interface states were evaluated along depth direction using unique multi-well-structured TSVs and charge-pumping method. It was considered that the interface traps and non-conformal thickness of TSV liner increased the noise propagation among stacked chips.

DOI： 10.1109/EDTM.2019.8731161

Language：English   Publishing type：Research paper (scientific journal)  

Through-silicon-vias (TSVs) with a diameter of 3 mu m and high aspect ratio of 15 are successfully fabricated based on a low-cost and low-temperature process involving spin coating of polyimide liner, electroless plating of Ni barrier/seed layer, and electroplating of Cu, which is suitable for via-middle/via-last processes that have a more stringent thermal budget. A novel eccentric spin coating technique is proposed for liner formation, which greatly improves the wafer-level uniformity and reduces the bottom dielectric thickness of the vias located close to the center of the wafer. The measured results show that the fabricated TSVs exhibit low depletion capacitance of 33 fF, low leakage current of 2.2 pA at 20 V, and good barrier property against Cu diffusion even after annealing at 400 degrees C, indicating the feasibility of the proposed technique in high density and low area penalty 3-D large-scale integrated circuits.

DOI： 10.1109/LED.2018.2884452

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/TCPMT.2018.2871764

Language：English   Publishing type：Research paper (other academic)  

© 2018 IEEE. A good habit of measuring blood pressure (BP) daily is helpful for us to stay healthy or to monitor hypertensive conditions. However, the conventional method of measuring BP using a pressure cuff has many weaknesses. In order to eliminate the use of this pressure cuff, we proposed a system using the pulse arrival time (PAT) to measure BP. This PAT can be measured using time difference between the R-peaks of electrocardiogram (ECG) and photoplethysmography (PPG) signals. In our system, we obtained these two signals by using our self-designed ECG and PPG sensors. Our sensors were fabricated in 0.18 μm CMOS technology with a small recording area of about 2.53 mm 2 and 6.25 mm 2 , respectively. Our ECG sensor has variable amplifying gains and can achieve a total maximum gain of 60 dB. Besides that, it has a high pass filter with wide cutoff frequencies between 0.1-200 Hz, and low pass filter with cutoff frequencies of 0.2-10 kHz. The design of our ECG circuit allows us to obtain the ECG signals using fingertips and without using a ground electrode. This compact system has the potential to become a wireless wearable in the future. The measured PAT was fitted into a mathematical model and cuff-less BP readings were obtained. A plot of reference BP using oscillometric cuff and cuff-less BP showed a good correlation of r = 0.83 for systolic blood pressure (SBP). The SBP and diastolic blood pressure (DBP) mean absolute difference for the system are 6.75 mmHg and 6.08 mmHg respectively, which fairly passed the strict standard set by IEEE. In the future, our system will be compared with the use of sphygmomanometer, which is the gold standard, to further evaluate its accuracies.

DOI： 10.1109/BIOCAS.2018.8584776

Language：English   Publishing type：Research paper (other academic)  

© 2018 IEEE. We fabricate FlexTrate TM that is highly integrated bendable and/or rollable electronic systems in which various Si and/or III-V chips are embedded in elastomers and interconnected at the wafer level. This paper describes the process integration of the FlexTrate TM using massively parallel capillary self-assembly and a new single stress buffer layer technologies to form fine-pitch interconnection between the embedded neighboring chips and characterize the electrical/mechanical properties.

DOI： 10.1109/IFETC.2018.8584029

Language：English   Publishing type：Research paper (scientific journal)  

© 2018 IEEE. We investigated the impact of mechanical stress on the cell characteristics of metal-oxide-nitride-oxide-semiconductor (MONOS) structures through experimental observations based on a curvature method for residual stress extraction and an analysis of the interface state. Residual stress induced on a substrate was observed to change from compressive to tensile depending on the tungsten process conditions; a high interface trap density was extracted under a high compressive stress environment based on a silicon bonding model. These interface trap densities were suggested as being attributable to a critical factor weakening the leakage characteristics of the MONOS structure. Besides, interface traps interrupted electron tunneling due to unintended charge trapping at the interface, which deteriorated memory characteristics indicated by a reduction in trap density. These results experimentally supported the effects of mechanical stress on device characteristics and reliability, which could be a straightforward way toward understanding the impact of stress for improved future flash memory applications.

DOI： 10.1109/TED.2018.2865007

Language：English   Publishing type：Research paper (other academic)  

Pulse Arrival Time Measurement with Finger-Based ECG and Trans-Nail PPG Circuits for Cuffless Blood Pressure Monitoring

Language：English   Publishing type：Research paper (other academic)  

© 2018 IEEE. Through-silicon-via (TSV) with polymer liner has attracted considerable attention because a polymer liner has low dielectric constant and good step coverage along the TSV surface, and it can suppress the TSV-induced stress. A polyimide (PI) is used as the polymer liner of TSV. However, there is a modulation of the parasitic capacitance present between TSV metal and Si substrate due to its high polar character. Therefore, in this paper, we propose the deployment of benzocyclobutene (BCB) and polybenzoxazole (PBO) which consists of no-polar groups as the polymer-liner material of TSV for minimizing the capacitance modulation. In this study, a metal-insulator-semiconductor capacitor with blind TSV structures with PI, BCB or PBO liners were fabricated and evaluated. In the case of BCB and PBO liners, remarkable hysteresis suppressions of the C-V curves was observed as compared to that of the PI liner. These results indicate that polar character is one of the most important characters for suppression of the capacitance modulation around TSVs and the detrapped-charge-induced signal noise. Then, BCB and PBO is a promising liner material of TSV for realizing highperformance and high-reliability three-dimensional stacked ICs.

DOI： 10.1109/IITC.2018.8430390

Language：English   Publishing type：Research paper (other academic)  

In this paper, a BCB (benzocyclobutene) resin is employed as a spin-on low-k polymer for TSV liner dielectrics. The BCB is perfectly covered on the sidewall of deep Si holes with a diameter of 8 μm and depth of 40 μm (aspect ratio: 5). The step coverage of the BCB is high and controllable by conditioning the spin rotation speed, spin-coating time, and deforming pressure to eliminate bubbles formed in the deep Si holes prior to spin-coating. Cu-TSVs with the BCB liner dielectric are successfully formed by the subsequent electro-less plated and electroplated Cu technologies. This cost-effective spin-on BCB technology will be applied to via-last TSV fabrication at low temperature below 250 C to give low-capacitance TSVs.

DOI： 10.23919/ICEP.2018.8374320

Language：English   Publishing type：Research paper (other academic)  

The Effect of High Electric Field in Tunnel-FET MONOS Memory on Endurance Characteristics

Language：English   Publishing type：Research paper (scientific journal)  

Development of integrated photoplethysmographic recording circuit for trans-nail pulse-wave monitoring system

Language：English   Publishing type：Research paper (scientific journal)  

A self-assembly and electrostatic (SAE) carrier technology is developed for high-precision and high-throughput chip-to-wafer 3-D integration. In this paper, water surface tension-driven chip assembly is combined with electrostatic adhesion to keep high alignment accuracies obtained by the capillary self-assembly process. The self-assembled chips can be firmly fixed on an SAE carrier wafer by electrostatic adhesion, and then, the chips can be readily detached from the carrier by discharging and transferred to another carrier with a temporary adhesive. This paper describes the impact of chip clamping forces and electrical reliability of the SAE carrier on chips to be 3-D stacked in chip-to-wafer configuration. Through-Si via formation is demonstrated by using a via-last 3-D integration process based on the SAE carrier. The demonstration shows that the SAE carrier maintains higher chip alignment accuracies than does conventional carrier without electrostatic adhesion.

DOI： 10.1109/TED.2017.2767598

Language：English   Publishing type：Research paper (other academic)  

An Integrated Photo-Plethysmography Recording Circuit for Trans-Nail Pulse-Wave Monitoring System

Language：English   Publishing type：Research paper (other academic)  

Wide-range bioelectrical impedance analysis circuit with GIDL-controlled ultrasmall current and ultralow frequency square wave generator

Language：English   Publishing type：Research paper (other academic)  

New Tunnel FET Charge-Trapping Memory with Large Memory Window for Ultra Low Power Operation

Language：English   Publishing type：Research paper (other academic)  

Development of Vertically-Stacked Multi-Shank Si Neural Probe Array with Sharpened Tip for Cubic Spatial Recording

Language：English   Publishing type：Research paper (other academic)  

Characterization of Cu-TSVs Fabricated by a New All-Wet Process

Language：English   Publishing type：Research paper (other academic)  

A local bending stress is induced by coefficient of thermal expansion (CTE) mismatch between underfill material and metal microbumps in three-dimensional IC (3D IC). A high concentration of filler in underfill is effective to suppress the local bending stress. However, it is difficult to apply high concentration of filler due to fine pitch microbumps. On the other hand, manganese nitride-based compound has large negative CTE compared with conventional negative-CTE materials. In this study, we have investigated the effect of manganese nitride-based filler on local bending stress induced by CTE mismatch between underfill and metal microbumps in 3D IC. We observed that manganese nitride-based filler can decrease CTE of underfill compared with conventional silica-based filler. This result indicated that manganese nitride-based filler can reduce keep-out-zone (KOZ) in 3D IC by local bending stress suppression.

DOI： 10.1109/ECTC.2017.209

Language：English   Publishing type：Research paper (scientific journal)  

Massively parallel chip assembly based on multi-interposer block concept is demonstrated for large-area heterogeneous system integration. The chips are aligned in parallel by liquid surface tension and assembled on the Si interposers through oxide-oxide bonding at room temperature without thermocompression. 3-D Cu sidewall interconnects (the width is approximately 20 mu m) climbing over 100-mu m-thick self-assembled chips are formed with a spin-on thick photoresist by electroplating. In addition, 3-D Cu interconnects with a width of nearly 10 mu m are successfully formed across polyimide slopes formed on the sidewall of self-assembled chips. The electrical properties of the 3-D sidewall interconnects are characterized by the daisy chains, resistance distribution, and characteristic fluctuation of CMOS fabricated on the self-assembled chips.

DOI： 10.1109/TED.2017.2705562

Language：English   Publishing type：Research paper (other academic)  

Through-Si-via (TSV) with polymer liner formation has attracted considerable attention because a polymer liner can be formed easily by spin coating, and it has low dielectric constant and good coverage along the TSV surface. A polyimide (PI) was used as the polymer liner of TSV. However, there is a high charge-trap density in the PI layer. These charge traps leads to modulation of the parasitic capacitance present between the TSV metal and the Si substrate. Therefore, in this paper, we propose the deployment of polybenzoxazole (PBO) as the polymer-liner material of TSV for minimizing the capacitance modulation. In this study, a metal-insulator-semiconductor capacitor with blind TSV structure was fabricated with PBO and PI liners. Further, capacitance-voltage (C-V) characteristics of the fabricated MOS capacitor were evaluated. In case of the PBO liner, remarkable suppression of the C-V curve shift was observed as compared to that of the PI liner. These results indicate that the PBO is a promising TSV liner material for realizing high-performance, high-reliability, and low-cost three-dimensional stacked ICs.

DOI： 10.1109/IITC-AMC.2017.7968936

Language：English   Publishing type：Research paper (other academic)  

Three-dimensional IC (3D IC) is a promising method to enhance IC performance. Conventional 3D ICs consist of vertically stacked several thin IC chips those are electrically connected with lots of through-Si vias (TSVs) and metal microbumps. Metal microbumps are surrounded by organic adhesive. An epoxy-based material, so-called underfill, has been widely used to fill the gap between several chips. In general, coefficient of thermal expansion (CTE) of the underfill material is larger than that of metal microbumps. This CTE mismatch induces local bending stress in thinned IC chips. This local bending stress would affect CMOS circuit in thinned IC chips. Therefore, we should suppress the local bending stress to realize 3D IC with high reliability. In this work, we propose a novel underfill with negative-CTE filler which can suppress the local bending stress in 3D IC.

DOI： 10.1109/3DIC.2016.7970031

Language：English   Publishing type：Research paper (other academic)  

For safe electrical stimulation with body-implanted devices, the degradation of stimulus electrodes must be considered because it causes the unexpected electrolysis of water and the destruction of tissues. To monitor the charge injection property (CIP) of stimulus electrodes while these devices are implanted, we have proposed a charge injection monitoring system (CIMS). CIMS can safely read out voltages produced by a biphasic current pulse to a stimulus electrode and CIP is calculated from waveforms of the acquired voltages. In this paper, we describe a wide-range and low-power analog front-end (AFE) for CIMS that has variable gain-frequency characteristics and low-power analog-to-digital (A/D) conversion to adjust to the degradation of stimulus electrodes. The designed AFE was fabricated with 0.18μm CMOS technology and achieved a valuable gain of 20-60 dB, an upper cutoff frequency of 0.2-10 kHz, and low-power interleaving A/D conversion. In addition, we successfully measured the CIP of stimulus electrodes for body-implanted devices using CIMS.

DOI： 10.7567/JJAP.56.04CM05

Language：English   Publishing type：Research paper (scientific journal)  

Development of Si neural probe with piezoresistive force sensor for minimally invasive and precise monitoring of insertion forces
A Si neural probe is one of the most important tools for neurophysiology and brain science because of its various functions such as optical stimulation and drug delivery. However, the Si neural probe is not robust compared with a metal tetrode, and could be broken by mechanical stress caused by insertion to the brain. Therefore, the Si neural probe becomes more useful if it has a stress sensor that can measure mechanical forces applied to the probe so as not to be broken. In this paper, we proposed and fabricated the Si neural probe with a piezoresistive force sensor for minimally invasive and precise monitoring of insertion forces. The fabricated piezoresistive force sensor accurately measured forces and successfully detected insertion events without buckling or bending in the shank of the Si neural probe. This Si neural probe with a piezoresistive force sensor has become one of the most versatile tools for neurophysiology and brain science.

DOI： 10.7567/JJAP.56.04CM04

Language：English   Publishing type：Research paper (scientific journal)  

Evaluation of insertion characteristics of less invasive Si optoneural probe with embedded optical fiber
A less invasive Si optoneural probe with an embedded optical fiber was proposed and successfully fabricated. The diameter of the optical fiber was completely controlled by hydrogen fluoride etching, and the thinned optical fiber can propagate light without any leakage. This optical fiber was embedded in a trench formed inside a probe shank, which causes less damage to tissues. In addition, it was confirmed that the optical fiber embedded in the probe shank successfully irradiated light to optically stimulate gene transfected neurons. The electrochemical impedance of the probe did not change despite the light irradiation. Furthermore, probe insertion characteristics were evaluated in detail and less invasive insertion was clearly indicated for the Si optoneural probe with the embedded optical fiber compared with conventional optical neural probes. This neural probe with the embedded optical fiber can be used as a simple and easy tool for optogenetics and brain science.

DOI： 10.7567/JJAP.56.04CM08

Language：Japanese  

光ファイバ埋め込みシリコンオプト神経プローブの開発

Language：Japanese  

半導体微細加工技術を用いた高機能シリコン神経プローブの開発

Language：English   Publishing type：Research paper (scientific journal)  

Plasma-and water-assisted oxide-oxide thermocompression direct bonding for a self-assembly based multichip-to-wafer (MCtW) 3D integration approach was demonstrated. The bonding yields and bonding strengths of the self-assembled chips obtained by the MCtW direct bonding technology were evaluated. In this study, chemical mechanical polish (CMP)-treated oxide formed by plasma-enhanced chemical vapor deposition (PE-CVD) as a MCtW bonding interface was mainly employed, and in addition, wafer-to-wafer thermocompression direct bonding was also used for comparison. N-2 or Ar plasmas were utilized for the surface activation. After plasma activation and the subsequent supplying of water as a self-assembly mediate, the chips with the PE-CVD oxide layer were driven by the liquid surface tension and precisely aligned on the host wafers, and subsequently, they were tightly bonded to the wafers through the MCtW oxide-oxide direct bonding technology. Finally, a mechanism of oxide-oxide direct bonding to support the previous models was discussed using an atmospheric pressure ionization mass spectrometer (APIMS).

DOI： 10.3390/mi7100184

Language：English   Publishing type：Research paper (other academic)  

Analysis of Charge Injection Characteristics of Stimulus Electrode with Wide-Range Analog Front-end for Body-Implanted Devices

Language：Japanese  

集積化脳神経プローブシステムの過熱保護用温度検出回路の一考察

Language：Japanese  

Fundamental characteristics of AZO transparent stimulus electrode for fully-implantable subretinal prosthesis

Language：Japanese  

Evaluation of Insertion Characteristics of Si Opto-Neural Probe with Embedded Optical fiber

Language：Japanese  

Evaluation of Depth-dependent Interface States at TSV-liner SiO2 Using Multi-well Structured TSV

Language：English   Publishing type：Research paper (other academic)  

Insertion Characteristics Evaluation of Si Opto-Neural Probe with Embedded Optical fiber

Language：English   Publishing type：Research paper (other academic)  

Evaluation of Depth-dependent TSV-liner Interface States Using Multi-well Structure TSV and Charge Pumping Technique

Language：English   Publishing type：Research paper (other academic)  

Development of Si Neural Probe with Piezoresistive Force Sensor for Insertion Force Monitoring

Language：Japanese  

画素間ばらつき補正機能を有する３次元積層人工網膜チップの提案

Language：English   Publishing type：Research paper (scientific journal)  

To enable chronic and stable neural recording, we have been developing an implantable multichannel neural recording system with impedance analysis functions. One of the important things for high-quality neural signal recording is to maintain well interfaces between recording electrodes and tissues. We have proposed an impedance analysis circuit with a very small circuit area, which is implemented in a multichannel neural recording and stimulating system. In this paper, we focused on the design of an impedance analysis circuit configuration and the evaluation of a minimal voltage measurement unit. The proposed circuit has a very small circuit area of 0.23mm(2) designed with 0.18 mu m CMOS technology and can measure interface impedances between recording electrodes and tissues in ultrawide ranges from 100 Omega to 10 M Omega. In addition, we also successfully acquired interface impedances using the proposed circuit in agarose gel experiments. (C) 2016 The Japan Society of Applied Physics

DOI： 10.7567/JJAP.55.04EM12

Language：English   Publishing type：Research paper (scientific journal)  

As three-dimensional (3D) ICs have many advantages, IC performances can be enhanced without scaling down of transistor size. However, 3D IC has mechanical stresses inside Si substrates owing to its 3D stacking structure, which induces negative effects on transistor performances such as carrier mobility changes. One of the mechanical stresses is local bending stress due to organic adhesive shrinkage among stacked IC chips. In this paper, we have proposed an evaluation method for in-plane local stress distribution in the stacked IC chips using retention time modulation of a dynamic random access memory (DRAM) cell array. We fabricated a test structure composed of a DRAM chip bonded on a Si interposer with dummy Cu/Sn microbumps. As a result, we clarified that the DRAM cell array can precisely evaluate the in-plane local stress distribution in the stacked IC chips. (C) 2016 The Japan Society of Applied Physics

DOI： 10.7567/JJAP.55.04EC07

Language：English   Publishing type：Research paper (scientific journal)  

A three-dimensional stacked IC (3D IC) is a one of the promising structures for enhancing IC performances. A 3D IC consists of several materials such as a Si substrate, metal for through Si via (TSV) and microbump, organic adhesive called the underfill, and so on. These materials generate a coefficient of thermal expansion (CTE) mismatch. On the other hand, heat is generated in the Si substrate during circuit operation and in the environment outside 3D IC, for example. Both the CTE mismatch and heat generation induce local stress caused by expansion of the underfill injected around metal microbumps. In this paper, we report our investigation results of the effects of adhesive expansion on transistor performances by finite element method (FEM) simulation and measurement of transistor characteristics. (C) 2016 The Japan Society of Applied Physics

DOI： 10.7567/JJAP.55.04EC03

Language：Japanese  

Evaluation of Local Bending Stress Effects on 3DIC with Retention Time Measurement of DRAM Cell Array

Language：English   Publishing type：Research paper (scientific journal)  

Evaluation of In-plane Local Bending Stress Distribution with DRAM Cell Array for Highly Reliable 3D IC

DOI： 10.7567/JJAP.55.04EC07

Language：English   Publishing type：Research paper (scientific journal)  

The self-assembly of known good dies on hosting substrates using liquid surface tension is a promising technology to create highly integrated 3-D and heterogeneous microelectronic systems. In this paper, we investigate the effects of the edge structures of self-assembled chips on alignment accuracies. Nine types of 100-mu m-thick Si chips (3 mm x 3 mm) with and without step geometries on their hydrophilic or hydrophobic peripheries are self-assembled onto hydrophilic assembly sites formed on planar-and plateau-type host substrates. When hydrophobic peripheries with step geometries are applied to both the edges of chips and assembly sites formed on substrates, the resulting average alignment accuracy is 300 nm. Total accuracy variation within 2 mu m is realized by using either chip or substrate having 10-mu m-height step structures with hydrophobic edges. We obtain a high tolerance for initial offsets indicating positioning misalignment prior to chip release, with the plateau-type substrates and the chips having hydrophobic step structures at the edges. These chips are precisely self-assembled, even under a large initial offset of 1.5 mm in a horizontal direction to both the substrates. The extremely large offset is comparable with 50% of the side length of the 3-mm-square chip. On the other hand, the chips formed by an accurate saw dicing that gives high chip-size accuracies as designed exhibit high alignment accuracies and tolerances when compared with the chips with the hydrophobic step structures and the chips formed by plasma dicing, which offer a large pseudo step with a height of 100 mu m. [2014-0298]

DOI： 10.1109/JMEMS.2015.2480787

Language：Japanese  

三次元集積化技術におけるチップ薄化に伴う局所曲げ応力のDRAMセルアレイを用いた評価

Language：Japanese  

電気/薬液/光による高度脳操作を可能にするシリコン神経プローブの開発

Language：Japanese  

柔軟性を有するフレキシブルケーブル一体化シリコン神経プローブの開発-多機能集積化脳神経プローブシステムの開発1-

Language：Japanese  

低消費電力生体信号処理LSIの設計及びポータブルプロトタイプシステムの開発 (多機能集積化脳神経プローブシステム2)

Language：Japanese  

3D IC用ビアラスト/バックサイドビアプロセスにおける高アスペクト比ビア形成がトランジスタに与える影響評価

Language：Japanese  

Development of Si Opto-Neural Probe having Multiple Optical Waveguides with Reflection Mirror for Cerebrum Cortex Stimulation

Language：Japanese  

Study of local stress induced by circuit operation heating in 3D IC

Language：Japanese  

チップ集積・フレキシブルケーブル一体化シリコン神経プローブの開発(集積化脳神経プローブシステムの開発1)

Language：English   Publishing type：Research paper (other academic)  

Local Stress Effect due to Operation-Heating-Induced Adhesive Expansion on Transistor Performances in 3D IC

Language：English   Publishing type：Research paper (other academic)  

Evaluation of 2-D Local Stress Distribution in Stacked IC Chip Using Stress-induced Retention Time Modulation od DRAM Cell Array

Language：Japanese  

DRAMセルアレイの電荷保持特性を用いた3DICにおける局所曲げ応力の影響評価

Language：English   Publishing type：Research paper (scientific journal)  

Twelve-channel vertical-cavity surface-emitting laser (12-ch VCSEL) chips are heterogeneously self-assembled on Si and glass wafers using water surface tension as a driving force. The VCSEL chips have a high length-to-width aspect ratio, that is, 3 mm long and 0.35 mm wide. The VCSEL chips are precisely self-assembled with alignment accuracies within 2 mu m even when they are manually placed on liquid droplets provided on the host substrate. After the self-assembly of the VCSEL chips and the subsequent thermal compression, the chips successfully emit 850 nm light and exhibit no degradation of their current-voltage (I-V) characteristics. (C) 2015 The Japan Society of Applied Physics

DOI： 10.7567/JJAP.54.030206

Language：Japanese  

表層刺激電極を有する網膜下埋植人工網膜チップモジュールの作製

Language：Japanese  

三次元集積化における異種材料間の熱膨張係数差がおよぼす影響

Language：Japanese  

マルチグルーブシャンクを有する昆虫用In vivoシリコン神経プローブの作製(集積化脳神経プローブシステムの開発３)

Language：Japanese   Publishing type：Research paper (scientific journal)  

In recent years, lots of research on biomedical technologies directly using bio-signals such as BMI (Brain Machine Interface) have been performed intensively. Among bio-signals, ECoG (Electrocorticogram), LFP (Local Field Potential), and AP (Action Potential) are usually recorded especially for diagnosis, treatment, and prevention of brain diseases. These bio-signals have different amplitudes and frequency bandwidths, and the signal intensities vary accordingly with recording electrode conditions and individual variation. Therefore, a multiple bio-signals recording system having adjustable gain and bandwidth is strongly required. In this study, we designed the adjustable gain amplifier appropriate for the system, and fabricated the module composed of the amplifier and a Si neural probe for the multiple bio-signal recording in the deep brain. Additionally, we verified fundamental functions of the module by in vitro experiments.

DOI： 10.11239/jsmbe.52.O-377

Language：Japanese   Publishing type：Research paper (scientific journal)  

In this study, we have developed a chip-surface stimulus electrode array for fully-implantable subretinal prosthesis chip. To realize visual restoration with high resolution, stimulus electrodes should be miniaturized and arrayed with high density. When we miniaturize them, however, their electrochemical impedances become higher and their amount of charge injection become smaller. Additionally, as the number of electrodes increases, it becomes difficult to make electrical connection to each pixel of the retinal prosthesis chip and each electrode by electrical wiring. To overcome these problems, we have developed the stimulus electrodes that have low electrochemical impedances and large charge injection capacities, and established a fabrication process of chip-surface stimulus electrode array. We fabricated the stimulus electrodes made of extremely porous platinum which had large-surface-area compared with conventional Pt. We also fabricated the chip-surface stimulus electrodes array on the subretinal prosthesis chip which surface was rough and covered with insulator film.

DOI： 10.11239/jsmbe.52.O-253

Language：English   Publishing type：Research paper (scientific journal)  

Silicon-lattice distortion in the 50-mu m-thick stacked large scale integrated circuit (LSI) chip over Cu-Sn mu-bumps was studied by synchrotron-assisted micro-X-ray diffraction. The top and bottom surfaces of the upper chip experienced 0.25% and 0.1% tensile strain (equivalent to 450 and 200 MPa of tensile stress), respectively. Si [004] plane showed a maximum tilt value of +0.45 degrees and -0.25 degrees, respectively, over the mu-bump and in the bump-space region. Raman spectroscopy revealed that upper stacked chip experienced similar to 1000 MPa of tensile stress and similar to-200 MPa of compressive stress, respectively, over the mu-bump and bump-space regions. Distorted Si-lattice in 3D-LSIs caused 4% and 12% change in ON-current characteristic for n- and p-MOSFET devices, respectively.

DOI： 10.1109/TED.2013.2295463

Language：English   Publishing type：Research paper (scientific journal)  

A new 3-D integration concept based on reconfigured wafer-to-wafer stacking is proposed. Using reconfigured wafer-to-wafer 3-D integration, many known-good dies (KGDs) can be simultaneously and precisely self-assembled by water surface tension onto a carrier wafer, which is called a reconfigured wafer. In addition, the KGDs on the reconfigured wafer can be transferred and bonded to another target wafer at the wafer level. The alignment accuracy is within 1 mu m when 3 x 3-, 5 x 5-, 4 x 9,- or 10 x 10-mm(2) chips are employed. To 3-D stack many KGDs in a batch process, we developed and employed a self-assembly multichip bonder. KGDs with 20-mu m-pitch Cu-SnAg microbumps covered with a nonconductive film as a preapplied underfill material on their top surface were self-assembled right-side up, and then transferred to the corresponding target interposer wafer upside down. The resulting daisy chain with 500 Cu-SnAg microbumps exhibited ohmic contacts, and the resistance of similar to 40 m Omega/bump was sufficiently low for 3-D large-scale integration application.

DOI： 10.1109/TED.2013.2294831

Language：English   Publishing type：Research paper (scientific journal)  

The development of poly(3,4-ethylenedioxythiophene) (PEDOT) stimulus electrodes and the relationship between the electrical stimulation of a rabbit retina and electrically evoked potential (EEP) were studied in detail. We fabricated implantable flexible cables with Pt, IrOx, and PEDOT electrodes and evaluated the electrochemical impedances (EIs) and charge injection capacities (CICs) of such electrodes. From the result, we confirmed that PEDOT electrodes have both lower EIs and larger CICs than Pt and IrOx electrodes. In addition, we performed in vivo experiments with PEDOT electrodes and clarified the relationships between the electrical stimulation of the rabbit retina and EEP. It is highly probable that visual restoration will be realized safely with PEDOT electrodes. (C) 2013 The Japan Society of Applied Physics

DOI： 10.7567/JJAP.52.04CL03

Language：English   Publishing type：Research paper (scientific journal)  

We have fabricated various types of Si neural probe for in vivo and in vitro neuronal signal recordings by combining standard photolithography with a bulk micromachining process. To place the probe tip at target areas in the brain precisely, the mechanical properties of the Si neural probes with various tip shapes were carefully investigated under different insertion conditions to brain phantoms. As results, the minimum length and penetration force of the Si neural probe were determined from conditions where the Si neural probe began to penetrate the surface of the brain phantom. To control buckling of the Si neural probe, it is necessary to optimize the insertion rate in accordance with the conditions of the Si neural probe. Although the insertion forces of the Si neural probe with a sharpened tip were smaller than those of the Si neural probe with a normal tip, the effect of the probe tip shape became small with increased insertion speeds. (C) 2013 The Japan Society of Applied Physics

DOI： 10.7567/JJAP.52.04CL04

Language：English   Publishing type：Research paper (other academic)  

Investigation of local bending stress effect on complementary metal-oxide-semiconductor characteristics in thinned si chip for chip-to-wafer three-dimensional integration
A three-dimensional LSI (3D-LSI) that vertically stacks Si chips with a number of through-silicon vias (TSVs) and metal microbumps has attracted much attention recently. However, there are some issues to be resolved in the fabrication of 3D-LSI. In this study, we investigated impacts of local bending stress on the performance of a complementary metal-oxide-semiconductor (CMOS) circuit fabricated in a thinned Si chip. First, we proposed a novel method and a test structure to easily induce the local bending stress in the thinned Si chip. Then, we evaluated the distribution of the local bending stress and its effects on the electrical characteristics of metal-oxide-semiconductor field-effect transistor (MOSFETs). As a result, we observed the degradations of the MOSFET currents and CMOS inverter switching behaviors in accordance with the chip local bending. Our experimental results obviously indicate that the local bending stress caused large fluctuations in the performance of the circuit fabricated in the thinned Si chip. © 2013 The Japan Society of Applied Physics.

DOI： 10.7567/JJAP.52.04CB11

Language：English   Publishing type：Research paper (scientific journal)  

We report high-performance MOSFET nonvolatile memory with high-density cobalt-nanodots (Co-NDs) floating gate (the density is as high as 4-5 x 10(12)/cm(2) and the size is similar to 2 nm) and HfO2 high-k blocking dielectric. The device is fabricated using a gate-last process. A large memory window, high-speed program/erase (P/E), long retention time, and excellent endurance till 10(6) P/E cycles are obtained. In addition, the discrete Co-NDs make dual-bit operation successful. The high performance suggests that high work-function Co-NDs combined with high-k blocking dielectric have a potential as a next-generation nonvolatile-memory candidate.

DOI： 10.1109/TNANO.2010.2050331

Language：English   Publishing type：Research paper (scientific journal)  

Metal-oxide-semiconductor field-effect transistor (MOSFET) nonvolatile memories with high-density tungsten nanodots (W-NDs) dispersed in silicon nitride as a floating gate were fabricated and characterized. The W-NDs with a high density of similar to 5 x 10(12) cm(-2) and small sizes of 2-3 nm were formed by self-assembled nanodot deposition (SAND). A large memory window of similar to 1.7 V was observed with bi-directional gate voltage sweeping between -10 and +10 V. Considering that there is no hysteresis memory window for the reference sample without W-NDs, this result indicates the charge trapping in W-NDs or related defects. Finally, the program/erase speed and retention characteristics were investigated and discussed in this paper.

DOI： 10.1088/0268-1242/24/4/045022

Event date： 2020.9

Language：English  

Country：Other  

Event date： 2020.9

Language：English  

Country：Other  

Event date： 2020.9

Language：English  

Country：Other  

Event date： 2020.9

Language：English  

Country：Other  

Event date： 2020.6

Language：English  

Country：Other  

Event date： 2020.6

Language：English  

Country：Other  

Event date： 2020.6

Language：English  

Country：Other  

Event date： 2020.3

Language：English  

Country：Other  

Event date： 2019.12

Language：English  

Country：Other  

Development of underfill with negative-CTE material for high-reliable three-dimensional integrated circuit (3D IC)

Event date： 2019.10

Language：English  

Country：Other  

Investigation of the Underfill with Negative-Thermal-Expansion Material toSuppress Mechanical Stress in 3D Integration System

Event date： 2019.7

Language：English  

Country：Other  

Local Bending Stress Suppression with Negative-CTE Material for High Performance 3D IC

Language：Japanese  

Country：Japan  

C-12-53 Design and Evaluation of MuIti-Biosignal Recording ModuleWith Tumable Bandwidth and Programmable Gain Functions

Language：Japanese  

Country：Japan  

C-12-3 Low Power Characteristics of 3-D Stacked Retinal Prosthesis Chipwith Edge Enhancement Function

Language：Japanese  

Country：Japan  

6PM3-PMN-006 Fabrication and Insertion Characteristics Evaluation of Lower Invasive Si Neural Probe
Recently, many neural probes with various materials and shapes have been developed for treatments of cerebropathy and analyses of the brain function. Among these probes, silicon neural probe attracts much attentions because various kinds of functional structures such as microfluidic channel and optical waveguides can be fabricated by semiconductor micro- and nano-fabrication technologies. On the other hand, it was reported that the recording quality of the neuronal signals deteriorated when nervous tissues were damaged due to insertion and placement of the silicon neural probes. In this research, lower invasive Si neural probes with small shank cross-sections and sharpened tips were successfully fabricated using silicon anisotropic etching techniques. Also, insertion characteristics of the probes were carefully evaluated, indicating that the probe will cause less damages to nervous tissues in the brain.

Language：Japanese  

Country：Japan  

Development of Adjustable Gain-Bandwidth Bio-signal Recording LSI and Si Neural Probe Module
In this paper, we have designed and evaluated an adjustable gain-bandwidth LNA and ADC circuit chip, and successfully fabricated the Si neural probe module with the chip for multiple bio-signal recordings and analysis in a brain. In the bio-signal processing circuit, gain can be adjusted from 20 dB to 60 dB, and lower and upper cut-off frequencies can be adjusted from 56mHz to 35Hz and from 492Hz to 11kHz, respectively. This chip is appropriate for recording of various targeted bio-signals and is robust for variation of electrical environments. This module can realize a higher precision bio-signal recording system and becomes one of the most versatile tools for neurophysiology.

Language：Others  

Venue：アメリカ合衆国 San Diego (USA) Sheraton San Diego Hotel & Marina   Country：Other  

Plasma Assisted Multichip-to-Wafer Direct Bonding Technology for Self-Assembly Based 3D Integration

Language：Others  

Venue：アメリカ合衆国 San Diego （USA） Sheraton San Diego Hotel & Marina   Country：Other  

Impact of Deep-Via Plasma Etching Process on Transistor Performance in 3D-IC with Via-Last Backside TSV

Language：Others  

Venue：アメリカ合衆国 San Diego   Country：Other  

Development of Highly-Reliable Microbump Bonding Technology Using Self-Assembly of NCF-Covered KGDs and Multi-Layer 3D Stacking Challenges

Language：Others  

Venue：日本国 仙台 (仙台国際センター)   Country：Other  

Novel Local Stress Evaluation Method in 3D IC Using DRAM Cell Array with Planar MOS Capacitors

Language：Others  

Venue：日本国 名古屋 (名古屋国際会議場)   Country：Other  

大脳皮質層別光刺激のための反射ミラー集積シリコン神経プローブの開発

Language：Others  

Venue：日本国 大阪 (大阪大学吹田キャンパス)   Country：Other  

回路動作の発熱によって三次元集積回路内に生成される局所応力の影響に関する研究

Language：Others  

Venue：日本国 名古屋 (名古屋国際会議場)   Country：Other  

チップ集積・フレキシブルケーブル一体化シリコン神経プローブの開発(集積化脳神経プローブシステムの開発1)

Language：Others  

Venue：日本国 札幌   Country：Other  

Local Stress Effect due to Operation-Heating-Induced Adhesive Expansion on Transistor Performances in 3D IC

Language：Others  

Venue：日本国 北海道   Country：Other  

Evaluation of 2-D Local Stress Distribution in Stacked IC Chip Using Stress-induced Retention Time Modulation od DRAM Cell Array

Language：Others  

Venue：日本国 名古屋 (名古屋国際会議場)   Country：Other  

DRAMセルアレイの電荷保持特性を用いた3DICにおける局所曲げ応力の影響評価

Language：Others  

Venue：日本国 名古屋 (名古屋国際会議場)   Country：Other  

3D IC用ビアラスト/バックサイドビアプロセスにおける高アスペクト比ビア形成がトランジスタに与える影響評価

Language：Others  

Venue：日本国 東京   Country：Other  

電気/薬液/光による高度脳操作を可能にするシリコン神経プローブの開発

Language：Others  

Venue：日本国 東京   Country：Other  

柔軟性を有するフレキシブルケーブル一体化シリコン神経プローブの開発-多機能集積化脳神経プローブシステムの開発1-

Language：Others  

Venue：日本国 東京   Country：Other  

低消費電力生体信号処理LSIの設計及びポータブルプロトタイプシステムの開発 (多機能集積化脳神経プローブシステム2)

Language：Others  

Venue：日本国 青森   Country：Other  

三次元集積化技術におけるチップ薄化に伴う局所曲げ応力のDRAMセルアレイを用いた評価

Language：Others  

Venue：日本国 東京   Country：Other  

DRAMリテンション測定を用いた3DIC局所曲げ応力の影響評価

Language：Japanese  

Country：Japan  

Design of Regulator Circuit with Over-temperature Protection for Silicon Intelligent Neural Probes

Language：English  

Country：Other  

Noise Propagation through TSV in Mixed-Signal 3D-IC and Investigation of Liner Interface with Multi-Well Structured TSV

Language：English  

Country：Other  

Low-Viscosity Underfill Technology with Negative CTE Filler for High-Density 3D Interconnections

Language：English  

Country：Other  

Spike Timing Dependent Plasticity Characteristics of Tunnel FET based MONOS Memory for Low Power Neural Network Circuits