記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Operating IoT devices by supplying power from an energy harvester and installing AI accelerators in IoT devices are required. Nevertheless, conventionally selected architectures for AI processing require a large amount of power, making it difficult to operate in low-power bands such as IoT devices or even impossible to operate in the first place. Therefore, driving AI accelerators with power that energy harvesters can supply is an issue. However, there has been no past exploration of AI accelerators in the driven of the μW scale. In this paper, we analyze the configuration of Vector Matrix Multiplier, mainly used for AI accelerators, and show the effective configuration for μW scale IoT devices. Using 180nm CMOS to synthesize the four architectures of various sizes, we characterize device performance and analyze energy consumption and circuit area. As a result of the analysis, it shows that the configuration in which all calculations are deployed on the circuit can have the lowest energy consumption. In addition, we found that when there is a limit on circuit area, a configuration in which some calculations are performed in the time domain by lowering the voltage is suitable.

DOI： https://doi.org/10.1109/MCSoC60832.2023.00018

記述言語：日本語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1541/ieejeiss.142.1199

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/GCCE50665.2020.9292032

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1007/978-3-030-61108-8_20

記述言語：英語   掲載種別：研究論文（学術雑誌）  

PC process migration using FPGAs in ring networks
<p>This paper describes a method of process migration of PCs by FPGA-based ring networks. Here the original system configuration is given on the premise that the proposed hybrid cluster control circuit is used, and the communication protocol used on them is determined. The experiment results show that this system has the capability to perform PC process migration with FPGAs. The primary advantage of this system is that it is suitable for low-cost operations in which the PC is shut down after the process is entrusted to the FPGAs, and the result is obtained later.</p>

DOI： 10.1587/comex.2019XBL0163

記述言語：その他  

開催年月日： 2023年12月

記述言語：英語   会議種別：口頭発表（一般）  

開催地：Singapore University of Technology and Design   国名：シンガポール共和国  

Operating IoT devices by supplying power from an energy harvester and installing AI accelerators in IoT devices are required. Nevertheless, conventionally selected architectures for AI processing require a large amount of power, making it difficult to operate in low-power bands such as IoT devices or even impossible to operate in the first place. Therefore, driving AI accelerators with power that energy harvesters can supply is an issue. However, there has been no past exploration of AI accelerators in the driven of the μW scale. In this paper, we analyze the configuration of Vector Matrix Multiplier, mainly used for AI accelerators, and show the effective configuration for μW scale IoT devices. Using 180nm CMOS to synthesize the four architectures of various sizes, we characterize device performance and analyze energy consumption and circuit area. As a result of the analysis, it shows that the configuration in which all calculations are deployed on the circuit can have the lowest energy consumption. In addition, we found that when there is a limit on circuit area, a configuration in which some calculations are performed in the time domain by lowering the voltage is suitable.

その他リンク： https://xplorestaging.ieee.org/document/10387933

記述言語：日本語  

記述言語：その他  

記述言語：その他  

記述言語：その他  

記述言語：その他  

種別：大会・シンポジウム等