Language：English   Publishing type：Research paper (scientific journal)  

Other Link： http://ieeexplore.ieee.org/document/8010799/

Language：English   Publishing type：Research paper (scientific journal)  

This paper investigates a possibility of application of a virtual inductor realized by an integrated defected ground structure (DGS) to design a front-end circuit in CMOS technology. Two types of DGS are analyzed and found that the inductance realized by a square-shaped DGS achieves smaller size and higher quality factor than an H-shaped DGS. Then, a 15-GHz low phase noise voltage-controlled oscillator (VCO) employing the proposed square-shaped DGS in 0.18-μm 1P6M CMOS technology is designed. The fabricated VCO operates from 15.2 to 16.12 GHz and consumes 5-mW power. The measured phase noise is -132.08 dBc/Hz at 10-MHz offset frequency, and this results in the figure of merit (FoM) and FoM taking account of the area to be 189.1 and 199.9 dB, respectively.

DOI： 10.1109/JEDS.2017.2728686

Other Link： http://ieeexplore.ieee.org/document/7984797/

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

DOI： http://dx.doi.org/10.1109/TMTT.2016.2618919

Other Link： http://dx.doi.org/10.1109/TMTT.2016.2618919

Language：English   Publishing type：Research paper (scientific journal)  

DOI： http://doi.org/10.1587/elex.13.20160591

Other Link： http://doi.org/10.1587/elex.13.20160591

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/LMWC.2016.2601300

Other Link： http://dx.doi.org/10.1109/LMWC.2016.2601300

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/LMWC.2016.2597219

Other Link： http://ieeexplore.ieee.org/document/7542143/?arnumber=7542143

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1002/mop.29650

Other Link： http://onlinelibrary.wiley.com/doi/10.1002/mop.29650/full

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1587/elex.13.20151115

Other Link： https://www.jstage.jst.go.jp/article/elex/advpub/0/advpub_13.20151115/_article

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1049/el.2015.4465

Other Link： http://digital-library.theiet.org/content/journals/10.1049/el.2015.4465

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/TCSII.2023.3283532

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1109/IMS37964.2023.10188161

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/TAP.2023.3262977

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1109/IMS37964.2023.10188034

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1109/WPTCE56855.2023.10215978

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1109/WPTCE56855.2023.10216256

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/TCSI.2022.3205367

Language：English   Publishing type：Research paper (other academic)  

A three-Tunable low-pass π-phase compensator technique is proposed and employed in a K-band CMOS power amplifier (PA) to solve the phase shift problem at intermediate nodes of stacked transistor configurations (STCs). Also, it reduces the effects of harmonic signals that in turns, enhances the overall power added efficiency (PAE) of the PA. The PA consists of two stages i.e. driver and main stages, designed using 2-STCs in 180-nm CMOS technology. The fabricated PA achieved a power gain of 12.8 dB at 23 GHz, a maximum PAE of 18.3%, an output power of 1 dB compression point left(mathrm{P}{1 mathrm{~dB } }
ight) of 14.1 1 dBm, and saturated output power left(mathrm{P}{ ext {sat } }
ight) of 16.0 dBm while it consumes chip area of 0.604 mm2 including pads.

DOI： 10.1109/RFIT54256.2022.9882403

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/WPW54272.2022.9853985

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/WPW54272.2022.9901332

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/LMWC.2022.3189347

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1109/IMS37962.2022.9865455

Language：English   Publishing type：Research paper (scientific journal)  

Defected Ground Structure (DGS) based on-chip bandstop filter (BSF) design is proposed for millimeter-wave applications. In the proposed structure, a capacitively loaded T-shape resonator is embedded in the original DGS resonator, which forms two high quality ( Q -) factor small loop resonators. Moreover, this structure, in combination with the feedline and series capacitor, independently realizes the position of two transmission poles: one at each side of the parallel resonance without increasing the layout size. The proposed BSF presents a sharp scattering (S-) parameter response due to the appearance of two transmission poles. As a result, the loaded Q -factor and negative group delay of the BSF are improved. The prototype of the proposed BSF is fabricated in 0.18- μm Complementary Metal-Oxide-Semiconductor (CMOS) process and measured. The measurement result shows a return loss of 1.78 dB at 53.2 GHz center stopband frequency with the negative group delay of 161 pS. The measurement results also agree well with the electromagnetic simulation results. Without pads, the active area of the prototyped BSF is only 0.024 mm2.

DOI： 10.1109/TCSII.2022.3158995

Other Link： https://ieeexplore.ieee.org/document/9733395

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1109/IMS37962.2022.9865438

Language：English   Publishing type：Research paper (other academic)  

Millimeter-wave miniaturized Substrate Integrated Waveguide (SIW) cavity resonator is proposed in 0.18-μm CMOS technology. Miniaturization of the SIW cavity resonator is achieved first by taking 1/16thparts of the standard SIW and employing folded ridge structure. Later this folded ridge sixteenth mode SIW cavity is inductively loaded by a complementary split-ring resonator, which provides internal matching within the cavity resonator. This improved matching enhances the return loss, the external Q-factor, and ultimately, the loaded Q-factor of the proposed cavity resonator. At 60 GHz resonance frequency, the fabricated prototype of the proposed cavity resonator presents a measured reflection coefficient of -33.42 dB, with the external Q- factor 112. Moreover, the active area of the fabricated cavity without measuring pads is only 0.019 mm2.

DOI： 10.1109/IMS37962.2022.9865522

Language：English   Publishing type：Research paper (scientific journal)  

Defected Ground Structure (DGS) based on-chip bandstop filter (BSF) design is proposed for millimeter-wave applications. In the proposed structure, a capacitively loaded T-shape resonator is embedded in the original DGS resonator, which forms two high quality ( ${Q}$ -) factor small loop resonators. Moreover, this structure, in combination with the feedline and series capacitor, independently realizes the position of two transmission poles: one at each side of the parallel resonance without increasing the layout size. The proposed BSF presents a sharp scattering (S-) parameter response due to the appearance of two transmission poles. As a result, the loaded ${Q}$ -factor and negative group delay of the BSF are improved. The prototype of the proposed BSF is fabricated in 0.18- $mu ext{m}$ Complementary Metal-Oxide-Semiconductor (CMOS) process and measured. The measurement result shows a return loss of 1.78 dB at 53.2 GHz center stopband frequency with the negative group delay of 161 pS. The measurement results also agree well with the electromagnetic simulation results. Without pads, the active area of the prototyped BSF is only 0.024 mm2.

DOI： 10.1109/TCSII.2022.3158995

Language：Others   Publishing type：Research paper (scientific journal)  

This letter presents a $V$ -band low phase noise voltage-controlled oscillator (VCO) design using a novel integrated two-branches defected ground structure (DGS) resonator in 0.18- $mu ext{m}$ complementary metal-oxide-semiconductor (CMOS) technology. The proposed DGS resonator is realized in the top metal layer (M6) which has not only a higher quality factor than its predecessors but is also effective to reduce the length of interconnects. The measured carrier frequency and phase noise are 49 GHz and -122.05 dBc/Hz (-102.58 dBc/Hz) at 10-MHz (1-MHz) offset frequencies, respectively. The VCO core consumes 5.5 mW of dc power from the dc supply, which results in a figure of merit (FoM) of -189 dBc/Hz. The proposed VCO using the two-branches DGS resonator may give an alternative low-cost solution for designing a high-performance VCO or frequency synthesizer at $V$ -band and beyond.

DOI： 10.1109/LMWC.2022.3171405

Language：English   Publishing type：Research paper (scientific journal)  

This letter presents a V-band low phase noise voltage-controlled oscillator (VCO) design using a novel integrated two-branches defected ground structure (DGS) resonator in 0.18-μm complementary metal-oxide-semiconductor (CMOS) technology. The proposed DGS resonator is realized in the top metal layer (M6) which has not only a higher quality factor than its predecessors but is also effective to reduce the length of interconnects. The measured carrier frequency and phase noise are 49 GHz and -122.05 dBc/Hz (-102.58 dBc/Hz) at 10-MHz (1-MHz) offset frequencies, respectively. The VCO core consumes 5.5 mW of dc power from the dc supply, which results in a figure of merit (FoM) of -189 dBc/Hz. The proposed VCO using the two-branches DGS resonator may give an alternative low-cost solution for designing a high-performance VCO or frequency synthesizer at V-band and beyond.

DOI： https://doi.org/10.1109/LMWC.2022.3171405

Other Link： https://ieeexplore.ieee.org/document/9773303

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/TCSII.2021.3123954

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/TCSII.2021.3123954

Other Link： https://ieeexplore.ieee.org/document/9594096

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/TCSII.2021.3123655

Other Link： https://ieeexplore.ieee.org/document/9592631

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/TCSII.2021.3123655

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/LMWC.2021.3122149

Other Link： https://ieeexplore.ieee.org/document/9599586

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1038/s41598-021-99405-7

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1038/s41598-021-01677-6

Other Link： https://www.nature.com/articles/s41598-021-01677-6

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/IMS19712.2021.9574938

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1109/WPTC51349.2021.9458177

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/LMWC.2021.3064602

Language：English   Publishing type：Research paper (scientific journal)  

A voltage-controlled oscillator (VCO) is usually designed by maximizing the quality (Q-) factor of the LC-tank resonator to realize a low phase noise. For the same frequency, the ratio of C/L affects the loaded Q-factor (QL) and then phase noise of the VCO. This affect has not been considered so far in the design of VCO because the conventional on-chip spiral inductor cannot be optimized for C/L ratio. This brief first investigates the effects of C/L ratio on the phase noise, and a design methodology for optimized C/L ratio using defected ground structure (DGS) resonator is presented. Then, the resonators were further evaluated based on LgL-product simulation for a fixed Ibias. Employing the proposed resonator, a very low phase noise KUband VCO is designed and implemented in 0.18-lm CMOS technology. The measurement result shows that the proposed VCO has a phase noise of -110.77 dBc/Hz at 1 MHz offset of 17.5 GHz carrier frequency and a frequency tuning range of 8.7%. The VCO consumes 2.3 mW power, which results in a figure of merit (FoM) of -191.95 dB.

DOI： 10.1109/TCSII.2021.3079309

Other Link： https://ieeexplore.ieee.org/document/9428594

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1038/s41598-021-84333-3

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/TCSII.2020.3016385

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.23919/EuMC48046.2021.9338129

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/LMWC.2020.3016136

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1109/IMS30576.2020.9223866

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/LMWC.2020.3004753

Language：Others   Publishing type：Research paper (scientific journal)  

This work proposes a new theory to reduce the phase noise of K-band Voltage-Controlled Oscillators (VCOs) in Complementary Metal Oxide Semiconductor (CMOS) process by introducing one or more transmission poles around the parallel resonance of an LC-tank circuit. Introduction of transmission poles beside the parallel resonance of the LC-tank circuit sharpens the skirt characteristics of the Scattering (S) parameters of the resonators. In return, sharp S-parameters slope enhances the resonator loaded quality (Q) factor without compromising the unloaded Q-factor. In addition, the transmission pole can be realized near the second harmonic of the oscillation. This allocation of the transmission pole leads to the cancellation of this second harmonic and a further reduction of the phase noise. The proposed theory is verified by three different designs based on defected ground structure (DGS) resonators. These designs realized a low-band transmission pole before the parallel resonance, a high-band transmission pole after the parallel resonance, and dual-band transmission poles around the parallel resonance. First, each design is verified and compared to the others using circuit and electromagnetic simulations to establish the Q-factor improvement. Then, each of the resonators is utilized in a differential VCO topology and the phase noise reduction in post-layout simulations is confirmed. Finally, two chips are fabricated in 0.18-μ m CMOS technology and measured. The measurement results are in good agreement with the simulations, which confirm our claim about the proposed theory.

DOI： 10.1109/TCSI.2020.2965007

Language：Others   Publishing type：Research paper (scientific journal)  

This letter presents the improvement of the phase noise (PN) of a voltage-controlled oscillator (VCO) by using a defected ground structure (DGS) resonator with a high-band transmission pole. The proposed DGS resonator has two loops in a coplanar stripline topology. The outer loop is loaded by a series capacitance, which produces the high-band transmission pole. The overall combination has a parallel capacitor to generate the necessary parallel resonance for the VCO operation. This proposed DGS resonator has a sharper impedance and frequency response slope, which results in an improved quality factor. In return, utilization of this DGS resonator into a KU-Band VCO reduces its PN. The prototyped VCO in 0.18-µm CMOS oscillates at 15.52 GHz and shows a PN of −111.27 and −134.07 dBc/Hz at 1- and 10-MHz offset, respectively, while consuming 3.3-mW power. The VCO has a frequency tuning range of 9.5%, which results in a figure of merit (FoM) of −192.7 dB.

DOI： 10.1109/LMWC.2019.2950525

Language：Others   Publishing type：Research paper (other academic)  

In this paper, to characterize the effect of interconnects inductance on VCO's phase noise precisely, two K-band VCO circuits that employ DGS as an inductor are designed and analyzed. It's shown that not only the quality factor of the inductor in resonator has a significant effect on VCO's phase noise, the parasitic inductance of the interconnecting transmission lines will also inflect the phase noise severely. To get the Quantitative analysis, a K-band (25 GHz) VCO is implemented in the 0.18-mu mathrm{m} 1P6M CMOS process and measured.

DOI： 10.1109/APMC46564.2019.9038781

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/LMWC.2019.2935621

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/TCSII.2018.2883671

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/LMWC.2019.2917747

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/mwsym.2019.8700821

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/mwsym.2019.8700853

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/WISNET.2019.8711815

Language：Others   Publishing type：Research paper (other academic)  

This work proposes a new theory to improve the phase noise of a Voltage-Controlled Oscillator (VCO) by introducing dual series resonances around the parallel resonance of an LC-tank circuit. The overall circuit has an improved susceptance slope parameters, which results in the improvement of quality (Q-) factor. Later, its effectiveness is demonstrated to design a low phase noise K-band VCO. The proposed characteristics are realized by a compact defected ground structure (DGS) resonator in a coplanar strip line (CPS) topology. The DGS is loaded by a capacitor, and this combination introduces the parallel resonance. The CPS signal line is implemented with high characteristic impedance to introduce a series inductance. Then, a gap in the CPS is introduced with a loading series capacitance forming a series resonance circuit with the CPS inductance. The overall combination of the series and parallel resonance circuits allowed the targeted two series resonances before and after the parallel resonance. The design is implemented in 0.18-μm CMOS technology, and the post-layout simulation shows that the VCO has a phase noise of -112.31 dBc/Hz @1 MHz offset of 22.07 GHz oscillation, which is 2.3 dB improvement compared to single series resonance VCO. The VCO consumes 4 mW power resulting in a figure of merit (FoM) of -193.2 dB.

DOI： 10.1109/ISCAS.2019.8702264

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/WPT.2018.8639281

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/WPT.2018.8639134

Language：Others   Publishing type：Research paper (other academic)  

A novel technique for a low phase noise and compact K-band Voltage-Controlled Oscillator (VCO) using multi-layers DGS resonator is proposed. The proposed DGS resonator realizes an additional series resonance at the higher side of parallel resonance frequency, and this results in improving both the active and loaded quality factor of the resonator. The proposed resonator has active quality factor of 130 and a compact size of 0.009 mm 2 (0.000459 ? 2 ). Using the proposed DGS resonator in the VCO causes 9 dB improvement in the phase noise compared the VCO implemented using the conventional LC resonator. Two VCOs are designed using the method to illustrate the effect of the series resonance. The first VCO is designed three layers DGS resonator and the other VCO using two layers DGS resonator. The designs are implemented in 0.18 µm CMOS technology and consume 2.9 mW power, and from the post layout results, the first proposed VCO oscillates from 19.6 to 21.3 GHz (8.3 %) and has a phase noise of -113.2 dBc/Hz at 1 MHz offset frequency, and this results in the figure of merit (FoM) and FoM taking account of the tuning range to be -194.4 and -192.7 dB, respectively. The second VCO has a tuning range of 6.1 % and phase noise of -114 dBc/Hz @ 1 MHz offset at 19.6 GHz oscillation.

DOI： 10.1109/MWSCAS.2018.8623874

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.2528/pierm18101608

Language：Others   Publishing type：Research paper (scientific journal)  

This paper presents a new type of a low-loss miniaturized coplanar-waveguide (CPW) transmission line (TL) by employing distributed loading, capacitors and inductors, in 0.18-μm complementary metal-oxide-semiconductor (CMOS) technology. The capacitors are realized by vertical parallel plates made of vias, and a group of open stubs inserted to the signal line, whereas the inductors are realized by high impedance lines. Then, the proposed CPW-TL is employed to design a miniaturized millimeter wave ultra-wideband low-loss Wilkinson power divider/combiner (WPD/C). The proposed distributed loading results in reducing each WPD/C arm length by more than 50% without changing its characteristic impedance and insertion loss (IL). The design is fabricated in 0.18-μm CMOS technology and tested. The measured results show a wideband performance from dc to 67 GHz with 1-dB IL and isolation greater than 15 dB from 36 to 67 GHz. In addition, the fabricated WPD/C achieves an excellent amplitude imbalance and phase imbalance of less than 0.16 dB and 0.45°, respectively. The core chip size is 336 × 165 μm 2 , which is almost 32.8% compact compared to the recently proposed WPD in the same technology.

DOI： 10.1109/TMTT.2018.2873381

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/RFIT.2018.8524088

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/TMTT.2018.2852661

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/TCPMT.2018.2861411

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/IMaRC.2017.8449719

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/ACCESS.2018.2866457

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/IMBIOC.2018.8428951

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/ISCAS.2018.8351670

Language：Others   Publishing type：Research paper (scientific journal)  

A novel 22-GHz-band oscillator using an integrated defected ground structure (DGS) resonator is presented for quasi-millimeter waveband applications. The DGS is etched on the first metal layer (M1) below a 50-Ω microstrip line on the top metal layer (M6) of 0.18-μm one-poly six-metal (1P6M) complementary metal-oxide-semiconductor (CMOS) technology. The proposed oscillator is fabricated using 0.18-μm CMOS technology, and the measured carrier frequency and phase noise are 22.88 GHz and-129.21 dBc/Hz (-108.05 dBc/Hz) at 10-MHz (1 MHz) offset frequency, respectively. The power dissipation is 6 mW that results in a figure of merit to be-188.8 dB. As the DGS resonator could be designed at any high frequency, it may give an alternative design approach of high performance voltage controlled oscillator and frequency synthesizers at K-band and beyond, thus alleviates the problem of self-resonance that a spiral inductor usually encounters at higher frequency.

DOI： 10.1109/LMWC.2018.2801031

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/RWS.2018.8304959

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/TCSII.2017.2740401

Language：Others   Publishing type：Research paper (other academic)  

In the paper, we propose a novel voltage-controlled oscillator (VCO) employing defected ground structure (DGS) band stop filter (BSF). The VCO operates from 15.24 GHz to 15.86 GHz. A square shaped DGS etched at the lowest metal layer (M1) below 50-Ohm microstrip line on the top metal layer (M6) of 0.18 μm 1P6M CMOS process. The proposed square-shaped DGS resonator achieves smaller size and higher quality factor than those of a conventional spiral inductor resonator at Ku band frequency. The power dissipation of the VCO is 4 mW. The measured carrier frequency and phase noise are 15.76 GHz and-127.57 dBc/Hz (104.25 dBc/Hz) at 10 MHz (1 MHz) offset frequency, respectively. The measured figure of merit (FoM) is 182.9 dB. The fabricated chip core VCO size is only 0.084mm2 which increases figure of merit (FoMa) to 194 dB.

DOI： 10.23919/EuMC.2017.8230959

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/LMWC.2017.2750032

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/JEDS.2017.2728686

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/LMWC.2017.2734771

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/APMC.2017.8251489

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/APMC.2017.8251624

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1109/APMC.2016.7931382

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/RWS.2017.7885983

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/TMTT.2016.2618919

Language：Others   Publishing type：Research paper (scientific journal)  

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/APCCAS.2016.7803949

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/LMWC.2016.2601300

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1587/elex.13.20160591

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/LMWC.2016.2597219

Language：English   Publishing type：Research paper (scientific journal)  

Other Link： http://jairo.nii.ac.jp/0001/00389403

Language：Others   Publishing type：Research paper (scientific journal)  

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/WAMICON.2016.7483829

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/WAMICON.2016.7483819

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/EuCAP.2016.7481426

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1049/el.2015.4465

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1002/mop.29650

Language：English   Publishing type：Research paper (other academic)  

A design of an improved open loop resonator on-chip bandpass filter for 60 GHz millimeter-wave applications using 0.18 μm CMOS technology is presented. The proposed on-chip BPF employs H-shaped parasitic structure inserted between two open loop coupled resonator. The adoption of a two open loop coupled resonators BPF and the utilization of two transmissions zero located at 48 and 80 GHz permit a compact size and high selectivity of the BPF. In addition, the parasitic H-shaped structure increases the capacitance between the two resonators, which enables a further reduction of the physical length of the filter and enhances the coupling between the resonators which improve the filter insertion loss. The proposed BPF has a center frequency of 60 GHz, an insertion loss of-2 dB, a 3dB band width of 13 GHz, and a core size 160 × 480 μm2 with total chip size 680 × 280 μm2 (including bonding pads).

DOI： 10.1109/ICM.2015.7438049

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1109/ICM.2015.7438050

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/ICECS.2015.7440292

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1587/elex.13.20151115

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/APCAP.2015.7374402

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/SIRF.2015.7119885

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/EuMC.2014.6986380

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/USNC-URSI.2014.6955519

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/MWSYM.2013.6697475

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/EuCAP.2012.6206127

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/JEC-ECC.2012.6186968

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/MECAP.2010.5724184

Event date： 2015.12

Language：English   Presentation type：Oral presentation (general)  

Country：Morocco  

Other Link： http://ieeexplore.ieee.org/document/7438050/

Event date： 2015.12

Language：English   Presentation type：Symposium, workshop panel (public)  

Country：Egypt  

Other Link： http://ieeexplore.ieee.org/document/7440292/

Event date： 2015.6 - 2015.7

Language：English   Presentation type：Oral presentation (general)  

Country：Indonesia  

Other Link： http://ieeexplore.ieee.org/document/7374402/

Event date： 2015.1

Language：English  

Country：United States  

Other Link： http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=7119885&abstractAccess=no&userType=inst

Event date： 2014.10

Language：English   Presentation type：Oral presentation (general)  

Country：Italy  

Other Link： http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6986380&abstractAccess=no&userType=inst

Event date： 2014.7

Language：English   Presentation type：Oral presentation (general)  

Country：United States  

Other Link： http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6955519&abstractAccess=no&userType=inst

Event date： 2013.6

Language：English   Presentation type：Oral presentation (general)  

Country：United States  

Other Link： http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6697475

Event date： 2012.3

Language：English   Presentation type：Oral presentation (general)  

Country：Czech Republic  

Other Link： http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=6206127&abstractAccess=no&userType=inst

Event date： 2012.3

Language：English   Presentation type：Oral presentation (general)  

Country：Egypt  

Other Link： http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=6186968&abstractAccess=no&userType=inst

Event date： 2010.10

Language：English   Presentation type：Oral presentation (general)  

Country：Egypt  

Other Link： http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5724184&abstractAccess=no&userType=inst

Event date： 2022.12

Language：English   Presentation type：Oral presentation (invited, special)  

Country：Egypt  

Event date： 2022.4

Language：English   Presentation type：Oral presentation (general)  

Venue：London   Country：United Kingdom  

Recently, defected ground structure (DGS) resonators have been employed to design a low phase noise Voltage-Controlled Oscillator (VCO) for quasi-millimeter wave applications [10]. A few advantages of such VCOs are that a DGS resonator has a higher Q-factor than an on-chip spiral inductor, and it has a higher self-resonance frequency compared to a conventional LC resonator so that a stable inductance value with respect to the frequency can be realized. However, one of its drawbacks is that the tuning range of DGS-based VCOs is limited. In this paper, a method to realize a wide tuning range of DGS-based VCOs has been proposed using two interconnected DGS resonators. As a result, the designed VCO implemented in 0.18-µm 1P6M CMOS technology achieves a 19.8% tuning range with the best phase noise performance of -109.43dBc/Hz at 1-MHz offset frequency in simulations. The experiment result shows that the fabricated VCO has a phase noise of -108.41dBc/Hz at 1-MHz offset frequency with the carrier frequency of 18.51GHz, which exhibits good agreement with the simulation.

Other Link： https://ieeexplore.ieee.org/document/9783689

Event date： 2022.4

Language：English   Presentation type：Oral presentation (general)  

Country：United Kingdom  

Other Link： https://ieeexplore.ieee.org/document/9784336

Event date： 2022.4

Language：English   Presentation type：Oral presentation (general)  

Country：United Kingdom  

Other Link： https://ieeexplore.ieee.org/document/9784207

Event date： 2022.4

Language：English   Presentation type：Oral presentation (general)  

Country：United Kingdom  

Other Link： https://ieeexplore.ieee.org/document/9784281

Event date： 2022.4

Language：English   Presentation type：Oral presentation (general)  

Venue：London   Country：United Kingdom  

This paper proposes a compact, high quality (Q-) factor cavity in commercial CMOS technology for terahertz band applications. The proposed cavity consists of a folded quarter-mode substrate integrated waveguide (QMSIW) topology. It also outlines some guidelines for creating layouts with specific foundries, particularly for building vertical walls using an array of vias. The cavity was implemented in 0.18 µm CMOS technology and measurements were taken. The measurements showed that the resonant frequency and reflection coefficient were 96.9 GHz and -30.14 dB, respectively, in good agreement with the simulation results. The area of the proposed cavity was 0.0506 mm2 without measurement pads, which is only 2.4% and 8.9% when compared to the standard full-mode SIW cavity and the recently proposed 87 GHz.

Other Link： https://ieeexplore.ieee.org/document/9784193

Event date： 2021.6

Language：English   Presentation type：Oral presentation (general)  

Country：United States  

Other Link： https://ieeexplore.ieee.org/document/9574938

Event date： 2021.6

Language：English   Presentation type：Oral presentation (general)  

Country：United States  

Other Link： https://ieeexplore.ieee.org/document/9458177

Event date： 2021.1

Language：English   Presentation type：Oral presentation (general)  

Country：Netherlands  

Other Link： https://ieeexplore.ieee.org/document/9338129

Event date： 2017.1

Language：English   Presentation type：Oral presentation (general)  

Country：United States  

Other Link： http://ieeexplore.ieee.org/document/7885983/

Event date： 2016.10

Language：English   Presentation type：Oral presentation (general)  

Country：Korea, Republic of  

Other Link： http://ieeexplore.ieee.org/document/7803949/