Language：Others  

Language：Japanese  

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/IPDPSW59300.2023.00115

Language：English   Publishing type：Research paper (international conference proceedings)  

DOI： https://doi.org/10.1007/978-3-031-29927-8_28

Language：Others  

DOI： 10.1007/978-3-031-29927-8_28

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/MCSoC57363.2022.00041

Publishing type：Research paper (international conference proceedings)   Publisher：ACM  

We study software automatic tuning. Automatic tuning tools using iterative one-dimensional search estimate hyperparameters of machine learning programs. Iterative one-dimensional search searches the parameter space consisting of possible values of the parameters to be tuned by repeatedly measuring and evaluating the target program. Since it takes time to train a machine learning program, estimating the optimal hyperparameters is time-consuming. Therefore, we propose a method to reduce the time required for automatic tuning by parallelization of iterative one-dimensional search. For parallelization, we use multiple job execution on a supercomputer that can utilize multiple GPUs, which is effective for machine learning. In this method, each job measures different hyperparameters. The next search point is determined by referring to the data obtained from each job. The target program is a pedestrian path prediction application. This program predicts future routes and arrival points based on past pedestrian trajectory data. The program is intended to be used in a variety of locations, and the locations and movement patterns will vary depending on the dataset used for training. We hypothesized that the estimation results of one dataset could be used for automatic tuning of another dataset, thereby reducing the time required for automatic tuning. Experimental results confirm that the parallelized iterative one-dimensional search reduces the estimation time from 89.5 hours to 4 hours compared to the sequential search. We also show that the iterative one-dimensional search efficiently investigates the point at which the performance index improves. Moreover, the hyperparameters estimated for one data set are used as the initial point for the search and automatic tuning for another data set. Compared to the results of automatic tuning with the currently used hyperparameters as the initial values, both the number of executions and execution time were reduced.

DOI： 10.1145/3578178.3578235

Scopus

researchmap

Other Link： https://dblp.uni-trier.de/db/conf/hpcasia/hpcasia2023.html#FujikaYTFKOK23

Publishing type：Research paper (scientific journal)  

DOI： 10.48550/arXiv.2312.05779

researchmap

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/DASC/PiCom/CBDCom/Cy55231.2022.9927975

Language：Japanese  

Language：Japanese  

Development Status of ABINIT-MP in 2022
We have been developing the ABINIT-MP program for fragment molecular orbital (FMO) calculations over 20 years. Several improvements for accelerated processing were made after the release of Open Version 2 Revision 4 at September 2021. Functionalities were enhanced as well. In this short report, we summarize such developments toward the next release of Revision 8

DOI： 10.2477/jccj.2022-0037

Language：Others  

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1585/pfr.17.2403079

Language：Japanese  

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.48550/arXiv.2203.14188

Language：Japanese  

フラグメント分子軌道計算（FMO）を行うソフトウェアABINIT-MPについて、名古屋大学情報基盤センターが提供するスーパーコンピュータ「不老」TypeⅠサブシステム（CPU:ARMA64FX）を用いて性能評価した結果を示す。

Language：Japanese  

本発表ではサポートベクターマシン（SVM）にCMOSアニーリングを適用することを検討する。SVMとは線形入力素子を利用して2クラスのパターン識別器を構成する手法である。訓練サンプルから、各データ点との距離が最大となるマージン最大化超平面を求めるという基準で線形入力素子のパラメータを学習する。この際誤分類の許容度や汎化性能におけるハイパーパラメータの調整が必要になるが本研究では交差エントロピー損失を評価指標としてチューニングする。一方、CMOSアニーリングマシンは「組合せ最適化問題」に対して高速に最適解を出すアニーリング技術を常温環境で利用できる非ノイマン型計算機である。これを2クラス分類問題に用いSVMと比較する。

Language：Japanese  

Mesh tensorflowは2019年に提案された分散型深層学習用の言語である。モデル並列によって大規模ニューラルネットワーク学習を行うといった特徴を持つソフトウェアだが、BERT型の構造を持つニューラルネットワークのみにしか使用できない点もあり性能評価事例が多くない。そこで本研究ではGPUスパコン上でMesh Tensorflowのサンプルコードの性能評価を行う。コード内ではパラメタとしてバッチサイズやレイアウトルール等が存在するため、それらを考慮した性能評価を行う。

CiNii Research

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/IPDPSW52791.2021.00109

Language：Others   Publishing type：Research paper (other academic)  

DOI： 10.1109/IPDPSW52791.2021.00117

Language：Japanese  

我々は複数のパラメータを同時に推定する手法として，パラメータ空間における反復一次元探索を提案している．この手法はパラメータの組み合わせを自動的に選択し，その実行性能を実測，さらに別の組み合わせの選択を繰り返すことで探索を行う．この提案手法を機械学習プログラムに適用する．機械学習には複数のハイパーパラメータが存在し，適切なハイパーパラメータの組み合わせを推定するには時間がかかる．本研究は歩行者経路予測アプリケーションに用いる機械学習のハイパーパラメータについて適切な組み合わせを推定し，マルチGPU環境を利用して実測処理を並列化することで，約15日かかる推定が約12時間で完了することを示す．

Language：Japanese  

我々は反復一次元探索を用いた自動チューニングの研究に取り組んでおり，マルチGPU環境を用いた機械学習のプログラムのハイパーパラメータの最適化を進めている．機械学習は同一のハイパーパラメータを用いても毎回教師データが変わるなど同一の結果にならないため，自動チューニングの結果にブレが生じる．このブレに対して，これまで，我々は推定したパラメータに対して追加測定を行い自動チューニングの安定性を高める手法を提案してきた．本研究では，歩行者経路予測アプリケーションに用いる機械学習プログラムに適用しマルチGPU環境で推定したハイパーパラメータの値を並列化し複数回まとめて追加測定することによる，自動チューニングの精度向上について示す．

Language：Others  

Language：Others  

Language：Others  

Language：Others  

Language：Others  

Language：Others  

Language：English  

Language：Others  

Language：Others  

Language：Others  

Language：Others  

Language：Others  

Language：Others  

Language：Others  

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1109/CANDARW51189.2020.00044

Language：Others  

Language：Others  

Language：Others  

Language：Others  

Language：Others  

Language：Others  

Utilization of Low-precision and Mixed-precision Calculation in Parareal Method

Language：English   Publishing type：Research paper (other academic)  

In the present paper, we propose an efficient direct-iterative hybrid solver for sparse matrices that can derive the scalability of the latest multi-core, many-core, and vector architectures and examine the execution performance of the proposed SLOR-PCR method. We also present an efficient implementation of the PCR algorithm for SIMD and vector architectures so that it is easy to output instructions optimized by the compiler. The proposed hybrid method has high cache reusability, which is favorable for modern low B/F architecture because efficient use of the cache can mitigate the memory bandwidth limitation. The measured performance revealed that the SLOR-PCR solver showed excellent scalability up to 352 cores on the cc-NUMA environment, and the achieved performance was higher than that of the conventional Jacobi and Red-Black ordering method by a factor of 3.6 to 8.3 on the SIMD architecture. In addition, the maximum speedup in computation time was observed to be a factor of 6.3 on the cc-NUMA architecture with 352 cores.

DOI： 10.1145/3368474.3368484

Language：Japanese  

Language：English   Publishing type：Research paper (other academic)  

Optimization of Numerous Small Dense-Matrix-Vector Multiplications in H-matrix Arithmetic on GPU

DOI： 10.1109/MCSoC.2019.00009

Language：Japanese  

GPUによる階層型行列計算法の高速化に向けた多数の小密行列ベクトル積計算の最適化

Language：English   Publishing type：Research paper (international conference proceedings)  

Language：English   Publishing type：Research paper (other academic)  

Performance evaluation of the MODYLAS application on modern multi-core and many-core environments

Language：Japanese   Publishing type：Research paper (scientific journal)  

Language：Japanese  

高精度行列‐行列積のためのBatched BLASおよび疎行列演算を用いた実装方式のGPU環境での性能評価

Language：Japanese  

マルチコア・メニーコア計算機環境におけるChebyshev基底通信削減CG法の性能評価

Language：Japanese  

512bit SIMD環境における分子動力学アプリケーションMODYLASの性能評価

Language：English   Publishing type：Research paper (other academic)  

HACApK is a software package for solving dense linear systems of equations and is used in other software packages, like ppohBEM for solving boundary integral equations. To enable the solution of large-scale boundary value problems, HACApK hierarchically compresses the coefficient matrix and uses the BiConjugate Gradient Stabilized (BiCGStab) method for solving the linear system. To extend HACApK's capability, this paper outlines how we ported the HACApK linear solver onto GPU clusters. Though the potential of GPUS has been widely accepted in high-performance computing, it is still a challenge to utilize the GPUS for a solver, like HACApK, that requires fine-grained irregular computation and global communication. To utilize the GPUS, we integrated the variable-size batched GPU kernel that was recently released in the MAGMA software package. This is the first time the variable-size batched kernels were used in a solver or application code. We discuss several techniques to improve the performance of the batched kernel and demonstrate the effects of these techniques on two state-of-The-Art GPU clusters. For instance, with two 14-core Intel Xeon CPUs and four NVIDIA P100 GPUS per node, the GPU kernel obtained a solver speedup of 8× on one node and 4× on eight nodes. We also show that when the inter-GPU communication becomes significant, the solution time can be further reduced by a factor of 2× by carefully designing the communication layer with the underlying node architecture in mind.

DOI： 10.1109/IPDPS.2018.00102

Language：Japanese   Publishing type：Research paper (scientific journal)  

Language：Japanese  

Mellanox社のスイッチ装置への集団通信オフロード機能による集団通信隠蔽効果の調査

Language：Japanese  

GPGPUによる高精度行列‐行列積アルゴリズムのためのBatched BLASを用いた実装方式の提案

Language：Japanese  

Chebyshev基底通信削減CG法のマルチコア・メニーコア計算環境における性能評価

Language：Japanese   Publishing type：Research paper (scientific journal)  

Language：Japanese   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

In molecular dynamics (MD) simulations, calculations of potentials and their derivatives by coordinate, i.e., forces, in a pairwise additive manner such as the Lennard–Jones interactions and a short-range part of the Coulombic interactions form the main part of arithmetic operations. It is essential to achieve high thread-level parallelization efficiency of these pairwise additive calculations of potentials and forces to use current supercomputers with many-core architectures effectively. In this paper, we propose four new thread-level parallelization algorithms for the pairwise additive potential and force calculations. We implement the four codes in a MD calculation code based on the fast multipole method. Performance benchmarks were taken on the FX100 supercomputer and Intel Xeon Phi coprocessor. The code succeeds in achieving high thread-level parallelization efficiency with 32 threads on the FX100 and up to 60 threads on the Xeon Phi.

DOI： 10.1007/s11227-018-2272-2

Language：Japanese  

Software Auto-Tuning for Hierarchical Matrix Computation

Language：Others   Publishing type：Research paper (other academic)  

Performance of Hierarchical-matrix BiCGStab Solver on GPU Clusters.

DOI： 10.1109/IPDPS.2018.00102

Language：English   Publishing type：Research paper (international conference proceedings)  

DOI： 10.1007/978-3-319-69953-0_16

Other Link： https://doi.org/10.1007/978-3-319-69953-0_16

Language：Japanese  

高精度行列‐行列積アルゴリズムにおけるBatched BLASの適用

Language：English   Publishing type：Research paper (other academic)  

The demand for dense matrix computation in large scale and complex simulations is increasing
however, the memory capacity of current computer system is insufficient for such simulations. Hierarchical matrix method (H -matrices) is attracting attention as a computational method that can reduce the memory requirements of dense matrix computations. However, the computation of H -matrices is more complex than that of dense and sparse matrices
thus, accelerating the H -matrices is required. We focus on H -matrix - vector multiplication (HMVM) on a single NVIDIA Tesla P100 GPU. We implement five GPU kernels and compare execution times among various processors (the Broadwell-EP, Skylake-SP, and Knights Landing) by OpenMP. The results show that, although an HMVM kernel can compute many small GEMV kernels, merging such kernels to a single GPU kernel was the most effective implementation. Moreover, the performance of BATCHED BLAS in the MAGMA library was comparable to that of the manually tuned GPU kernel.

DOI： 10.1007/978-3-319-69953-0_16

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1007/978-3-319-69953-0_16

Language：Japanese   Publishing type：Research paper (other academic)  

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1007/s11227-018-2272-2

Other Link： https://link.springer.com/article/10.1007/s11227-018-2272-2

Language：Japanese   Publishing type：Research paper (scientific journal)  

九州大学情報基盤研究開発センターではスーパーコンピュータシステム “ITO” を導入し，2017 年 10 月より一部システムによる試験運用を開始，2018 年 1 月より全システムによるサービス提供を予定している．本システムは最新の CPU や GPU を搭載していることに加えて，オープンデータの活用やパブリッククラウドサービスとの連携を考慮した挑戦的なシステムである．本稿では ITO の設計を紹介し，既に試験運用を開始しているバックエンドサブシステム B を用いて測定した性能評価の結果を示す．

Language：Japanese  

非ブロッキング集団通信の通信隠蔽効果に関する調査

Language：Japanese  

スーパーコンピュータシステムITOの性能評価

Language：Japanese   Publishing type：Research paper (scientific journal)  

本稿では，非ブロッキング集団通信による通信隠蔽技術について，特にプログレススレッドを用いた場合の実用上の効果を計測し，評価した．従来の通信隠蔽率のみを計測するベンチマークプログラムでは，プログレススレッドを利用した場合の計算性能の低下による影響が計測結果に反映されないため，実用性の検証が困難である．そこで本稿では，計算と通信を含む総合的な性能評価を行うため，スレッド並列とプロセス並列によるハイブリッド並列のベンチマークプログラムを作成した．このプログラムは，通信と計算の量をそれぞれ明示的に指定するため，プログレススレッドへの CPU コアの割り当て方法やスレッドのスケジューリングポリシーなどの実行時パラメータを変化させた場合の，計測結果の相互比較も可能となった．このプログラムを，Fujitsu PRIMERGY CX 400 および Fujitsu PRIMEHPC FX 100 上で実行し，性能を計測した．その結果，Alltoall では，適切な実行時パラメータを選択することにより，プログラム全体としての性能向上が見込めることが分かった．一方，Allreduce では，特にノード内で複数のプロセスを起動した場合に，性能が低下する場合があることが分かった．これらの結果から，非ブロッキング集団通信の利用にあたっては，使用する集団通信の種類やメッセージサイズ，計算量等に応じて，効果を事前に調査することが重要であることを確認した．また，非ブロッキング集団通信を推進するもう一つの手段であるオフロード機能について，Mellanox 社の SHArP 機能を用いた場合の通信隠蔽効果を予備評価し，通信隠蔽による性能向上が見込めることを確認した．

Language：Japanese  

スーパーコンピュータ上でのDeep Learning学習環境の初期構築

Language：Japanese  

階層型行列計算のGPU向け最適化

Language：Japanese   Publishing type：Research paper (scientific journal)  

階層型行列は小さな密行列と低ランク近似行列から構成される行列である．密行列を階層型行列によって近似することで，大規模な計算をより少ないメモリ量で行うことが可能となる．しかし階層型行列を用いた計算は複雑であるため，最適化が求められている．我々はこれまで階層型行列を用いた境界要素法による静電場解析問題の実装と評価をマルチコア CPU やメニーコアプロセッサにて実施してきた．本稿では，階層型行列を係数行列に持つ線形方程式に対する反復法を対象として，GPU クラスタ上での性能評価や最適化に取り組んだ結果を示す．主要な計算部である階層型行列ベクトル積計算を構成する密行列ベクトル積計算を MAGMA BLAS に行わせることで高速化を目指したところ，GPU カーネル起動のオーバーヘッドにより実行時間が増大したが，BATCHED MAGMA を用いることで大幅に性能が改善した．実験環境としては TSUBAME 2.5 (最大 8 ノード / 1 ノードあたり 1 GPU) および Reedbush-H (最大 8 ノード / 1 ノードあたり 1 GPU) を使用し，それぞれ 8 ノードまで性能向上は得られたが，ノード数を増やした場合には MPI 処理の時間も目立ってきており，さらなる最適化が求められる結果となった．

Language：Japanese  

GPUクラスタ上における階層型行列計算の最適化

Language：English   Publishing type：Research paper (other academic)  

Language：English   Publishing type：Research paper (other academic)  

Pascal vs KNL: Performance Evaluation with ICCG Solve

Language：English   Publishing type：Research paper (other academic)  

In this paper, we focus on auto-tuning (AT) performance on nonuniform memory access (NUMA) and many-core architectures. Code from the finite difference method (FDM) is selected to evaluate AT performance, and results on the Xeon Phi (Knights Landing, KNL) for four kinds of memory (FLAT and CACHE) and cluster modes (QUADRANT and SNC4) yielded the following findings: (1) The KNL memory mode did not affectoverall performance, except FLAT-SNC4. The difference ofexecution time for the CACHE mode to the FLAT mode was only 0.99%. (2) Hyper-threading (HT) technology worked well, and yielded 1.86x (baseline) and 1.50x (with AT). (3) Varying hybrid MPI/OpenMP execution was very effective for KNL. Themaximum factors of speedups were 2.16x in the baseline and2.91x with AT. (4) AT with code selection persisted as a powerful tool, even in KNL. We obtained speedups by AT for a maximum of 1.64x. Moreover, we had room to speedup by a further 1.31x by adapting AT for the fastest execution.

DOI： 10.1109/IPDPSW.2017.27

Language：Japanese  

A Consideration of Auto-tuning Technology for Finite Difference Method in Post Moore's era

Language：Japanese  

GPU搭載スーパーコンピュータReedbush‐Hの性能評価

Language：Japanese  

OpenACCを用いたICCG法ソルバーのPascal GPUにおける性能評価

Language：Japanese  

Xeon Phi+OmniPath環境におけるOpenMP,MPI性能最適化

Language：Japanese  

Optimization of ICCG Solver for Intel Xeon Phi

Language：Japanese  

Performance Evaluation of Pipelined CG Method

Language：Japanese  

データ解析・シミュレーション融合スーパーコンピュータシステムReedbush‐Uの性能評価

Language：Japanese  

高バンド幅メモリ環境における数値計算アルゴリズムの変革と自動チューニング技術~FDMコードを例にして~

Language：Japanese  

3次元積層技術による高メモリバンド幅時代の自動チューニング~FDMコードを例にして~

Language：English   Publishing type：Research paper (other academic)  

ppOpen-HPC is an open source infrastructure for development and execution of large-scale scientific applications on post-peta-scale (pp) supercomputers with automatic tuning (AT). ppOpen-HPC focuses on parallel computers based on many-core architectures and consists of various types of libraries covering general procedures for scientific computations. The source code, developed on a PC with a single processor, is linked with these libraries, and the parallel code generated is optimized for post-peta-scale systems. In this article, recent achievements and progress of the ppOpen-HPC project are summarized.

DOI： 10.1007/978-4-431-55420-2_2

Language：Japanese  

階層型行列ベクトル積のメニーコア向け最適化

Language：Japanese  

FPGAを用いた階層型行列ベクトル積

Language：English   Publishing type：Research paper (other academic)  

In this paper, we propose an effective kernel implementation for an application of the finite difference method (FDM) by merging computations of central-difference and explicit time expansion schemes without IF statements inside the loops. The effectiveness of the implementation depends on the CPU architecture and execution situation, such as the problem size and the number of MPI processes and OpenMP threads. We adopt auto-tuning (AT) technology to select the best implementation. The AT function for the selection, referred to as «code selection», is implemented in an AT language, namely, ppOpen-AT. The results of experiments conducted using current advanced CPUs (Xeon Phi, Ivy Bridge, and FX10) indicated that crucial speedups of conventional AT are achieved by code selection. In particular, the heaviest kernels achieved speedups of 4.21x (Xeon Phi), 2.52x (Ivy Bridge), and 2.03x (FX10).

DOI： 10.1109/IPDPSW.2016.49

Language：English   Publishing type：Research paper (other academic)  

For application programmers, reducing efforts for optimizing programs is an important issue. Our solution of this issue is an auto-tuning (AT) technique. We are developing an AT language named ppOpen-AT. We have shown that this language is useful for multi-and many-core parallel programming. Today, OpenACC attracts attention as an easy and useful graphics processing unit (GPU) programming environment. While OpenACC is one possible parallel programming environment, users have to spend time and energy in order to optimize OpenACC programs. In this study, we investigate the usability of ppOpen-AT for OpenACC programs and propose to expand ppOpen-AT for further optimization of OpenACC.

DOI： 10.1109/IPDPSW.2016.123

Language：Japanese  

Language：English   Publishing type：Research paper (other academic)  

For application programmers, reducing efforts for optimizing programs is an important issue. Our solution of this issue is an auto-tuning (AT) technique. We are developing an AT language named ppOpen-AT. We have shown that this language is useful for multi-and many-core parallel programming. Today, OpenACC attracts attention as an easy and useful graphics processing unit (GPU) programming environment. While OpenACC is one possible parallel programming environment, users have to spend time and energy in order to optimize OpenACC programs. In this study, we investigate the usability of ppOpen-AT for OpenACC programs and propose to expand ppOpen-AT for further optimization of OpenACC.

DOI： 10.1109/IPDPSW.2016.123

Language：English   Publishing type：Research paper (other academic)  

In this paper, we propose an effective kernel implementation for an application of the finite difference method (FDM) by merging computations of central-difference and explicit time expansion schemes without IF statements inside the loops. The effectiveness of the implementation depends on the CPU architecture and execution situation, such as the problem size and the number of MPI processes and OpenMP threads. We adopt auto-tuning (AT) technology to select the best implementation. The AT function for the selection, referred to as "code selection", is implemented in an AT language, namely, ppOpen-AT. The results of experiments conducted using current advanced CPUs (Xeon Phi, Ivy Bridge, and FX10) indicated that crucial speedups of conventional AT are achieved by code selection. In particular, the heaviest kernels achieved speedups of 4.21x (Neon Phi), 2.52x (Ivy Bridge), and 2.03x (FX10).

DOI： 10.1109/IPDPSW.2016.49

Language：Japanese  

Language：Japanese  

Performance Evaluation of a Hierarchical Auto-tuning Function toward to Post Moore's Era

Language：Japanese  

FPGAを用いた疎行列数値計算の性能評価

Language：Japanese  

Optimization of matrix assembly process in FEM applications on manycore architectures

Language：English   Publishing type：Research paper (other academic)  

In this paper, we present a directive-based auto-tuning (AT) framework, called ppOpen-AT, and demonstrate its effect using simulation code based on the Finite Difference Method (FDM). The framework utilizes well-known loop transformation techniques. However, the codes used are carefully designed to minimize the software stack in order to meet the requirements of a many-core architecture currently in operation. The results of evaluations conducted using ppOpen-AT indicate that maximum speedup factors greater than 550% are obtained when it is applied in eight nodes of the Intel Xeon Phi. Further, in the AT for data packing and unpacking, a 49% speedup factor for the whole application is achieved. By using it with strong scaling on 32 nodes in a cluster of the Xeon Phi, we also obtain 24% speedups for the overall execution.

DOI： 10.1109/IPDPSW.2015.11

Language：Japanese  

ppOpen‐ATによるOpenACCプログラムの自動チューニング

Language：Japanese  

ppOpen‐ATによる静的コード生成で実現する自動チューニング方式の評価

Language：Japanese  

Parallel FEM application using ppOpen‐APPL/FVM

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SCG‐AT:静的コード生成のみによる自動チューニング実現方式

Language：Japanese  

ppOpen‐ATを用いたOpenACCプログラムの自動チューニング

Language：Japanese  

Towards Auto-tuning for Era of 200+ Threads Parallelism on One Node : An Adaptation of an FDM code

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An Auto-Tuning Methodology in The Era of Over 200 Threads per Node : Adaptation of Code Optimization to an FDM Program

Language：Japanese  

Language：English   Publishing type：Research paper (other academic)  

In this paper, we present a directive-based auto-tuning (AT) framework, called ppOpen-AT, and demonstrate its effect using simulation code based on the Finite Difference Method (FDM). The framework utilizes well-known loop transformation techniques. However, the codes used are carefully designed to minimize the software stack in order to meet the requirements of a many-core architecture currently in operation. The results of evaluations conducted using ppOpen-AT indicate that maximum speedup factors greater than 550% are obtained when it is applied in eight nodes of the Intel Xeon Phi. Further, in the AT for data packing and unpacking, a 49% speedup factor for the whole application is achieved. By using it with strong scaling on 32 nodes in a cluster of the Xeon Phi, we also obtain 24% speedups for the overall execution.

DOI： 10.1109/IPDPSW.2015.11

Language：Japanese  

1ノード200超スレッド時代の自動チューニング手法~FDMコード最適化を中心に~

Language：Japanese  

未知語の音声クエリに対する複数検索結果を用いた音声中の検索語検出

Language：Japanese  

動的な並列実行機構を用いたSpMV実装の性能評価

Language：English   Publishing type：Research paper (other academic)  

In this paper, we propose an Auto-tuning (AT) function with an AT language for a dedicated numerical library with respect to supercomputers in operation. The AT function is based on well-known loop transformation techniques, such as loop split, fusion, and re-ordering of statements. However, loop split with copies or increase of computations, and loop fusion to the split loop are taken into account by utilizing user knowledge.

DOI： 10.1109/MCSoC.2014.22

Language：English   Publishing type：Research paper (other academic)  

In this study, we evaluate the performance of sparse matrix-vector multiplication (SpMV) using the compressed row storage (CRS) format on CPUs and MIC. We focus on the relationship between OpenMP scheduling and performance. The performance of SpMV is measured using various OpenMP scheduling settings and the results are analyzed, which show that OpenMP scheduling has a considerable effect on the performance of SpMV. We confirm that some scheduling settings resulted in performance improvements compared with default scheduling for particular matrices. The results of the evaluation show that the performance of SpMV is improved by up to 1.57 times compared with SPARC64 IXfx, 2.47 times compared with Xeon Ivy Bridge-EP, and 2.26 times compared with Knights Corner. Next, we modify the SpMV function of OpenATLib, an auto-tuned numerical library, to consider the scheduling of optimization as an additional SpMV implementation. We measure the performance of the GMRES solver and obtain performance improvements of up to 11.4%. These results will help to improve the performance of various numerical calculation applications.

DOI： 10.1109/MCSoC.2014.43

Language：Japanese  

Optimization of matrix assembling process in FEM applications on multicore/manycore architectures
Finite-element method (FEM) is one of the most well-known numerical methods for solving partial differential equations (PDE), and applied to various kinds of scientific simulations. Matrix assembling and sparse matrix solver are the most expensive processes in finite-element procedures. In the present work, the matrix assembling process is parallelized using OpenMP, and three types of implementations are evaluated on various types of multicore/manycore architectures. Results and analyses of computations and strategies towards automatic tuning will be described in the presentation.

Language：Japanese  

1ノード200超スレッド時代の自動チューニング手法~FDMコードを例にして~

Language：Japanese  

疎行列ソルバーにおける自動チューニングを用いたOpenMP指示文の最適化

Language：Japanese  

様々な計算機環境におけるOpenMP/OpenACCを用いたICCG法の性能評価

Language：Japanese  

Auto-tuning for A Code from Finite Difference Method with ppOpen-AT on the Xeon Phi

Language：English   Publishing type：Research paper (other academic)  

In order to execute various finite-difference method applications on large-scale parallel computers with a reasonable cost of computer resources, a framework using an adaptive mesh refinement (AMR) technique has been developed. AMR can realize high-resolution simulations while saving computer resources by generating and removing hierarchical grids dynamically. In the AMR framework, a dynamic domain decomposition (DDD) technique, as a dynamic load balancing method, is also implemented to correct the computational load imbalance between each process associated with parallelization. By performing a 3D AMR test simulation, it is confirmed that dynamic load balancing can be achieved and execution time can be reduced by introducing the DDD technique. © The Authors. Published by Elsevier B.V.

DOI： 10.1016/j.procs.2014.05.084

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通信削減アルゴリズムCAQRのRSDFTの直交化処理への適用と評価

Language：Japanese  

レイテンシコアの高度化・高効率化による将来のHPCIシステムに関する調査研究のアプリケーションの異機種環境での評価~メニーコア環境を中心に~

Language：English   Publishing type：Research paper (other academic)  

In this paper, we propose an Auto-tuning (AT) function with an AT language for a dedicated numerical library with respect to supercomputers in operation. The AT function is based on well-known loop transformation techniques, such as loop split, fusion, and re-ordering of statements. However, loop split with copies or increase of computations, and loop fusion to the split loop are taken into account by utilizing user knowledge.

DOI： 10.1109/MCSoC.2014.22

Language：English   Publishing type：Research paper (scientific journal)  

In order to execute various finite-difference method applications on large-scale parallel computers with a reasonable cost of computer resources, a framework using an adaptive mesh refinement (AMR) technique has been developed. AMR can realize high-resolution simulations while saving computer resources by generating and removing hierarchical grids dynamically. In the AMR framework, a dynamic domain decomposition (DDD) technique, as a dynamic load balancing method, is also implemented to correct the computational load imbalance between each process associated with parallelization. By performing a 3D AMR test simulation, it is confirmed that dynamic load balancing can be achieved and execution time can be reduced by introducing the DDD technique.

DOI： 10.1016/j.procs.2014.05.084

Language：Japanese  

Performance Evaluation of Computer Systems Consisted of Various Architectures with Scientific Application

Language：English   Publishing type：Research paper (other academic)  

In this paper, we demonstrate a new approach for power-consumption optimization using a dedicated Auto-tuning (AT) language. Our approach is based on recently developed technologies: (1) a power measurement application programming interface, (2) an AT mathematical core library. Preliminary performance evaluation enables us to select the best kernel for a real-world scientific program using either the CPU or Graphics Processing Unit, with respect to energy consumption. From the results of the evaluation, we found the performance-changing point in the experimental environment. © 2013 IEEE.

DOI： 10.1109/MCSoC.2013.14

Language：English   Publishing type：Research paper (other academic)  

We present a code optimization technique by adapting an auto-tuning (AT) function to an explicit method with the static code generator FIBER. The AT function is evaluated with current multicore processors to match situations with high-thread parallelism (HTP). The results of performance evaluations indicate that the AT function is crucial for HTP, as the speedups of the explicit method with a static code generator are as much as 7.4x compared to that of original implementations based on compiler optimization only. © 2013 IEEE.

DOI： 10.1109/MCSoC.2013.15

Language：Japanese  

メニーコアアーキテクチャ向けのSpMV最適化と自動チューニング

Language：Japanese  

ppOpen‐ATにより自動生成されたppOpen‐HPCコードにおける自動チューニング機能の性能評価

Language：Japanese  

Xeon PhiにおけるSpMVの性能評価

Language：Japanese  

陽解法カーネルのための自動チューニング記述言語ppOpen‐ATの新機能について

Language：English   Publishing type：Research paper (other academic)  

Many iterative solvers and preconditioners have recently been proposed for linear iterative matrix libraries. Currently, library users have to manually select the solvers and preconditioners to solve their target matrix. However, if they select the wrong combination of the two, they have to spend a lot of time on calculations or they cannot obtain the solution. Therefore, an approach for the automatic selection of solvers and preconditioners is needed. We have developed a function that automatically selects an effective solver/preconditioner combination by referencing the history of relative residuals at run-time to predict whether the solver will converge or stagnate. Numerical evaluation with 50 Florida matrices showed that the proposed function can select effective combinations in all matrices. This suggests that our function can play a significant role in sparse iterative matrix computations. (C) 2013 The Authors. Published by Elsevier B.V. and peer review under responsibility of the organizers of the 2013 International Conference on Computational Science

DOI： 10.1016/j.procs.2013.05.300

Language：Japanese  

A New Function of an Auto-tuning Description Language ppOpen-AT for Kernels of Explicit Method

Language：Japanese  

メニーコアプロセッサXeon Phiの性能評価

Language：Japanese  

Language：Japanese  

レイテンシコアの高度化・高効率化による将来のHPCIシステムに関する調査研究のためのアプリケーション最適化と異機種計算機環境での性能評価

Language：Japanese  

レイテンシコアの高度化・高効率化による将来のHPCIシステムに関する調査研究のためのアプリケーションと性能評価

Language：Japanese  

Research activity for Ultra Low Performance HPC

Language：English   Publishing type：Research paper (other academic)  

This paper describes a fast implementation of a FEM application on a GPU. We implemented our own FEM application and succeeded in obtaining a performance improvement in two of our application components: Matrix Assembly and Sparse Matrix Solver. Moreover, we found that accelerating our Boundary Condition Setting component on the GPU and omitting CPU-GPU data transfer between Matrix Assembly and Sparse Matrix Solver slightly further reduces execution time. As a result, the execution time of the entire FEM application was shortened from 44.65 sec on only a CPU (Nehalem architecture, 4 cores, OpenMP) to 17.52 sec on a CPU with a GPU (TeslaC2050).

DOI： 10.1007/978-3-642-38718-0_16

Language：English   Publishing type：Research paper (other academic)  

In this paper, we propose "control formats" to obtain better thread performance of sparse matrix-vector multiplication (SpMV) for unsymmetric and symmetric matrices. By using the control formats, we established the following maximum speedups of SpMV in 16-thread execution on one node of the T2K Open Supercomputer: (1) 7.14x for an unsymmetric matrix by using the proposed Branchless Segmented Scan compared to the original Segmented Scan method
(2) 12.7x for a symmetric matrix by using the proposed Zero-element Computation-free method compared to a simple SpMV implementation. © 2013 Springer-Verlag.

DOI： 10.1007/978-3-642-38718-0_24

Language：Japanese  

本報告では，レイテンシコアの高度化・高効率化による将来の HPCI システムに関する調査研究におけるターゲットアプリケーションの特徴について，演算パターンと通信パターンの観点からの分類法を提案する．東京大学情報基盤センターに設定された富士通 PRIMEHPC FX10 を用いたプロファイル結果を示し，同計算機でのハードウェア性能からの特徴について紹介する．

Language：Japanese  

本報告では，レイテンシコアの高度化・高効率化による将来の HPCI システムに関する調査研究におけるターゲットアプリケーションの特徴について，演算パターンと通信パターンの観点からの分類法を提案する．東京大学情報基盤センターに設定された富士通 PRIMEHPC FX10 を用いたプロファイル結果を示し，同計算機でのハードウェア性能からの特徴について紹介する．

Language：Japanese  

An Improvement in Preconditioned Algorithm of BiCGStab Method

Language：Japanese  

Performance Evaluation of Oakleaf‐FX (Fujitsu PRIMEHPC FX10) Supercomputer System

Language：English   Publishing type：Research paper (other academic)  

We are developing ppOpen-AT, which is an infrastructureof auto-tuning (AT) for ppOpen-HPC. ppOpen-HPC is numerical middleware for post Petascale era. In this study, we propose a new auto-tuning (AT) facility for semi-structured grids in OpenFOAM. We focus on sparse matrix-vector multiplication and the matrix storage formats. Using the features of input data and mesh connectivity, we propose a hybrid storage format that is suitable for semistructured grids. We evaluate the proposed AT facility on the T2K supercomputer and an Intel Xeon cluster. For a typical computational fluid dynamics scenario, we obtain speedup factors of 1.3 on the T2K and 1.84 on the Xeon cluster. These results indicate that the proposed AT method has the potential to select the optimal data format according to features of the input sparse matrix. © 2012 IEEE.

DOI： 10.1109/MCSoC.2012.26

Language：Japanese  

Fault Convergence: A New Concept of Safety for Numerical Computation Software

Language：Japanese  

ポストペタスケール環境のための自動チューニング基盤ppOpen‐ATの新機能について

Language：Japanese  

Xabclib:ソルバ・前処理自動選択機能を備えた疎行列ライブラリ

Language：Japanese  

GPUを用いた疎行列ベクトル積計算の最適化

Language：English   Publishing type：Research paper (other academic)  

We propose a general application programming interface called OpenATLib for auto-tuning (AT). OpenATLib is carefully designed to establish the reusability of AT functions for sparse iterative solvers. Using APIs of OpenATLib, we develop a fully auto-tuned sparse iterative solver called Xabclib. Xabclib has several novel runtime AT functions. We also develop a numerical computation policy that can optimize memory space and computational accuracy. Using the above functions and policies, we obtain the following important findings: (1) an average memory space is reduced to 1/45 under lower memory policies, and (2) fault convergence, which the conventional solvers judges to be converged but actually not converged in the sense of the before-preconditioned matrix, is avoided under higher accuracy policies. The results imply policy-based runtime AT plays significant role in sparse iterative matrix computations.

DOI： 10.1109/ICIAS.2012.6306176

Language：Japanese  

An Improvement in Preconditioned Algorithm of BiCGStab Method
前処理付きBiCGStab（PBiCGStab）法の改善アルゴリズムを提案する．前処理付きBiCG法にCGS法の導出手順を適用すると，CGS法の合理的な前処理付きアルゴリズムが構成される．この手法をPBiCGStab法へと拡張するにあたり，BiCGStab法に現れるMR演算に対し論理面からの新たな考察を行い，適用できることを示した．本提案アルゴリズムが従来のPBiCGStabよりも合理的であることと，数値実験により本提案の有効性を示す．An improved preconditioned BiCGStab algorithm (improved PBiCGStab) is proposed. Rational preconditioned algorithm of CGS has been constructed, by applying the derivation procedure of the CGS to the preconditioned BiCG. In order to extend this approach to the BiCGStab, minimum residual part of the BiCGStab must be considered logically. This proposed algorithm is also more rational than the conventional typical PBiCGStab mathematically. Numerical results show advantages of this improved PBiCGStab.

Language：Japanese  

Fault Convergence: A New Concept of Safety for Numerical Computation Software
本論文では，数値計算ソフトウェアで多く用いられている数値反復解法において生じると考えられる収束障害 （Fault Convergence） の概念を提案する．数値計算分野で用いられている偽収束 （False Convergence） との違いを議論する．Laprie により定義されたディペンダブルコンピューティング実現のための 3 つの脅威―障害 (fault) ‐異常 (error) ‐故障 (failure) モデル－を用いて数値反復解法での収束問題を議論することにより，収束障害の一例を示す．In this paper, we propose a concept of "Fault Convergence" for numerical iteration methods, which are widely used methods in numerical software. With respect to the difference to the concept of "False" convergence on numerical computation field, we explain a situation that fault convergence occurs. By using the model proposed by Laprie with the 3 kinds of threats to dependable computing―the fault-error-failure model―, we discuss an example of fault convergence situation in convergence problem to numerical iterative methods.

Language：Japanese  

Development of Auto-tuning Infrastructure ppOpen-AT for ppOpen-HPC

Language：Japanese  

Study of OpenFOAM tuning in ppOpen-AT

Language：Japanese  

Performance Evaluation of HITACHI SR16000 model M1 Supercomputer System

Language：Japanese  

複数GPU向けのCUDAコードを生成するOpenMP処理系の提案

Language：Japanese  

Performance Evaluation of HITACHI SR16000 model M1 Supercomputer System
本稿では東京大学情報基盤センターにおいて 2011 年 10 月に稼働を開始したスーパーコンピューターシステム HITACHI SR16000 モデル M1（愛称 Yayoi） の性能について報告する．本システムは計算ノードに Power7 プロセッサを搭載した最新のスーパーコンピューターシステムである．いくつかのベンチマークを用いて性能評価を行った結果，性能の特性や重要な実行時環境変数の設定などが明らかとなった．We report the performance of HITACHI SR16000 model M1 supercomputer system (named Yayoi) which has started in October 2011 at Information Technology Center, The University of Tokyo. This is a latest supercomputer system which mounts Power7 CPU on the computation node. We executed several benchmarks on the system and unveiled characteristic features of performance and imporant parameters.

Language：Japanese  

著者らは OpenMP プログラムから CUDA プログラムへ変換する処理系，"OMPCUDA" の開発を行っている．本稿では，OMPCUDA における複数 GPU 向けの CUDA プログラムを生成するための機能の実装を述べ，生成された CUDA コードの評価結果について考察する．

Language：Japanese  

An improvement in preconditioned algorithm of BiCGStab method

Language：Japanese  

Language：Japanese  

Parallel ILU Preconditioner Based on Extended Hierarchical Interface Decomposition for Heterogeneous environments

Language：Japanese  

Evaluation of Auto‐Tuning Function on OpenATLib

Language：Japanese  

Implementation of Matrix Assembly in 3D Finite Element Method for CUDA

Language：Japanese  

Parallel ILU Preconditioner Based on Extended Hierarchical Interface Decomposition for Heterogeneous environments
拡張階層型領域間分割は，領域外からの高次フィルインを考慮可能とする並列化手法であり，分散データの局所性も高いことから，メニーコア環境での効率的な並列化手法として期待される．本研究では，物性値分布に不均質性をもつことから悪条件となる三次元静弾性問題に対し，拡張階層型領域間分割に基づく高次フィルイン前処理付き反復解法を適用する．本報告では，T2K(東大) を利用し，マルチコア環境における本並列実装プログラムの収束性および高次フィルイン付き前処理の並列性能についてマルチカラー法との比較に基づき評価する．Extended version of Hierarchical Interface Decomposition(HID) is developed as an effective parallelization method for Finite Element Method(FEM) on multi/many-core environments for its high locality of distributed mesh data. And thichker separators introduced in Extended HID allow us to take into account high level fill-ins in parallel ILU preconditioners. We implemented Extended HID to OpenMP parallel FEM base simulation of linear elasticity problem with heterogeneous property. The developed code has been tested on the T2K Open Super Computer(T2K/Tokyo) using 1 node, 16 cores to evaluate the robustness and the scalability of parallel ILU decomposition based on the comparison with MC ordering.

Language：Japanese  

Evaluation of Auto-Tuning Function on OpenATLib
科学技術計算等で利用される行列計算ライブラリは高い演算性能が得られるパラメータの選択や入力に多大な手間が必要なため，それを自動的に設定する方式が求められている．そこで，筆者らは自動チューニングインターフェース OpenATlib を開発している．本稿では OpenATLib の提供する機能の 1 つであるリスタート周期自動チューニング機能について述べる．本機能では残差履歴を用いて最適なリスタート周期を自動的に選択する．T2K オープンスパコンを用いて 3 種の解法で本機能の効果を評価した結果，固定値と比較して最大で 38.5 倍の性能差があり，機能の有効性が確認できた．Matrix libraries have many parameters as inputs by the user. They include problem parameters what are difficult to set values and the approach of automatically setting them is needed. Then, we proposed Auto-tuning interface "OpenATLib." In this paper, we explain a runtime automatic tuning approach for deciding the size of projection matrix in Krylov subspace methods. This approach searches the best size of projection matrix with history of residual values at runtime.Performance evaluations of OpenATLib using 3 solvers on T2K Open Supercomputer indicates that the maximum speedup establishes 38.5x.

Language：Japanese  

Implementation of Matrix Assembly in 3D Finite Element Method for CUDA
本稿では三次元有限要素法 (FEM) アプリケーションにおける行列生成処理の CUDA 向け実装について述べる．GPU は高い演算性能・メモリ転送性能を持つため様々な科学技術計算アプリケーションに利用されており，FEM についても多くの研究がなされている．特に，FEM の実行時間の多くは疎行列ソルバーが占めるため，疎行列ソルバーを対象とした GPU 実装の研究が盛んである．本稿では，疎行列ソルバーに次いで実行時間を要する処理である行列生成処理を対象として，1GPU，2GPU および 2GPU と CPU を用いた実装と性能について報告する．We describe the implementation of matrix assembly process in 3D Finite Element Method (FEM) using CUDA. Because GPU has high calculation performance and memory transfer performance, GPU is now utilizing for several scientific applications include FEM. Especially, many researches aim at speeeding up of sparse matrix solver because sparse matrix solver has the largest time ratio of execution time of FEM. In this paper, we focus on matrix assembly process which has the second largest time ratio of FEM, and show the result of implementation and performance evaluation.

Language：Japanese  

前処理付きBiCGStab法の問題点に対する改良

Language：Japanese  

HxABCLibScript : An Extension of an Auto-tuning Language for Heterogeneous Computing Environment
本稿では，CPUおよびGPU(Graphics Processing Unit)を混載した非均質計算機において，任意のプログラムの一部分が，適する計算資源上で実行される最適化を実現する自動チューニング専用言語HxABCLibScriptを提案する．性能評価の結果，HxABCLibScript記述から自動生成されるコードは，問題サイズや反復回数に応じ，CPUとGPU間で適切に計算資源を切り替えることで最適化されることを確認した．In this paper, we propose HxABCLibScript, which is a dedicated language for auto-tuning description on heterogeneous computer environment, which includes CPU and GPU (Graphics Processing Unit), to adapt arbitrary parts of programs. Results of performance evaluation indicated that the automatically generated codes from the description of HxABCLibScript can select the best computer resources between CPU and GPU according to problem size or the number of iterations on the program.

Language：Japanese  

Implementation and Evaluation of 3D Finite Element Method for CUDA

Language：Japanese  

Implementation and Evaluation of 3D Finite Element Method for CUDA
本稿では三次元弾性静力学を対象とした有限要素法(Finite Element Method, FEM)のGPU(CUDA)向け実装と性能評価について述べる．高い演算性能・メモリ転送性能を持つGPUは様々な科学技術計算アプリケーションに利用されており，FEMについても多くの研究がなされている．本稿では特に前処理付き共役勾配法(Conjugate Gradient Method, CG法)による疎行列ソルバーと係数行列生成部分に注目し，CUDA向けの実装と性能評価を行った結果を報告する．In this paper, we describe the implementation and evaluation of Finite Element Method(FEM) on GPU(CUDA). Because GPU has high calculation performance and memory transfer performance, GPU is now utilizing for several scientific applications include FEM. We show the result of implementation and performance evaluation especially about sparse matrix solver using Conjugate Gradient Method and matrix creation.

Language：Japanese  

Optimized Implementation of Segmented Scan Method for CUDA

Language：Japanese  

ATのGPUへの展開

Language：Japanese  

Research on Intermediate Language for GPU Computing
In this presentation, we will discuss a intermediate language suitable for GPU computing. GPUs as data parallel processors have very high execution peak performance for general purpose computation. GPUs attract attention as accelerators in HPC (High Performance Computing). Accelerators usually have parallel execution models like SIMD and SPDM, independent memory, and high-speed on-chip scratchpad memory. Intermediate languages used in CPU compilers cannot fully describe these features. Users are using different programming environments for each accelerators and tuning source codes toward the peak performance. We evaluate the execution performance of a native compiling environment based on Java Bytecode and discuess the intermediate language which is suitable to describe the accelerator features.

Language：Japanese  

Optimized Implementation of Segmented Scan Method for CUDA
本稿では Segmented Scan 法を用いた疎行列ベクトル積の CUDA 向け最適化実装について述べる．我々は実装の再利用性に着目した自動チューニングインターフェース OpenATLib の提案を行い，また OpenATLib の提供する機能の一つである疎行列ベクトル積においては Segmented Scan 方式を元にスカラ計算機向けに改良を行った Branchless Segmented Scan 方式を提案している．本稿ではこれらの方式を元にして CUDA 向けの新たな Segmented Scan 方式を考案し実装した．GPU 上で高速実行可能なようにアルゴリズムの改良や各種の最適化を行った結果，偏りの大きな行列に対して NVIDIA GeForceGTX285 上で最大で 3.26GFLOPS の性能を達成した．We discuss about optimized implementation of sparse matrix vector multiplication for CUDA using Segmented Scan method. We proposed Auto-tuning interface OpenATLib and we also proposed Branchless Segmented Scan method besed on Segmented Scan method for scalar computer as an important new feature of sparse matrix vector multiplication. In this paper, we proposed and implemented new Segmented Scan method for CUDA based on Segmented Scan method and Branchless Segmented Scan method. As a result of optimized implementation, we aimed 3.26GFLOPS on NVIDIA GeForceGTX285.

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A Software Cache Implementation for GPU

Language：Japanese  

A Software Cache Implementation for GPU
高性能コンピューティングにおいて GPU が注目されている．NVIDIA 製 GPU は CUDA において高性能なシェアードメモリを有効に用いるプログラミング技術により各種アプリケーションで非常に高いピーク性能が得られている一方，プログラミングの容易さ，汎用性に問題を残している．本研究においては CUDA においてユーザが明示的に使用するシェアードメモリの一部をデバイスメモリのキャッシュとするソフトウェアキャッシュ機構を提案する．本機構によりデバイスメモリからシェアードメモリへ暗黙的にデータ転送が行われ汎用計算の高速化が達成される．In HPC, GPU attracts attention. Although programming difficulty still remains, very high peak performance can be achieved using NVIDIA GPUs. In this research, we propose a software cache mechanism which caches the device memory of CUDA with the shared memory. User data can be transfered implicitly with the software cache and performance improvement of general-purpose computation benchmark programs can be achieved.

Language：Japanese  

A Software Cache Implementation for GPU
高性能コンピューティングにおいて GPU が注目されている．NVIDIA 製 GPU は CUDA において高性能なシェアードメモリを有効に用いるプログラミング技術により各種アプリケーションで非常に高いピーク性能が得られている一方，プログラミングの容易さ，汎用性に問題を残している．本研究においては CUDA においてユーザが明示的に使用するシェアードメモリの一部をデバイスメモリのキャッシュとするソフトウェアキャッシュ機構を提案する．本機構によりデバイスメモリからシェアードメモリへ暗黙的にデータ転送が行われ汎用計算の高速化が達成される．In HPC, GPU attracts attention. Although programming difficulty still remains, very high peak performance can be achieved using NVIDIA GPUs. In this research, we propose a software cache mechanism which caches the device memory of CUDA with the shared memory. User data can be transfered implicitly with the software cache and performance improvement of general-purpose computation benchmark programs can be achieved.

Language：Japanese  

OMPCUDA:GPU向けOpenMP処理系

Language：Japanese  

OMPCUDA:GPU向けOpenMPの実装

Language：Japanese  

OMPCUDA : Implementation of OpenMP for GPU
General-purpose computation using GPU (GPGPU) has been a focus of attention because of its performance, but the difficulity of GPGPU programming is a problem. So we have proposed GPGPU programming style using existing parallel programming style. In this paper, we implemented OMPCUDA OpenMP for CUDA-capable GPU, for explore a possibilities of GPGPU using OpenMP. Then, we evaluated out implimentation using test program. As a result, we confirmed that OMPCUDA make GPGPU parallel programming easy and can get speed-up.

Language：Japanese  

Message Passing GPGPU Programming
As GPU's performance increases, general-purpose computation using GPU (GPGPU) is watched with keen interest more and more. GPGPU is expected to overtake CPU's performance by its parallel processing tendency, but, programming for GPGPU is not easy because of its special programming style. In this paper, we propose GPGPU programming style using existing parallel programming style. We take up several existing parallel programming styles such as message passing, and examined how they can be applied to GPGPU programming.

Language：Japanese  

Message Passing GPGPU Programming
As GPU's performance increases, general-purpose computation using GPU (GPGPU) is watched with keen interest more and more. GPGPU is expected to overtake CPU's performance by its parallel processing tendency, but, programming for GPGPU is not easy because of its special programming style. In this paper, we propose GPGPU programming style using existing parallel programming style. We take up several existing parallel programming styles such as message passing, and examined how they can be applied to GPGPU programming.

Language：Japanese  

GPGPU Programming Using Existing Parallelizing Method

Language：Japanese  

Proposal of GPGPU Programming Using Existing Parallelizing Method
GPGPU utilizing GPU's performance for general-purpose computation is attracting much attention. GPGPU is expected to effect higher performance than CPU. However, creating GPGPU programming is not easy because programming methods peculiar to GPGPU programming are needed. In this paper, we propose to use existing parallellizing method as one of a new method making GPGPU programming easier. Also we consider writing programs running on GPUs with OpenMP and MPI based on the new GPGPU programming language of CUDA.

Language：Japanese  

A Performance Comparison of Software-DSM Mocha and MPI Using Parallel Benchmarks
Software distributed shared memory (S-DSM) system is more friendly and easier to do programming compared with message pcissing interface. In this paper, we compared the performance of Mocha which is one of S-DSM systems, and MPICH which is a widely-used parallel programming library with message passing interface. Four applications (MM, SOR, IS, LU) were used for the parallel benchmarks. To measure S-DSM system overhead, the exe- cution time of interrupt handlers was measured. The result shows that the followings should be performed to archive high performance in the S-DSM system compared with MPI: 1. Introdaction of a pre-fetching for shared data before a page fault; 2. Improvement of acquiring lock performance; 3. Improvement of barrier synchronization performance.

Language：Japanese  

A Performance Comparison of Software-DSM Mocha and MPI Using Parallel Benchmarks
Software distributed shared memory (S-DSM) system is more friendly and easier to do programming compared with message pcissing interface. In this paper, we compared the performance of Mocha which is one of S-DSM systems, and MPICH which is a widely-used parallel programming library with message passing interface. Four applications (MM, SOR, IS, LU) were used for the parallel benchmarks. To measure S-DSM system overhead, the exe- cution time of interrupt handlers was measured. The result shows that the followings should be performed to archive high performance in the S-DSM system compared with MPI: 1. Introdaction of a pre-fetching for shared data before a page fault; 2. Improvement of acquiring lock performance; 3. Improvement of barrier synchronization performance.

Language：Japanese  

CPUとGPUを用いた基本行列計算ライブラリ

Language：English   Publishing type：Research paper (other academic)  

GPUs for numerical computations are becoming an attractive alternative in research. In this paper, we propose a new parallel processing environment for matrix multiplications by using both CPUs and GPUs. The execution time of matrix multiplications can be decreased to 40.1% by our method, compared with using the fastest of either CPU only case or GPU only case. Our method performs well when matrix sizes are large.

Language：Japanese  

Proposal and Implementation of Parallel GEMM Routine Using CPU and GPU
GPUs for numerical computations are becoming an attractive research topics. We have proposed a new computation method of GPU, which utilizes parallel processing based on CPU and GPU. In this paper, we apply this method to existing numerical computation library. We examine a performance tuning method and execute performance experiments using a benchmark program. We also apply the method to the GEMM routine of BLAS and execute the HPL benchmark. As a result, the performance can be improved to 1.45 times by our method, compared with a CPU only environment using Pentium4 3.0GHz. There is a precision problem depending on GPU's arithmatic precision, but we show such a potentiality that our method can be applied to various applications.

Language：Japanese  

A Performance Comparison of Parallel Applications between Software-DSM and MPI
Software distributed shared memory (S-DSM) system achieves a virtual shared memory on distributed memory environment such as PC cluster without special hardware supports. S-DSM system is more friendly and easier to do programming compared with message passing interface. In this paper, we compare the performance of Mocha which is one of S-DSM systems, and MPICH which is a popular parallel programming library with message passing interface. Three applications (MM, SOR, LU) are used for our benchmarks. The results show the application in MPI that can be tuned for communication is better performance than one on S-DSM, but the one in MPI that can not be tuned is equal performance to one on S-DSM.

Language：Japanese  

Ainori Communication : A Method to Reduce the Page Transfer of S-DSM Systems
We discuss the method to speed up the software distributed shared memory (S-DSM) systems. By predicting a page which will be needed to be transferred in the future and prefetching it, we can speed up the S-DSM systems. In this paper, we propose a method to transfer the predicted pages together with a message used in S-DSM systems. We will call this method Ainori communication. We evaluate our implementation using four S-DSM benchmarks and show that it can decrease the number of communication and improve the performance.

Language：Japanese  

A Performance Comparison of Parallel Applications between Software‐DSM and MPI

Language：Japanese  

Ainori Communication: A Method to Reduce the Page Transfer of S‐DSM Systems
We discuss the method to speed up the software distributed shared memory (S-DSM) systems. By predicting a page which will be needed to be transferred in the future and prefetching it, we can speed up the S-DSM systems. In this paper, we propose a method to transfer the predicted pages together with a message used in S-DSM systems. We will call this method Ainori communication. We evaluate our implementation using four S-DSM benchmarks and show that it can decrease the number of communication and improve the performance.

Language：Japanese  

Proposal and Implementation of Parallel GEMM Routine Using CPU and GPU

Language：Japanese  

CPUとGPUを複数用いた並列数値計算環境の検討

Language：Japanese  

Proposal of Matrix Multiply and Add Method by Parallel Processing Using CPU and GPU
A research that uses GPU for numerical calculation is becoming active. In this paper, we do not only solve numerical problem using GPU but also propose a method that divide a problem and calculate it using CPU and GPU. Measure a execution time of matrix multiply and add, and because of parallel processing the performance was improved of 38.1% than the case solved only with CPU. Moreover, we exmine a method for a best problem distribution using each FLOPS of CPU and GPU obtained by a preliminary experiment. As a result, we could obtain values by prediction nearby experimental values.

Language：Japanese  

GPUによるBLAS演算の性能評価

Language：Japanese  

GPUによる高速な行列積の実装

Language：Japanese  

命令レベル並列性を利用したOpenMPによるプロセッサシミュレータの並列実行

Event date： 2022.12

Language：English   Presentation type：Oral presentation (general)  

Country：Japan  

Event date： 2022.7

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Event date： 2022.7

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Event date： 2022.5

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Event date： 2021.3

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Event date： 2021.3

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Event date： 2021.3

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Event date： 2021.3

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Event date： 2021.3

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Event date： 2021.3

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Event date： 2021.3

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Event date： 2021.3

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Event date： 2020.12

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Event date： 2020.12

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Event date： 2020.12

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Event date： 2020.12

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Event date： 2020.12

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Event date： 2020.12

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Event date： 2020.12

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Event date： 2020.12

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Event date： 2020.12

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Event date： 2020.12

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Event date： 2020.8

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Event date： 2020.8

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Event date： 2019.5

Language：English   Presentation type：Oral presentation (general)  

Venue：Hilton Copacabana, Rio de Janeiro, Brazil   Country：Brazil  

Event date： 2019.2

Language：English   Presentation type：Oral presentation (general)  

Venue：National Sun Yat-sen University, Kaohsiung, Taiwan   Country：Taiwan, Province of China  

Event date： 2018.6

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：ウインクあいち   Country：Japan  

Event date： 2018.5

Language：English  

Venue：Vancouver   Country：Canada  

HACApK is a software package for solving dense linear systems of equations and is used in other software packages, like ppohBEM for solving boundary integral equations. To enable the solution of large-scale boundary value problems, HACApK hierarchically compresses the coefficient matrix and uses the BiConjugate Gradient Stabilized (BiCGStab) method for solving the linear system. To extend HACApK's capability, this paper outlines how we ported the HACApK linear solver onto GPU clusters. Though the potential of GPUS has been widely accepted in high-performance computing, it is still a challenge to utilize the GPUS for a solver, like HACApK, that requires fine-grained irregular computation and global communication. To utilize the GPUS, we integrated the variable-size batched GPU kernel that was recently released in the MAGMA software package. This is the first time the variable-size batched kernels were used in a solver or application code. We discuss several techniques to improve the performance of the batched kernel and demonstrate the effects of these techniques on two state-of-The-Art GPU clusters. For instance, with two 14-core Intel Xeon CPUs and four NVIDIA P100 GPUS per node, the GPU kernel obtained a solver speedup of 8× on one node and 4× on eight nodes. We also show that when the inter-GPU communication becomes significant, the solution time can be further reduced by a factor of 2× by carefully designing the communication layer with the underlying node architecture in mind.

Event date： 2018.3

Language：English   Presentation type：Oral presentation (general)  

Venue：Resorts World Convention Centre Sentosa   Country：Singapore  

Event date： 2017.12

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：くまもと県民交流館パレア   Country：Japan  

Event date： 2017.12

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：くまもと県民交流館パレア   Country：Japan  

Event date： 2017.10

Language：Japanese   Presentation type：Symposium, workshop panel (public)  

Venue：鳥羽シーサイドホテル   Country：Japan  

Event date： 2017.8

Language：English   Presentation type：Oral presentation (general)  

Venue：Nagoya University   Country：Japan  

Event date： 2017.7

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：秋田アトリオンビル   Country：Japan  

Event date： 2017.6

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：神戸大学先端融合研究環統合研究拠点 コンベンションホール   Country：Japan  

Event date： 2017.5 - 2017.6

Language：English   Presentation type：Symposium, workshop panel (public)  

Venue：Buena Vista Palace Hotel   Country：United States  

Event date： 2016.4

Language：English  

Country：Other  

Auto-Tuning of Hierarchical Computations with ppOpen-AT

Language：Others  

Country：Other  

Language：Others  

Country：Other  

Language：Japanese  

Country：Japan  

SIAM AN10(Conference Reports)

Language：Japanese  

Country：Japan  

IT Talents Who Sprang Out of the Mitoh-Youth : Field for Exploration, Growing, and Connection

Language：Japanese  

Country：Other  

行列-行列積に代表される基本線形計算を集約したライブラリBLAS (Basic Linear Algebra Subprograms) は、多くの数値計算で必須の処理である。しかし、従来の数値計算ライブラリは、演算速度の向上は考慮しているが演算精度の向上に関する考慮が不十分である。一方、尾崎が提案した高精度行列-行列演算アルゴリズム(以降、尾崎の方法)は、利用している浮動小数点演算型の精度限界まで高精度演算ができる。本研究では尾崎の方法の実装に対して、複数の小さな行列-行列積を高速に行うことができるBatched BLASを適用した実装方式を提案する。性能評価では、Batched BLASの有効性を検証し、CPU環境だけでなくGPU環境についても提案する実装方式の有効性を検証する。

Language：Others  

Country：Japan  

3. Progress in Simulation Study of Fundamental Physics and Visualization Technology: 3.2: Visualization Technology

Language：Japanese  

Country：Japan  

Language：Japanese  

Country：Japan  

我々は複数のパラメータを同時に推定する手法として，パラメータ空間における反復一次元探索を提案している．この手法はパラメータの組み合わせを自動的に選択し，その実行性能を実測，さらに別の組み合わせの選択を繰り返すことで探索を行う．この提案手法を機械学習プログラムに適用する．機械学習には複数のハイパーパラメータが存在し，適切なハイパーパラメータの組み合わせを推定するには時間がかかる．本研究は歩行者経路予測アプリケーションに用いる機械学習のハイパーパラメータについて適切な組み合わせを推定し，マルチGPU環境を利用して実測処理を並列化することで，約15日かかる推定が約12時間で完了することを示す．

Language：Japanese  

Country：Japan  

我々は反復一次元探索を用いた自動チューニングの研究に取り組んでおり，マルチGPU環境を用いた機械学習のプログラムのハイパーパラメータの最適化を進めている．機械学習は同一のハイパーパラメータを用いても毎回教師データが変わるなど同一の結果にならないため，自動チューニングの結果にブレが生じる．このブレに対して，これまで，我々は推定したパラメータに対して追加測定を行い自動チューニングの安定性を高める手法を提案してきた．本研究では，歩行者経路予測アプリケーションに用いる機械学習プログラムに適用しマルチGPU環境で推定したハイパーパラメータの値を並列化し複数回まとめて追加測定することによる，自動チューニングの精度向上について示す．

Type：Competition, symposium, etc. 

Type：Competition, symposium, etc. 

Type：Competition, symposium, etc. 

Type：Competition, symposium, etc. 

Type：Competition, symposium, etc. 

Type：Competition, symposium, etc. 

Type：Competition, symposium, etc. 

Type：Competition, symposium, etc. 

Type：Competition, symposium, etc. 

Type：Peer review 

Number of peer-reviewed articles in foreign language journals：0

Number of peer-reviewed articles in Japanese journals：1

Proceedings of International Conference Number of peer-reviewed papers：11

Proceedings of domestic conference Number of peer-reviewed papers：3