Kyushu University Academic Staff Educational and Research Activities Database
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Takatsugu Ono Last modified date:2019.06.27





E-Mail
Homepage
https://sites.google.com/site/takatsuguono/
Academic Degree
Ph.D.
Field of Specialization
System architecture
Research
Research Interests
  • Controlling PCM life time for a data center
    keyword : data center, memory, phase change memory, memory controller
    2016.01~2018.03.
  • Memory architecture for in-memory computing
    keyword : Computer architecture, System architecture, Memory architecture, DRAM
    2015.04~2017.03.
Academic Activities
Papers
1. Koki Ishida, Masamitsu Tanaka, Takatsugu Ono, Koji Inoue, Towards Ultra High-Speed Cryogenic Single-Flux-Quantum Computing, IEICE Transactions on Electronics, Vol.E101-C, No.5, 359-369, 2018.05.
2. Mihiro Sonoyama, Takatsugu Ono, Osamu Muta, Haruichi Kanaya, Koji Inoue, Wireless Spoofing-Attack PreventionUsing Radio-Propagation Characteristics, IEEE International Conference on Dependable, Autonomic and Secure Computing, 502-510, 2017.11.
3. Teruo Tanimoto, 小野 貴継, 井上 弘士, Hiroshi Sasaki, Enhanced Dependence Graph Model for Critical Path Analysis on Modern Out-of-Order Processors, IEEE Computer Architecture Letters, PP, 99, 1-1, 2017.03.
4. Takatsugu Ono, Yotaro Konishi, Teruo Tanimoto, Noboru Iwamatsu, Takashi Miyoshi, Jun Tanaka, A Flexible Direct Attached Storage for a Data Intensive Application, IEICE Transactions on Information and Systems, E98-D, 12, 2168-2177, 2015.12.
5. Takatsugu Ono, Inoue Koji, Kazuaki Murakami, Kenji Yoshida, Reducing On-Chip DRAM Energy via Data Transfer Size Optimization, IEICE Transactions on Electronics, E92-C, 4, 433-443, 2009.04.
Presentations
1. Takatsugu Ono, Yotaro Konishi, Teruo Tanimoto, Noboru Iwamatsu, Takashi Miyoshi, Jun Tanaka, FlexDAS: A Flexible Direct Attached Storage for I/O Intensive Applications, IEEE International Conference on Big Data, 2014.10.
2. Takatsugu Ono, Inoue Koji, Kazuaki Murakami, Adaptive cache-line size management on 3D integrated microprocessors, 2009 International SoC Design Conference, ISOCC 2009, 2009.12, The memory bandwidth can dramatically be improved by means of stacking the main memory (DRAM) on processor cores and connecting them by wide on-chip buses composed of through silicon vias (TSVs). The 3D stacking makes it possible to reduce the cache miss penalty because large amount of data can be transferred from the main memory to the cache at a time. If a large cache line size is employed, we can expect the effect of prefetching. However, it might worsen the system performance if programs do not have enough spatial localities of memory references. To solve this problem, we introduce software-controllable variable line-size cache scheme. In this paper, we apply it to an L1 data cache with 3D stacked DRAM organization. In our evaluation, it is observed that our approach reduces the L1 data cache and stacked DRAM energy consumption up to 75%, compared to a conventional cache..
Membership in Academic Society
  • Information Processing Society of Japan
  • The Institute of Electronics, Information and Communication Engineers