九州大学-研究者情報 [西澤伸一 (教授) 応用力学研究所新エネルギー力学部門]

西澤伸一（にしざわしんいち）

データ更新日：2023.12.07

教授　／　応用力学研究所新エネルギー力学部門新エネルギーシステム工学分野

原著論文

1.	西澤伸一, 山口博隆, 加藤智久, 小柳直樹, 木藤泰男, 荒井和雄, 昇華法によるSiC単結晶成長とその場観察(バルク成長分科会特集 : 結晶成長の科学と技術), 日本結晶成長学会誌, 10.19009/jjacg.29.5_431, 29, 5, 431-438, 2002.05, Silicon carbide (SiC) is the most promising material for high power, high frequency and low loss device applications. In order to realize SiC devices, it is necessary to improve the grown crystal quality. SiC bulk single crystal is grown by sublimation method, inside a closed carbon crucible. Because of the black box process, the optimization of sublimation process is difficult. From this point view the in situ X ray topography system was developed to observe the phenomena inside a crucible during the growth. The numerical simulation was also applied. From these observations, the heat and mass transfer in a crucible was discussed involving in the macroscopic crystal quality, such as crystal diameter, growing surface shape, and also in the microscopic crystal quality such as defect generations..
2.	Ryota Suewaka, Toshiaki Saishoji, Shin Ichi Nishizawa, Numerical and experimental investigation of effect of oxygen concentration on grown-in defects in a Czochralski silicon single crystal, Japanese Journal of Applied Physics, 10.35848/1347-4065/acde27, 62, 7, 2023.07, Grown-in defect-free wafers are required in silicon semiconductor devices. A point defect concentration simulation was performed along with an experimental investigation, demonstrating a wide range of oxygen concentrations from 1.6 × 1017 to 9.1 × 1017 cm−3 in crystals. Thus, the effect of oxygen atoms in a Czochralski silicon single crystal with grown-in defect behavior was revealed. Consequently, the increasing vacancy concentration trapped by the oxygen atom (oxygen coefficient) was estimated as 4.61 × 10−5 per oxygen atom. Previously, for obtaining the oxygen coefficient, a regression equation assuming thermal equilibrium concentrations of vacancy (V) and interstitial Si (I) was applied to the experimental results. However, the interface shape, thermal stress, and hot-zone structure of the experimental level needed to be arranged; this affected the grown-in defect behavior. In this study, the oxygen coefficient and thermal equilibrium concentration of V and I were determined uniquely without arranging the situations experimental level..
3.	Kaoru Kajiwara, Kazutaka Eriguchi, Kazuhiro Fusegawa, Noritomo Mitsugi, Shuichi Samata, Kazuhisa Torigoe, Kazuhiro Harada, Masataka Hourai, Shin Ichi Nishizawa, Evaluation of thermally activated defects behaviors in nitrogen-doped Czochralski silicon single crystals using deep level transient spectroscopy, Japanese Journal of Applied Physics, 10.35848/1347-4065/ace011, 62, 7, 2023.07, Thermally activated defect behaviors in nitrogen (N)-doped Czochralski silicon (Cz-Si) single crystals were investigated using deep level transient spectroscopy and quasi-steady-state photoconductance to confirm the crystals’ applicability in insulated gate bipolar transistors (IGBTs). The thermally activated defects, which were probably N-vacancy complexes and degraded the minority carrier lifetime, were detected with extremely low densities in N-doped Cz-Si compared with N-rich floating zone Si single crystals after heat treatments at 500 °C, resulting in a high remaining value of minority carrier lifetime. The difference was assumed to come from whether vacancies were released in the Si matrix during heat treatment. For the Cz-Si, vacancies were assumed to be strongly bound with oxygen atoms with concentrations of 1017 atoms cm−3. Therefore, vacancies were not released during heat treatment, resulting in low remaining N-vacancy complex densities. N-doped Cz-Si are potential materials for IGBTs because of their low densities from thermally activated defects..
4.	Thatree Mamee, Zaiqi Lou, Katsuhiro Hata, Makoto Takamiya, Shin ichi Nishizawa, Wataru Saito, Enhancement of turn-off gate voltage waveform change by digital gate control for bond wire lift-off detection in IGBT module, Microelectronics Reliability, 10.1016/j.microrel.2023.115067, 147, 2023.08, The bond wire lift-off is the one of main failures for insulated gate bipolar transistors (IGBT) power modules. The wire lift-off increases parasitic inductance LeE in the module and the gate voltage Vge waveform is modulated by LeE·dIe/dt. Therefore, the Vge waveform has the potential for an indicator of condition monitoring. The Digital gate control (DGC) can control switching behavior precisely for low-loss and low-noise switching. It is also effective for sensitivity enhancement of Vge waveform changed by the wire lift-off. This paper reports how the DGC 2-step vector control (2-sVC) can improve the wire lift-off failure detection sensitivity by Vge waveform. The experiment results showed that the Vge spike was generated by LeE·dIe/dt at the turn-off switching and the spike generation timing depended on the wire number. The DGC obtained the larger timing-shift Δtwire and the amplitude ΔVge-surge than those at the conventional gate control. In addition, the best vector condition improved the trade-off between turn-off loss and collector voltage overshoot compared with the conventional gate control. From these results, the DGC is effective to enhance the sensitivity of bond wire lift-off detection by Vge waveform maintaining the best switching performance..
5.	Taro Takamori, Keiji Wada, Norman Boettcher, Tobias Erlbacher, Wataru Saito, Shin-ichi Nishizawa, Adjustable Current Limiting Function With a Monolithically Integrated SiC Circuit Breaker Device, IEEE Transactions on Industry Applications, 10.1109/TIA.2023.3288856, 2023.09, This paper proposes a current limiting function for a self-sensing and self-triggering monolithically integrated SiC circuit breaker device. The proposed function provides the device not only with a fast-response current breaking operation but also with the current limiting operation, including supplying a constant current to the load and preventing the detection of inrush currents. This function is suitable for replacing mechanical conductors in initial charging circuits within rectifiers and safety equipment in case of overcurrent phenomena. The proposed method achieves certain constant currents through a simple variation of the gate-drive circuit with the adjustable parameters of an additional MOSFET. The mechanism of the current limiting function is verified using TCAD simulations based on certain conditions. Consequently, experimental results verified that the circuit breaker device with the current limiting function reduces the inrush current by up to 76.9% using a 500 VDC distribution circuit system..
6.	Tatsuta Tsukamoto, Shin ichi Nishizawa, Wataru Saito, A simple sensor device for power cycle degradation sensing, Microelectronics Reliability, 10.1016/j.microrel.2023.115068, 147, 2023.08, A new sensor device is proposed for detection of power cycle degradation. Proposed sensor device is consisting of a Schottky-barrier MOSFET and the sensing principle is based on change of I-V characteristics by mechanical stress. Samples were fabricated by metal lift-off process and SiO2 gate insulator film deposition and the fundamental operation was evaluated by four-point bending test for mechanical stress applying. The fabricated device showed monotonically drain current change with number of stress cycles and about 5 times current change compared with initial current after 10,000 cycles of 4 N stress. Large current change by cyclic mechanical stress is attractive for a simple detection of power cycle degradation without expensive analog-circuits..
7.	西澤伸一, 11.4 宇宙実験(11.宇宙工学), 日本機械学会誌, 10.1299/jsmemag.100.945_868_2, 100, 945, 868-868, 1997.08.
8.	西澤伸一, 11.4宇宙実験(11.宇宙工学), 日本機械学会誌, 10.1299/jsmemag.101.957_595_2, 101, 957, 595-595, 1998.08.
9.	Shinichi Nishizawa, H. Yamaguchi, T. Kato, N. Oyanagi, S. Yoshida, K. Arai, Development of X-ray topography system for in-situ observation of sublimation SiC single crystal growth, Denshi Gijutsu Sogo Kenkyusho Iho/Bulletin of the Electrotechnical Laboratory, 63, 8-9, 37-42, 1999.06, X-ray topography system for in-situ observation of sublimation SiC single crystal growth has been developed. The feature of SiC single crystal growth inside a closed carbon crucible over 2200°C is captured in real time. The system will clarify the SiC growth mechanism, such as growth rate, defect generation and stress distribution in a growing crystal, depending on temperature, pressure and other parameters. These results will be useful to develop a high quality and large SiC single crystal wafer, and enhance the hard electronics technology..
10.	西澤伸一, 11.4宇宙実験(11.宇宙工学), 日本機械学会誌, 10.1299/jsmemag.102.969_492_2, 102, 969, 492-492, 1999.08.
11.	西澤伸一, IWMCG-5 (5^	International Workshop on Modeling in Crystal Growth)に参加して(閑話休題), 日本結晶成長学会誌, 10.19009/jjacg.33.5_403, 33, 5, 403-404, 2006.05.
12.	C. Ota, J. Nishio, T. Hatakeyama, T. Shinohe, K. Kojima, S. Nishizawa, H. Ohashi, Fabrication of 4H-SiC floating junction Schottky barrier diodes (Super-SBDs) and their electrical properties, SILICON CARBIDE AND RELATED MATERIALS 2005, PTS 1 AND 2, 527-529, PART 2, 1175-1178, 2006.10, 4H-SiC floating junction Schottky barrier diodes (Super-SBDs) were fabricated. It was found that their properties are closest to the theoretical limitation, defined by the relationship between specific on-state resistance and breakdown voltage of 4H SiC-unipolar devices. They have a p-type floating layer designed as line-and-spacing. The specific on-state resistances of Super-SBDs with a few micrometers of spacing width were found to be nearly equal to those of conventional SBDs without p-type floating layer. The breakdown voltages of Super-SBDs were higher than those of conventional SBDs. Accordingly the properties of Super-SBDs have improved the trade-off between specific on-state resistance and breakdown voltage, and the highest value to date for Baliga's Figure of Merit (BFOM) has been obtained..
13.	Akimasa Kinoshita, Junji Senzaki, Makoto Katou, Shinsuke Harada, Mitsuo Okamato, Shin-ichi Nishizawa, Kenji Fukuda, Fukuyoshi Morigasa, Tomoyoshi Endou, Takuo Isii, Teruyuki Yashima, Activation treatment of ion implanted dopants using hybrid super RTA equipment, Silicon Carbide and Related Materials 2005, Pts 1 and 2, 10.4028/www.scientific.net/MSF.527-529.803, 527-529, 803-806, 2006.10, We perform rapid thermal annealing (RTA) on areas as large as 2-inch phi (diameter) at high temperature using the hybrid super RTA (HS-RTA) equipment. The HS-RTA equipment consists of an infrared annealing unit and a RF induction annealing unit in order to uniformly anneal over 2-inch phi susceptor. As a result of annealing by the HS-RTA equipment, the temperature is elevated from RT to peak temperature (similar to 1800 degrees C) for less than 1 min, remain stable at annealing temperature for 30s and falls from peak temperature to 1000 degrees C within less than 20s. The temperature distributions on a 2-inch phi susceptor are +/- 10 degrees C, +/- 33 degrees C and +/- 55 degrees C at 1565 degrees C, 1671 degrees C and 1752 degrees C, respectively. Phosphorus (P) ion implanted silicon carbide (SiC) samples are used to evaluate the performance of the HS-RTA equipment. The five implanted samples placed on the 2-inch phi susceptor are annealed for 30s at 1565 degrees C, 1671 degrees C and 1752 degrees C. The mean sheet resistances of the 5 samples annealed at 1565 degrees C, 1671 degrees C and 1752 degrees C are 92.6 Omega/square, 82.6 Omega/square and 75.5 Omega/square, respectively. The sheet resistance uniformities are 9.9%, 7.9% and 9.3%. The average roughness (R-a) is calculated from 10 mu m square Atomic Force Microscopy (AFM) image. R-a values of the samples annealed at 1565 degrees C, 1671 degrees C and 1752 degrees C are 2.399 nm, 2.408 nm and 3.282 nm, respectively..
14.	C. Ota, J. Nishio, K. Takao, T. Hatakeyama, T. Shinohe, K. Kojima, S. Nishizawa, H. Ohashi, Doping Concentration Optimization for Ultra-low-loss 4H-SiC Floating Junction Schottky Barrier Diode (Super-SBD), SILICON CARBIDE AND RELATED MATERIALS 2008, 10.4028/www.scientific.net/MSF.615-617.655, 615-617, 655-658, 2009.11, Previous Simulation works and experiments oil the loss of 4H-SiC floating junction Schottky barrier diodes (Super-SBDs) show that the loss is related to the doping concentration in the drift region and the pattern of the floating layer. The effect of the doping concentration for lowering the loss is characterized the breakdown voltage (V-bd) and the on-state resistances (RonS) of the Super-SBDs based oil Baliga's figure of Merit (BFOM). Experimental devices with two doping concentrations in the drift region are fabricated to investigate the static characteristics: V-bd and RonS. The V-bd of the Super-SBDs is close to the simulation result, near 3000 V. However the tendency of the V-bd by the doping concentration is not similar to the Simulation result. And the RonS are about 3.22 m Omega cm(2) which is higher than that of Simulation result. The doping concentration optimized in this study does not show significant lowering loss and the design of the floating layer in the termination region affect the low-loss static characteristics of the Super-SBD. In addition, adopting PiN Structure with floating layer (Super-PiN) affects the low-loss dynamic characteristics, optimizing the doping concentration in the drift region. We conclude that the fabricated Super-SBDs with the floating layer in the termination region, the drift region with a doping concentration of 1.0x10(16) cm(-3) and mesa-shaped termination structure, have excellent V-bd of 2990 V which is almost same as that of simulation result and RonS of 3.22 m Omega cm(2)..
15.	Kazuto Takao, Keiji Wada, Kyungmin Sung, Yuji Mastuoka, Yasunori Tanaka, Shinichi Nishizawa, Chiharu Ota, Takeo Kanai, Takashi Shinohe, Hiromichi Ohashi, 4.5kV-400A Modules using SiC-PiN diodes and Si-IEGTs Hybrid Pair for High Power Medium-Voltage Power Converters, 2012 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION (ECCE), 1509-1514, 2012.10, A new 4.5 kV-400 A module using SiC-PiN diodes and Si-IEGTs hybrid pair has been developed. The hybrid pair module is designed to realize high-frequency switching operation of high power medium-voltage power converters (1-10MVA, voltage range 3... 10kV). In order to realize a low switching loss operation of the hybrid pair module, a hard gate driving with low gate resistor has been employed. Switching characteristics of the hybrid pair are evaluated experimentally and compared with that of a conventional 4.5 kV Si-IEGT and Si-PiN diode pair (All Si). The results show that the reverse recovery loss of diode and the turn-on loss of the Si-IEGT are reduced up to 95% and 60%, respectively. As a result, the total switching loss (i.e. turn-on and turn-off losses of the Si-IEGT plus reverse recovery loss of the diode) can be reduced up to 49% with the hybrid pair. The developed hybrid pair modules are applied to a prototype high power converter, and a high-frequency switching operation of 4 kHz has been successfully demonstrated..
16.	Kazuto Takao, Keiji Wada, Kyungmin Sung, Yuji Mastuoka, Yasunori Tanaka, Shinichi Nishizawa, Chiharu Ota, Takeo Kanai, Takashi Shinohe, Hiromichi Ohashi, Maximum Switching Frequency Characterization of 4.5kV-400A SiC-PiN diode and Si-IEGT Hybrid Pair Power Module, 2013 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION (ECCE), 1570-1576, 2013.10, The maximum switching frequency of a 4.5 kV-400 A SiC-PiN diode and Si-IEGT hybrid pair module has been analyzed from the viewpoints of cooling capacity of the hybrid pair module and the minimum pulse width of the PWM signal. In the developed hybrid pair module, a direct water cooling type heat sink is employed to enhance the cooling capacity. It found that the developed 4.5 kV-400 A hybrid pair module could be operate at 10 kHz PWM switching frequency with the peak current of 110 A and the dc voltage of 2.5 kV. In this operating condition, the power losses of the Si-IEGT and SiC-PiN diode in the hybrid pair module are 2380W and 100 W, respectively..
17.	Kazuto Takao, Keiji Wada, Kyungmin Sung, Yuji Mastuoka, Yasunori Tanaka, Shinichi Nishizawa, Chiharu Ota, Takeo Kanai, Takashi Shinohe, Hiromichi Ohashi, Experimental evaluation of 10kHz switching operation of 4.5kV-400A SiC-PiN diode and Si-IEGT hybrid pair module, 2013 IEEE Energy Conversion Congress and Exposition, ECCE 2013, 10.1109/ECCE.2013.6646893, 1577-1583, 2013.10, Possibility of a 10 kHz switching frequency operation of a 4.5kV-400A SiC-PiN diode and Si-IEGT hybrid pair module has been investigated to drastically increase the switching frequency of medium-voltage power converters. For this purpose, the relation among the minimum pulsed width of the PWM signal, the modulation index, and the maximum switching frequency is analyzed based on the switching characteristics of the hybrid pair module. The analyzed data show that the 10 kHz switching frequency could be available with the hybrid pair module. © 2013 IEEE..
18.	Pucheng Liu, Kuniyuki Kakushima, Hiroshi Iwai, Akira Nakajima, Toshiharu Makino, Masahiro Ogura, Shinichi Nishizawa, Hiromichi Ohashi, Characterization of Two-Dimensional Hole Gas at GaN/AlGaN Heterointerface, 2013 1ST IEEE WORKSHOP ON WIDE BANDGAP POWER DEVICES AND APPLICATIONS (WIPDA), 155-158, 2013.08, Electrical properties of two-dimensional hole gas (2DHG) at GaN/Al0.23Ga0.77N heterointerface have been investigated. Existence of 2DHG at the interface is confirmed by capacitance-voltage and Hall Effect measurement. We have discussed transport mechanism of 2DHG by comparison with hole generated by conventional Mg impurity, based on experimental evaluations by X-ray diffraction, transmission electron microscope, atomic force microscope, secondary ion mass spectroscopy, and temperature dependence Hall Effect measurements..
19.	Kyungmin Sung, Ryuji Iijima, Shinichi Nishizawa, Isami Norigoe, Hiromichi Ohashi, Experimental Investigation of Normally-On Type Bidirectional Switch for Indirect Matrix Converters, 2014 INTERNATIONAL POWER ELECTRONICS CONFERENCE (IPEC-HIROSHIMA 2014 - ECCE-ASIA), 10.1109/IPEC.2014.6869568, 117-122, 2014.05, In this paper, the novel normally-on type bidirectional switch, in which is comprised of SiC-JFET, SiC-SBD, and Si-IGBT is proposed for one of a protection method of the Matrix Converter (MC). When the MC becomes gate block situation, a diode clamp circuit or auxiliary circuits keeps inductive load current loop in a conventional MC utilized a bidirectional switch. We focus that the normally-on type SiC-JFET becomes turn-on state, when zero gate bias voltage and a SiC-devices have a good tolerance capability for short current than silicon devices. These characteristic of normally-on type SiC-JFET is used to replace diode clamp circuit in MC driver system. The experimentation based on indirect MC induction motor driver system was carried out. The experimental result of IM driver shows that the proposed bidirectional switch can overcome a generated inductive load current by IM. Finally, in order to design heat sink, the power loss of each devices of proposed switch was estimated by experimental results..
20.	Kazunori Hasegawa, Ichiro Omura, Shin-ichi Nishizawa, An Evaluation Circuit for DC-Link Capacitors Used in a High-Power Three-Phase Inverter with Condition Monitoring, 2018 INTERNATIONAL POWER ELECTRONICS CONFERENCE (IPEC-NIIGATA 2018 -ECCE ASIA), 1938-1942, 2018.05, This paper presents a condition monitoring method of dc-link capacitors used in a high-power three-phase PWM inverter intended for load life testing with an evaluation circuit consisting a low-voltage inverter. The evaluation circuit provides the equivalent ripple current waveform and dc-bias voltage to those of the high-power inverter. Hence, the monitoring method allows the load life testing with the equivalent condition to the high-power inverter at low cost. Experimental results verify that the monitoring method extracts both the ESR and capacitance changes of a capacitor under test..
21.	Peng Luo, Sankara Narayanan Ekkanath Madathil, Shin Ichi Nishizawa, Wataru Saito, High dV/dt controllability of 1.2kV TCIGBT through dynamic avalanche elimination, PCIM Asia 2020 - International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, Proceedings, 176-180, 2020.08, High dV/dt controllability of IGBTs is important to achieve high power efficiency and switching speed. However, the Dynamic Avalanche (DA) phenomenon in MOS-gated bipolar devices is one major issue to affect dV/dt controllability, switching loss as well as gate stability. In this paper, the fundamental limit of the turn-off dV/dt controllability of trench IGBTs is analyzed through 3-D TCAD simulations. A DA free design enabled by Trench Clustered IGBT (TCIGBT) is investigated to show significant improvement in dV/dt controllability compared to that of conventional TIGBT at same turn-off energy loss (Eoff) condition. Furthermore, experimental results confirm that TCIGBT can remain DA free performance and high dV/dt controllability at high temperature..
22.	Taichi Ogawa, Wataru Saito, Shin-Ichi Nishizawa, Slit Field Plate Power MOSFET for Improvement of Figure-Of-Merits, IEEE Journal of the Electron Devices Society, 10.1109/JEDS.2021.3079396, 9, 552-556, 2021.09.
23.	Wataru Saito, Shin-Ichi Nishizawa, Zoomed Response Surface Method for Automatic Design in Parameters Optimization of Low-Voltage Power MOSFET, IEEE Journal of the Electron Devices Society, 10.1109/JEDS.2022.3187151, 10, 512-515, 2022.10, A new parameter optimization method using zoomed response surface (RS) is proposed for automatic design of low-voltage power MOSFET. Low-voltage MOSFET characteristics have been improved continuously considering with not only low power loss but also low cost to answer request to high-performance system. Complicated requirements lead long development schedule and low yield. Model-based design and machine learning are prospective method to answer the problem. However, reported methods require many simulation numbers (>1000) for training to obtain high accuracy, and it is difficult to optimize parameters considering the process margin at the same time. This article shows a simple design method using zoomed RS. Five parameters were automatically designed, taking account to process margin with simulation number of 130 only..
24.	Zaiqi Lou, Yunjie Zhu, Shin Ichi Nishizawa, Wataru Saito, The Effect of Parallel-Connected Varistor on UIS Robustness of SiC MOSFETs for Solid-State Circuit Breakers Application, ETG-Fachbericht, 2022-March, 165, 175-179, 2022.03, This paper aims to clarify the effect of parallel-connected varistor on unclamped inductive switching (UIS) robustness of SiC MOSFETs to improve the cut-off current capability of solid-state circuit breakers (SSCB). Because the operation of UIS tests is similar to that in the interruption of SSCB, UIS tests of SiC MOSFETs without varistor and with a parallel-connected varistor were implemented. It was found that the cut-off current of SiC MOSFETs with the varistor is much larger than that of SiC MOSFETs without varistor. The effect of varistor on increase of cut-off current depends on the MOS-gate type. The cut-off current is 3-5 times higher for planar-gate devices and 5-10 times higher for trench-gate devices compared with no varistor condition. To analyze mechanism of cut-off current increased by the varistor, the junction temperature in UIS tests with and without the varistor was estimated by simulation using experimental wave-forms. The simulation results show that the destruction mechanism of SiC MOSFETs is changed by varistor connection due to change of self-heating timing during the UIS..
25.	Wataru Saito, Shin-ichi Nishizawa, Switching Noise-Loss Trade-Off Improvement of SJ-IGBTs, 2022 IEEE 34TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD), 10.1109/ISPSD49238.2022.9813643, 2022-May, 53-56, 2022.05, Design of trench gate and p-column position in Superjunction (SJ)-IGBTs are discussed to improve the trade-off characteristics between surge voltage/current and turn-off/-on losses. Power electronics systems require not only low power loss but also low EMI noise for high cost performance by system downsizing. Although SJ-IGBTs are attractive for low loss operation due to thin drift layer and fast removal of the excess carriers through the p- and n-columns at the turn-off operation, the switching trade-off characteristics of SJ-IGBTs compared with the conventional IGBT and the improvement design have not been discussed sufficiently. This paper shows better switching trade-off compared with a conventional IGBT can be obtained by the trench gate and p-column designs due to management of the gate capacitance and hole current flow, because negative gate capacitance influences on not only turn-on switching but also turn-off switching..
26.	Norman Boettcher, Taro Takamori, Keiji Wada, Wataru Saito, Shin Ichi Nishizawa, Tobias Erlbacher, Short Circuit Performance and Current Limiting Mode of a Monolithically Integrated SiC Circuit Breaker for DC Applications up to 800 v, 24th European Conference on Power Electronics and Applications, EPE 2022 ECCE Europe, 2022.09, This paper presents the short circuit performance of a novel SiC circuit breaker device, which is based on the 'thyristor dual' functionality. The developed device structure is motivated with regard to manufacturing aspects and electrical requirements. Furthermore, the basic 'thyristor dual' operation is elaborated on the basis of quasi-static electrical measurements of a fabricated prototype. The proposed self-sensing and self-triggering devices make auxiliary circuitry like sensors and micro-controllers expendable and practically have no propagation delay. As a result, short circuit clearance within 122 ns at 800 V is demonstrated in experiments. Moreover, by utilisation of a third device terminal, a temporary current limiter functionality can be obtained. The scalability of the current limit value is discussed on the basis of measurements in time domain. The maximum current limit value achieved is 7.4 times higher than the trigger current level of the circuit breaker device. Additionally, the same circuit configuration which is used for the current limiting mode, allows to remotely reset the circuit breaker after it turned to blocking-state. This opens up a wide range of possibilities to enhance the circuit breaker with intelligent functionalities..
27.	Wataru Saito, Shin-Ichi Nishizawa, Scaling Design Effects on Surface Buffer IGBT Characteristics, IEEE Journal of the Electron Devices Society, 10.1109/JEDS.2021.3129162, 10, 23-28, 2022.10, Scaling design effects on surface buffer (SB) insulated gate bipolar transistor (IGBT) is analyzed not only for power loss reduction but also for switching controllability and robustness using TCAD simulation. Although the scaling design improves turn-off loss and on-state voltage drop V-ce(sat) trade-off due to injection enhancement (IE) effect, turn-on surge current is increased by the enhancement of negative gate capacitance due to thin gate oxide. Dual gate control improves turn-on switching controllability by hole current path control. Short circuit robustness is improved by the scaling design, because the saturation current is decreased with the scaling design due to pinch-off of the n-MOS channel. From these results, the scaling design is effective in improving the SB-IGBT characteristics including high robustness..
28.	Taro Takamori, Keiji Wada, Wataru Saito, Shin Ichi Nishizawa, Paralleled SiC MOSFETs DC Circuit Breaker with SiC MPS Diode as Avalanche Voltage Clamping, Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC, 10.1109/APEC43599.2022.9773380, 225-229, 2022.03, This paper proposes a solid-state DC circuit breaker composed of SiC MOSFETs and a SiC diode, based on the principle of avalanche voltage clamping. To realize a solid-state DC circuit breaker, it is necessary to reduce the conduction loss and increase the breaking capability. A parallel connection of power semiconductor devices is the most suitable configuration that can meet these requirements. However, in such a configuration, the current balance during current interruption may be affected by the difference in the breakdown voltage characteristics of the power semiconductor devices. The proposed solid-state DC circuit breaker is clamped using a SiC merged pin Schottky diode with high avalanche tolerance and robust characteristics under repetitive avalanche events. Experimental results from an unclamped inductive switching test circuit with a 400-V DC distribution system show that the proposed solid-state DC circuit breaker can interrupt currents up to 50-A..
29.	Peng Luo, Sankara Narayanan Ekkanath Madathil, Wataru Saito, Shin Ichi Nishizawa, Investigation of turn-on performance in 1.2 kV MOS-bipolar devices, Japanese Journal of Applied Physics, 10.35848/1347-4065/ac40aa, 61, 2022.02, In this paper, the turn-on characteristics of the 1.2 kV Trench IGBT (TIGBT) and the 1.2 kV Trench Clustered IGBT (TCIGBT) are investigated through TCAD simulations and experiments. The TCIGBT shows much lower turn-on energy loss (E on) due to higher current gain than an equivalent TIGBT and the negative gate capacitance effect is effectively suppressed in the TCIGBT by its self-clamping feature and PMOS action. In addition, the impact of 3D scaling rules on the turn-on performance of TIGBT and TCIGBT is analyzed in detail. Simulation results show that scaling rules result in a significant reduction of E on in both TIGBT and TCIGBT. Furthermore, the experimental results indicate that TCIGBT technology is well suited for high current density operations with low power losses. Compared to the state-of-the-art IGBT technology, an 18% reduction of total power loss can be achieved by the TCIGBT operated at 300 A cm-2 and 175 °C..
30.	Norman Boettcher, Taro Takamori, Keiji Wada, Wataru Saito, Shin Ichi Nishizawa, Tobias Erlbacher, Fabrication Aspects and Switching Performance of a Self-Sensing 800 V SiC Circuit Breaker Device, Proceedings of the International Symposium on Power Semiconductor Devices and ICs, 10.1109/ISPSD49238.2022.9813628, 2022-May, 261-264, 2022.05, This work presents the switching performance of a novel solid-state circuit breaker device suitable for DC-applications up to 800 V. These "dual thyristor"devices are manufactured employing a 4H-SiC JFET technology. With respect to scalability, the influence of specific design parameters on the quasi-static output characteristics are discussed along with corresponding fabrication aspects. In order to investigate the switching performance, clamped and unclamped inductive switching (CIS and UIS) experiments at up to 800 V are carried out. In case of CIS, current clearance is achieved within 642 ns after the self-sensed trigger event at 1.75 A. The UIS experiments reveal stable current handling capability during avalanche..
31.	Wataru Saito, Zaiqi Lou, Shin Ichi Nishizawa, Cutoff Current Capability of SiC-MOSFETs with Parallel Connected Varistor under UIS Condition, IEEE Workshop on Wide Bandgap Power Devices and Applications in Europe, WiPDA Europe 2022, 10.1109/WiPDAEurope55971.2022.9936060, 2022.09, Unclamped inductive switching (UIS) robustness of SiC MOSFETs with parallel connected varistor was evaluated to design the cutoff current capability of solid-state circuit breakers. Because the operation of UIS tests is similar to that in the interruption of solid-state circuit breakers, UIS tests of SiC MOSFETs without varistor and with a parallel-connected varistor were implemented. It was found that the cutoff current of SiC MOSFETs with the varistor was 3 to 6 times larger than that without varistor. The index of rating current for cutoff current capability was changed by parallel varistor connection, because the destruction mechanism of SiC MOSFETs was changed because of the change in self-heating timing during the UIS. From dependence of cutoff current on rating current, load inductance and varistor voltage, it is verified that the cutoff current of SiC MOSFET with varistor was limited by saturation current and current filament..
32.	Taro Takamori, Keiji Wada, Norman Boettcher, Tobias Erlbacher, Wataru Saito, Shin Ichi Nishizawa, Adjustable Current Limit Feature with a Self-Sensing and Self-Triggering Monolithically Integrated SiC Circuit Breaker Device, 2022 IEEE Energy Conversion Congress and Exposition, ECCE 2022, 10.1109/ECCE50734.2022.9948054, 2022.10, This paper proposes a current limit feature for a multi-functional SiC circuit breaker device with a “dual thyristor” structure. The proposed feature provides the device not only with a fast-response current breaking operation but also with the current limiting function, including supplying a constant current to the load and preventing the detection of inrush currents. The proposed feature is suitable for replacing mechanical circuit breakers in initial charging circuits for the rectifiers and a safety equivalent in case of overcurrent accidents. The proposed method achieves various constant currents by simply varying the gate-drive circuit with adjustable parameters of an additional MOSFET. Experimental results verified that the device with the current limit feature reduces the inrush current to up to 22.6% of capacitive load condition using a 500 VDC circuit system..
33.	Jiuyang Yuan, Yoshiji Miyamura, Satoshi Nakano, Wataru Saito, Shin Ichi Nishizawa, The Study of Dislocation Propagation in Si Wafer during IGBT High Thermal Budget Process, 7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023, 10.1109/EDTM55494.2023.10103031, 2023.03, There are several thermal budget processes for Si-IGBT fabrication, which sometimes cause dislocation propagation. The dislocation propagation depends on temperature and time of the process. In this paper, we analyzed the dislocation propagation in Si wafer during Si-IGBT fabrication process. We also calculated the dislocation density during diffusion process with several temperatures and times, and we confirmed that the lower temperature process causes the smaller dislocation propagation which may carry out the good device performance..
34.	Zaiqi Lou, Thatree Mamee, Katsuhiro Hata, Makoto Takamiya, Shin-Ichi Nishizawa, Wataru Saito, IGBT Power Module Design for Suppressing Gate Voltage Spike at Digital Gate Control, IEEE Access, 10.1109/access.2023.3237266, 11, 6632-6640, 2023.01, This paper clarifies the effect of gate inductance $L_{g}$ inside IGBT modules on gate voltage spikes when a digital gate driver is employed. Three IGBT modules with different $L_{g}$ were fabricated to implement double pulse tests by conventional gate driving and digital control gate driving with three-step vectors. It was found that the tradeoff between switching loss and voltage/current overshoots can be improved by digital control, but a large gate voltage spike was generated when gate-driving vectors were changed. And the spike voltage $V_{g_{}spike}$ was positively correlated to the $L_{g}$. Although the $V_{g_{}spike}$ can also be suppressed by decreasing the difference of gate driving vectors between the first and the second steps, the improvement of the tradeoff is weakened. Therefore, it is required that the $L_{g}$ inside the IGBT modules should be reduced to suppress the $V_{g_{}spike}$ while improving the tradeoff by the digital gate driver at the same time. Furthermore, by analyzing the oscillation of the $V_{g_{}spike}$ , it indicates that there should be some other stray elements, which couple $L_{g}$ and the stray capacitance inside IGBT chips, affecting the $V_{g_{}spike}$..
35.	Wataru Saito, Shin-Ichi Nishizawa, Simulation Study on Dual Gate Control of Surface Buffer Insulated Gate Bipolar Transistor for High Switching Controllability, IEEE Electron Device Letters, 10.1109/LED.2021.3075657, 42, 6, 907-910, 2021.06.
36.	Ryota Suewaka, Shin ichi Nishizawa, Impact of Marangoni effect of oxygen on solid–liquid interface shape during Czochralski silicon growth applied with transverse magnetic field, Journal of Crystal Growth, 10.1016/j.jcrysgro.2023.127123, 607, 2023.04, This study investigated the impact of the Marangoni effect of oxygen on the solid–liquid interface shape in the silicon single-crystal growth process by the transverse magnetic-field-applied Czochralski (Cz) method. To this end, the results of a 3D heat and mass transfer analysis were compared with the experimental results. The findings of the study revealed that the Marangoni effect of oxygen affected the solid–liquid interface shape predicted by the simulation. Moreover, with the introduction of this effect, both the solid–liquid interface shape and temperature distribution of the melt were found to be in good agreement with the experimental values..
37.	Kazuma Miyazaki, Satoshi Nakano, Shin ichi Nishizawa, Koichi Kakimoto, Effect of crucible thermal conductivity on dislocation distribution in crystals in a silicon carbide physical vapor transport furnace, Journal of Crystal Growth, 10.1016/j.jcrysgro.2022.126981, 603, 2023.02, The effect of the thermal conductivity of a crucible in a silicon carbide physical vapor transport furnace on the dislocation distribution in crystal was investigated using numerical analysis. The numerical analysis includes stress and dislocation propagation calculations based on the Alexander–Haasen model. Modifying the thermal conductivity of the carbon crucible can reduce the dislocation density. It can also homogenize the temperature distribution in the radial distribution in the crystal. The density of dislocations could be further by reduced using a carbon crucible with low thermal conductivity..
38.	Zaiqi Lou, Wataru Saito, Shin ichi Nishizawa, Application of N parallel-connected SiC MOSFETs to solid-state circuit breakers based on UIS tests, Microelectronics Reliability, 10.1016/j.microrel.2022.114737, 138, 2022.11, N parallel-connected SiC MOSFETs were investigated to apply to solid-state circuit breakers (SSCB), and it is an extension of a method that was proved valid by experiment of two parallel-connected SiC MOSFETs. The unclamped inductive switching (UIS) test was considered as the emergency interruption of SSCBs in this research. Because of the variations of breakdown voltage among SiC MOSFETs, the current flowing through devices is imbalanced during emergency interruption of SSCBs, which can drive some of the devices into thermal destruction prematurely. There are many compound cases for several SiC MOFETs with a certain maximum breakdown voltage variation. And the worst case, where the breakdown voltage of one device is assumed as the lowest, whereas the other devices have the same breakdown voltage, was extracted from the calculated results of four parallel-connected situation. In the worst case, it was found that the relation of breakdown voltage variations and current capacity is linear. Moreover, the distributions of breakdown voltage were taken as normal distributions. Using the worst case and distributions, a linear relation of breakdown voltage distributions and rated current of an SSCB could be concluded as a function of paralleled-connected numbers (N). Utilizing the function, the necessary breakdown voltage distributions and N of SiC MOSFETs can be evaluated for SSCBs meeting a certain yield ratio and current..
39.	Kaoru Kajiwara, Kazutaka Eriguchi, Kazuhiro Fusegawa, Noritomo Mitsugi, Shuichi Samata, Kazuhisa Torigoe, Kazuhiro Harada, Masataka Hourai, Shin-Ichi Nishizawa, Nitrogen-Doped Czochralski Silicon Wafers as Materials for Conventional and Scaled Insulated Gate Bipolar Transistors, IEEE Transactions on Semiconductor Manufacturing, 10.1109/TSM.2022.3199862, 35, 4, 620-625, 2022.11, Nitrogen-doped silicon wafers manufactured using the Czochralski technique (Cz-Si) with an oxygen concentration (OI) of 2.5–5.6 × 1017 atoms cm-3 are heat treated to simulate the conventional and scaled manufacturing processes of insulated gate bipolar transistors (IGBTs). Subsequently, the oxygen precipitation, lifetime, and gate oxide integrity (GOI) of the Cz-Si wafers are evaluated. After the high-temperature heat treatment that simulates the conventional process, the lifetime of the Cz-Si with an OI of 5.6 × 1017 atoms cm-3 only degrades slightly even when oxide precipitates are not detected. In contrast, after the low-temperature heat treatment that simulates the scaled process, oxide precipitates are detected and the lifetime reduces substantially at an OI of 5.6 × 1017 atoms cm-3. The Cz-Si with OI values below 3.3 × 1017 atoms cm-3 are considered suitable materials for IGBTs because no oxide precipitate is formed, and the lifetime is not degraded after high-and low-temperature heat treatments. Upon using GOI evaluation, the nitrogen-doped Cz-Si wafers are found to exhibit a breakdown voltage equal to that of an annealed Cz-Si wafer conventionally used for IGBTs. Therefore, nitrogen-doped Cz-Si wafers with OI below 3.3 × 1017 atoms cm-3 are potential materials for conventional and scaled IGBTs..
40.	Wataru Saito, Zaiqi Lou, Shin-Ichi NIshizawa, Unclamped Inductive Switching Robustness of SiC Devices With Parallel-Connected Varistor, IEEE Transactions on Electron Devices, 10.1109/TED.2022.3200637, 69, 10, 5671-5677, 2022.10, Unclamped inductive switching (UIS) robustness of SiC devices with parallel-connected varistor was evaluated to design the cutoff current capability of solid-state circuit breakers (SSCBs). Because the operation of UIS tests is similar to that in the interruption of SSCBs, UIS tests of SiC devices without varistor and with a parallel-connected varistor were implemented. It was found that the cutoff current of SiC devices with the varistor was much larger than that without varistor. The effect of varistor on the increase of cutoff current depended on the device type and rating current. The cutoff current was 3-6 times higher for planar MOSFETs and 5-10 times higher for trench MOSFETs compared with no varistor condition. In contrast, the effect of varistor for JFET was small because the gate drive condition strongly affected the current switching time from SiC-JFET to varistor. The index of rating current for cutoff current capability was changed by parallel varistor connection because the destruction mechanism of SiC devices was changed because of the change in self-heating timing during the UIS..
41.	Mitsuhiko Sagara, Keiji Wada, Shin ichi Nishizawa, Wataru Saito, Avalanche current balancing using parallel connection of SiC-MOSFET/SiC-JFETs with cascode connection, Microelectronics Reliability, 10.1016/j.microrel.2021.114237, 126, 2021.11, The realization of a DC breaker using semiconductors requires multiple power devices with low ON resistance to be connected in parallel. On the other hand, power devices that experience current interruption enter the avalanche mode to consume the energy stored in the parasitic inductance in the circuit wiring. In other words, a DC breaker requires the current balancing of multiple power devices connected in parallel during the avalanche mode. In this paper, a method to balance the current of power devices in avalanche mode is investigated. As a result, the use of SiC-JFET with cascode connections is found to be a suitable method by 400 V experimental system..
42.	Zaiqi Lou, Keiji Wada, Wataru Saito, Shin ichi Nishizawa, Investigations on acceptable breakdown voltage variation of parallel-connected SiC MOSFETs applied to olid-state circuit breakers, Microelectronics Reliability, 10.1016/j.microrel.2021.114270, 126, 2021.11, This paper aims to investigate the acceptable breakdown voltage variation of parallel-connected SiC power MOSFETs applied to solid-state circuit breakers (SSCB) under different total current conditions and its numerical simulation model. Due to variation of breakdown voltage among SiC power MOSFETs, the current flowing through devices is imbalanced during emergency interruption of SSCBs, which can drive some of the devices into thermal destruction. The unclamped inductive switching (UIS) test was imaged as the emergency interruption of SSCBs in this research. The UIS test of two parallel-connected SiC power MOSFETs was implemented. Proposed numerical simulation represents the experimental results with failure criteria by considering self-heating due to imbalanced current flowing. And it was found that the acceptable breakdown voltage variation and the total current have a linear relation..
43.	Shigyo, N., Watanabe, M., Kakushima, K., Hoshii, T., Furukawa, K., Nakajima, A. Nakajima , K. Satoh , T. Matsudai, T. Saraya , T. Takakura , K. Itou , M. Fukui , S. Suzuki , K. Takeuchi , I. Muneta , H. Wakabayashi , Nishizawa,S., K. Tsutsui , T. Hiramoto , H. Ohashi Iwai, H., Modeling and simulation of si IGBTs. Paper presented at the International Conference on Simulation of Semiconductor Processes and Devices,, SISPAD, doi:10.23919/SISPAD49475.2020.9241627 , 129-132, 2021.09.
44.	Kaoru Kajiwara, Kazuhisa Torigoe, Kazuhiro Harada, Masataka Hourai, Shin ichi Nishizawa, Oxygen concentration dependence of as-grown defect formation in nitrogen-doped Czochralski silicon single crystals, Journal of Crystal Growth, 10.1016/j.jcrysgro.2021.126236, 570, 2021.09, The interstitial oxygen concentration ([OI]) dependence of the as-grown defect (voids and dislocation clusters) behavior in nitrogen-doped silicon crystals fabricated by Czochralski technique (Cz-Si) have been investigated. Nitrogen-doped Cz-Si crystals with [OI] values of 7–8 and 1–3 × 1017 atoms cm−3 are evaluated, and it was found that the range of v/G in which as-grown defect-free (AGDF) region can be obtained become wide with decreasing [O I], where v is the crystal growth rate and G is the axial temperature gradient at the solid–liquid interface. This result indicates that as-grown defect suppression effect by nitrogen doping is enhanced at low [OI].By the analysis based on a thermodynamic model, it is shown that nitrogen–vacancy (NV) and nitrogen–oxygen (NO) complexes compete in the nitrogen-doped Cz-Si crystals and their concentration fraction changes with [OI] value. At low [OI], the concentration of the NO complex becomes low; thus, the concentration of nitrogen that can form NV complexes increases, thereby enhancing the as-grown defect suppression effect. Silicon wafers for insulated gate bipolar transistors (IGBTs) are required AGDF and oxide precipitate-free, therefore nitrogen-doped Cz-Si crystals with low [OI] values are suitable for the fabrication of silicon wafers for IGBTs..
45.	Yokogawa, R., Kobayashi, H., Numasawa, Y., Ogura, A., Nishizawa,S., Saraya, T., K.Itoh, T.Takakura, S.Suzuki, M.Fuui, K.Takeuchi and Hiramoto, T, Origin of carrier lifetime degradation in floating-zone silicon during a high-temperature process for insulated gate bipolar transisto, Japanese Journal of Applied Physics, doi:10.35848/1347-4065/abc1d0, 59, 11, 115503, 2021.06.
46.	Kaoru Kajiwara, Kazuhisa Torigoe, Kazuhiro Harada, Masataka Hourai, Shin-ichi Nishizawa, Oxygen concentration dependence of as-grown defect formation in nitrogen-doped Czochralski silicon single crystals, Journal of Crystal Growth, 570 , (2021), 126236, 2021.06, [URL].
47.	Wataru Saito, Shin Ichi Nishizawa, Simulation Study on Dual Gate Control of Surface Buffer Insulated Gate Bipolar Transistor for High Switching Controllability, IEEE Electron Device Letters, 10.1109/LED.2021.3075657, 42, 6, 907-910, 2021.06, A new device design in trench-gate insulated gate bipolar transistor (IGBT) with dual gate control is proposed for high switching controllability with low loss operation. Injection enhancement effect is effective to obtain low power loss operation of IGBTs. However, excess drift carriers limit turn-off dV/dt, and turn-on dI/dt, and the switching controllability by the external gate resistance is degraded. Surface buffer (SB) IGBT with dual gate control is effective to improve the switching controllability, because the hole current can be modulated effectively by the p-MOS control. TCAD simulation results show the SB-IGBT type-II with dual gate control is the best choice for good turn-off and turn-on switching performances..
48.	Taichi Ogawa, Wataru Saito, Shin Ichi Nishizawa, A design direction of low-voltage field-plate power MOSFETs for figure-of-merit (FOM) limit, Japanese Journal of Applied Physics, 10.35848/1347-4065/abe801, 60, SB, 2021.05, The design direction of low voltage field-plate (FP) power MOSFETs was studied toward the figure-of-merit (FOM) limit by TCAD simulation. The FOMs of R on Q g, R on Q sw, and R on Q oss are considering the on-resistance and the charge required for the switching to evaluate the conduction loss and the switching loss. The results show that thin oxide and narrow mesa structure is desired for minimizing on-resistance R on A and opposite design of thick oxide and wide mesa structure is a good choice to reduce R on Q sw for high switching frequency application. In addition, the potential of R on A and R on Q sw reduction is maintained, however, it is difficult to reduce the R on Q g and R on Q oss by the design parameter optimization. It is verified that power loss reduction in whole operating condition cannot be achieved only by the design parameter optimization and requires approach from the other direction..
49.	Zaiqi Lou, Wataru Saito, Shin Ichi Nishizawa, Investigation of acceptable breakdown voltage variation for parallel-connected SiC MOSFETs during unclamped inductive switching test, Japanese Journal of Applied Physics, 10.35848/1347-4065/abebc1, 60, SB, 2021.05, Current flowing through parallel-connected SiC MOSFETs are imbalanced during unclamped inductive switching (UIS) test, which can be imaged as the emergency interruption of solid-state circuit breakers, due to variations of breakdown voltage. The imbalanced current can drive devices into thermal destruction. This study evaluated acceptable breakdown voltage variations of two parallel-connected SiC MOSFETs under different total current, load inductances, and breakdown voltage temperature coefficient conditions during UIS mode operation by numerical simulation. The acceptable variation at 298 K was found to decrease with increasing total current and be influenced by the change of total current greater with larger inductances. SiC MOSFETs with larger breakdown voltage temperature coefficients allowing larger variations were also clarified..
50.	Wataru Saito, Shin Ichi Nishizawa, Power Loss Reduction of Low-Voltage Power MOSFET by Combination of Assist Gate Structure and Gate Control Technology, Proceedings of the International Symposium on Power Semiconductor Devices and ICs, 10.23919/ISPSD50666.2021.9452240, 2021-May, 271-274, 2021.05, A new structure with the optimum gate control is proposed for low power loss operation of low-voltage power MOSFETs. Although the application system requires continuing the on-resistance RonA reduction for more power efficiency improvement, RonA trend is facing the theoretical limit even with the FP technology. Assist Gate (AG) structure was proposed to improve the RonA and turn-off loss Eoff tradeoff, because the channel and drift resistances can be reduced with avoiding the Cgd increase by dual gate control. Dual gate control with synchronous rectify (SR) of AG-MOSFET also improves turn-on switching performance. This paper shows the AG-MOSFET with optimum gate control achieves 27% lower turn-on loss Eon and 42% lower surge current compared with no SR operation. A case study of the half-bridge application also shows 17% to 46% of total power loss reduction..
51.	M. Watanabe, N. Shigyo, T. Hoshii, K. Furukawa, K. Kakushima, K. Satoh, T. Matsudai, T. Saraya, T. Takakura, I. Muneta, H. Wakabayashi, A. Nakajima, S. Nishizawa, K. Tsutsui, T. Hiramoto, H. Ohashi, H. Iwai, Accurate TCAD simulation of trench-gate IGBTs and its application to prediction of carrier lifetime requirements for future scaled devices, 2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021, 10.1109/EDTM50988.2021.9420922, 2021.04, Silicon trench-gate insulated gate bipolar transistors (IGBTs) were analyzed using technology CAD (TCAD). Excellent agreement was confirmed between the J_{C}^{- } }V_{ ext{CE} characteristics obtained by 3D- TCAD simulations and experiments. The carrier lifetime requirement for scaled trench-gate IGBTs was determined by extraction of the on-resistance of the n-base layer derived from the electric potential profile..
52.	Taichi Ogawa , Wataru Saito and Shin-ichi Nishizawa, A design direction of low-voltage field-plate power MOSFETs for figure-of-merit (FOM) limit, Japanese Journal of Applied Physics, 10.35848/1347-4065/abe801, 60, SBBD16-1-SBBD16-5, 2021.03.
53.	Lou, Z., Saito, W. and Nishizawa,S., Investigation of acceptable breakdown voltage variation for parallel-connected SiC MOSFETs during unclamped inductive switching test, Japanese Journal of Applied Physics, 60, SBBD18(2021), https://doi.org/10.35848/1347-4065/abebc1, 2021.03.
54.	Peng Luo, Sankara Narayanan Ekkanath Madathil, Shin-Ichi Nishizawa, Wataru Saito, Turn-OFF dV/dt Controllability in 1.2-kV MOS-Bipolar Devices, IEEE Transactions on Power Electronics, 36, (3), 3304-3311, 2021.03.
55.	Miyamura, Y., Harada, H., Nakano, Nishizawa,S. & Kakimoto, K., Carbon monoxide concentrations in a czochralski growth furnace, Journal of Crystal Growth, doi:10.1016/j.jcrysgro.2020.126015, 558, 15, 126015, 2021.03.
56.	Y. Miyamura, H. Harada, S. Nakano, S. Nishizawa, K. Kakimoto, Carbon monoxide concentrations in a Czochralski growth furnace, Journal of Crystal Growth, 10.1016/j.jcrysgro.2020.126015, 558, 2021.03, High-performance power devices require silicon crystals with long minority carrier lifetimes and, subsequently, low carbon concentrations. This paper reports in-situ measurements of carbon monoxide (CO) in a Czochralski growth furnace used for the growth of single-crystal silicon. During the heating and melting processes, the major causes of CO gas generation are (i) outgassing from carbon parts inside the furnace, (ii) reactions between the quartz and carbon crucible, and (iii) reactions between the silicon melt and quartz crucible. By conducting heating experiments with and without polysilicon and quartz crucibles, we successfully measured the independent CO generation contributions of causes (i), (ii), and (iii) listed above. The outgassing process generated CO gas during the heating process of the raw material. CO generated during the melting process of the raw material was attributed to reactions between (ii), the quartz and carbon, and (iii), the silicon melt and carbon parts, which occurred after CO outgassing from carbon parts in the furnace..
57.	Peng Luo, Sankara Narayanan Ekkanath Madathil, Shin-Ichi Nishizawa, Wataru Saito, Turn-OFF dV/dt Controllability in 1.2-kV MOS-Bipolar Devices, IEEE Transactions on Power Electronics, 10.1109/tpel.2020.3014560, 36, 3, 3304-3311, 2021.03, Turn-off dV/dt controllability is an essential feature in insulated gate bipolar transistors (IGBTs) for flexible design in power switching applications. However, the occurrence of dynamic avalanche (DA) during the turn-off transients plays a key role on the turn-off power loss, dV/dt controllability and safe operating area of IGBTs. This article aims to clarify the impact of DA on the turn-off characteristics of 1.2-kV trench IGBTs through three-dimensional technology computer aided design (TCAD) simulations as well as experimental demonstrations. Measurement results show that DA is enhanced at high current density and high supply voltage conditions, which aggravates its influence on the dV/dt controllability as well as turn-off power loss. To eliminate the DA for high current density and low loss operations, a DA free design is experimentally demonstrated in the Trench Clustered IGBT (TCIGBT). Due to effective management of electric field and unique p-channel metal oxide semiconductor (PMOS) actions during turn-off, TCIGBT can retain high dV/dt controllability and low power loss at high current density operations..
58.	Peng Luo, Sankara Narayanan Ekkanath Madathil, Shin-Ichi Nishizawa, Wataru Saito, Turn-OFF dV/dt Controllability in 1.2-kV MOS-Bipolar Devices, IEEE Transactions on Power Electronics, 10.1109/TPEL.2020.3014560, 36, 3, 3304-3311, 2021.03.
59.	T. Saraya, K. Itou, T. Takakura, M. Fukui, S. Suzuki, K. Takeuchi, M. Tsukuda, K. Satoh, T. Matsudai, K. Kakushima, T. Hoshii, K. Tsutsui, H. Iwai, A. Ogura, W. Saito, S. Nishizawa, I. Omura, H. Ohashi, T. Hiramoto, 3.3 kV back-gate-controlled IGBT (BC-IGBT) using manufacturable double-side process technology, Technical Digest - International Electron Devices Meeting, IEDM, 10.1109/IEDM13553.2020.9371909, 2020-December, 5.3.1-5.3.4, 2020.12, Full integration of a back-gate-controlled IGBT (BC-IGBT), which comprises top and bottom independently controlled MOS gates, is experimentally demonstrated. By using the back side MOS gate for accelerating electron drain and blocking of hole injection, more than 60% reduction of turn-off loss was achieved. Instead of the conventional wafer bonding approach, a cost effective process flow using double side lithography has been developed and used. Thanks to the process flexibility, back side design was carefully optimized to achieve stable operation and manufacturability, in addition to low switching loss. BC-IGBT will provide a new technological option for expanding the applicable switching frequency / voltage range of Si power devices..
60.	Wataru Saito, Shin-Ichi Nishizawa, Improvement Design for Turn-On Switching Characteristics in Surface Buffer Insulated Gate Bipolar Transistor, IEEE Electron Device Letters, 10.1109/led.2020.3034898, 41, 12, 1814-1816, 2020.12, A design direction in surface buffer insulated gate bipolar transistor (SB-IGBT) is shown for improvement of turn-on switching characteristics, such as switching controllability, current surge and turn-on loss. At turn-on switching, hole current around the gate degrades the switching controllability and induces EMI noise due to negative gate capacitance. However, SB-IGBT can be designed to suppress the negative gate capacitance by enhancement of hole evacuation through pMOS channel. Although turn-on loss can be decreased by small gate-collector capacitance C {gc} , the influence of negative gate capacitance is remarkable. Therefore, TCAD simulation results show that high hole evacuation through pMOS channel and optimum C {gc} design are effective to improve turn-on switching characteristics..
61.	Wataru Saito, Shin-Ichi Nishizawa, Improvement Design for Turn-On Switching Characteristics in Surface Buffer Insulated Gate Bipolar Transistor, IEEE Electron Device Letters, 10.1109/LED.2020.3034898, 41, 12, 1814-1816, 2020.12.
62.	Taro Takamori, Keiji Wada, Wataru Saito, Shin-ichi Nishizawa, Gate drive circuit for current balancing of parallel-connected SiC-JFETs under avalanche mode, Microelectronics Reliability, 10.1016/j.microrel.2020.113776, 114, 113776-113776, 2020.11, This paper proposes a gate drive circuit for the current balancing of parallel-connected SiC-JFETs under avalanche mode. For a solid-state DC circuit breaker, the power devices have to be connected in parallel to reduce the ON-resistance and increase the current rating. In addition, it is reported that the SiC-JFET is suitable power devices from the viewpoint of both conduction loss and long-term reliability. This paper presents the behavior of current balancing of SiC-JFETs in parallel, and then proposes a design procedure of gate drive circuits. The gate drive circuits can achieve the current balance equalization of parallel-connected SiC-JFETs under avalanche mode. The validity of the proposed gate drive circuit is verified by the experiment that uses 1.2 kV SiC-JFETs in a 400 V system..
63.	Ryo Yokogawa, Hiroto Kobayashi, Yohichiroh Numasawa, Atsushi Ogura, Shin-ichi Nishizawa, Takuya Saraya, Kazuo Ito, Toshihiko Takakura, Shinichi Suzuki, Munetoshi Fukui, Kiyoshi Takeuchi, Toshiro Hiramoto, Origin of carrier lifetime degradation in floating-zone silicon during a high-temperature process for insulated gate bipolar transistor, Japanese Journal of Applied Physics, 10.35848/1347-4065/abc1d0, 59, 11, 115503-115503, 2020.11, We report on the relationship between carrier lifetime degradation of floating-zone silicon (FZ Si) and the guard ring formation process for silicon integrated gate bipolar transistor (Si-IGBT). A clear carrier lifetime degradation was observed through the guard ring oxidation and annealing processes for Si-IGBT and showed interstitial oxygen (Oi) concentration dependence, which was obtained by Fourier transform infrared absorption spectroscopy. Based on the carrier lifetime measurements through the step etching of the FZ Si substrate, it has been suggested that the carrier lifetime degradation is not only caused by the Oi itself near the FZ Si surface region but also the other defects induced by the Oi injection. Diffused interstitial Si atoms kicked-out by the Oi into the FZ Si substrate, which has a longer diffusion length than Oi, can be considered to be the origin of the carrier lifetime degradation..
64.	Ryo Yokogawa, Hiroto Kobayashi, Yohichiroh Numasawa, Atsushi Ogura, Shin-ichi Nishizawa, Takuya Saraya, Kazuo Ito, Toshihiko Takakura, Shinichi Suzuki, Munetoshi Fukui, Kiyoshi Takeuchi, Toshiro Hiramoto, Origin of carrier lifetime degradation in floating-zone silicon during a high-temperature process for insulated gate bipolar transistor, Japanese Journal of Applied Physics, 10.35848/1347-4065/abc1d0, 59, 11, 2020.11, We report on the relationship between carrier lifetime degradation of floating-zone silicon (FZ Si) and the guard ring formation process for silicon integrated gate bipolar transistor (Si-IGBT). A clear carrier lifetime degradation was observed through the guard ring oxidation and annealing processes for Si-IGBT and showed interstitial oxygen (O-i) concentration dependence, which was obtained by Fourier transform infrared absorption spectroscopy. Based on the carrier lifetime measurements through the step etching of the FZ Si substrate, it has been suggested that the carrier lifetime degradation is not only caused by the O-i itself near the FZ Si surface region but also the other defects induced by the O-i injection. Diffused interstitial Si atoms kicked-out by the O-i into the FZ Si substrate, which has a longer diffusion length than O-i, can be considered to be the origin of the carrier lifetime degradation..
65.	Peng Luo, Sankara Narayanan Ekkanath Madathil, Shin-Ichi Nishizawa, Wataru Saito, Evaluation of Dynamic Avalanche Performance in 1.2-kV MOS-Bipolar Devices, IEEE Transactions on Electron Devices, 10.1109/ted.2020.3007594, 67, 9, 3691-3697, 2020.09, It is well-known that the dynamic avalanche (DA) phenomenon poses fundamental limits on the power density, turn-off power loss, dV/dt controllability, and long-term reliability of MOS-bipolar devices. Therefore, overcoming this phenomenon is essential to improve the energy efficiency and ensure their safe operation. In this work, a detailed analysis of the 1.2-kV MOS-bipolar devices is undertaken through both calibrated TCAD simulations and experiments to show the fundamental cause of DA and the impact of the current density, supply voltage, and 3-D scaling rules on the DA performance. Furthermore, the DA performance of a 1.2-kV non-punch-through (NPT) trench clustered insulated gate bipolar transistor (TCIGBT) is evaluated for high current density and low power loss operations. The results indicate that this device configuration is free of DA and can be used for ultrahigh current density operation in an energy-efficient manner..
66.	Ryohei Sato, Koichi Kakimoto, Wataru Saito, Shin Ichi Nishizawa, Dislocation Propagation in Si 300 mm Wafer during High Thermal Budget Process and Its Optimization, 32nd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2020 Proceedings of the 2020 32nd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2020, 10.1109/ISPSD46842.2020.9170035, 2020-September, 494-497, 2020.09, [URL], This paper shows a new process guideline of high thermal budget process with Si 300 mm wafer in order to eliminate the dislocations. In the case of IGBT, high thermal budget process such as oxidation, diffusion, etc., cause large stress in wafer, and make dislocation propagation, slip, then degrade the device performance and yield. This degradation is enhanced with increasing wafer diameter, and becomes more serious for 300 mm process than that of 200 mm. We clarify the relation between the process condition (time-temperature profile) and dislocation behavior quantitatively under high thermal budget process, and propose the guideline to optimize the process condition. The optimized process minimizes the dislocation propagation in 300 mm Si wafer as same as that in 200 mm Si wafer with the conventional process condition..
67.	Peng Luo, Sankara Narayanan Ekkanath Madathil, Shin Ichi Nishizawa, Wataru Saito, Dynamic Avalanche Free Super Junction-TCIGBT for High Power Density Operation, 32nd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2020 Proceedings of the 2020 32nd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2020, 10.1109/ISPSD46842.2020.9170129, 2020-September, 470-473, 2020.09, [URL], Dynamic Avalanche (DA) effects in the Super-Junction Trench IGBTs are analyzed through 3-D TCAD simulations for the first time. A DA free solution for high power density and low loss is proposed and demonstrated in detail. Furthermore, simulation results show that DA results in significant increase in turn-off losses in the Super-Junction Trench IGBTs at high current density operations, which poses a fundamental limit on the power density of IGBT applications. In contrast, the Super-Junction Trench Clustered IGBTs remain DA free at high current density and show low switching losses due to enhanced PMOS action. Therefore, the Super-Junction Trench IGBTs are well suitable for high power density operations with a potential to operate beyond the 1-D unipolar 4H-SiC limit..
68.	Wataru Saito, Shin Ichi Nishizawa, High Switching Controllability Trench Gate Design in Si-IGBTs, 32nd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2020 Proceedings of the 2020 32nd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2020, 10.1109/ISPSD46842.2020.9170118, 2020-September, 447-450, 2020.09, [URL], A new trench gate design in Si-IGBTs is proposed and analyzed for high controllability of turn-off dV/dt and turn-on dI/dt with low loss operation. Power electronics systems require not only low power loss but also low EMI noise for high cost performance by system downsizing. Although turn-off loss $E _{off}$ and on-state voltage drop $V _ce(sat)$trade-off of IGBT can be improved by enhancement of Injection Enhancement (IE) effect, $E _off$ is limited by dynamic avalanche at low external gate resistance $R_{g}$ condition. In addition, EMI noise is induced by negative gate capacitance at the turn-on switching due to high dI/dt and large surge current $I_{surge}$. Therefore, the system designers require good switching controllability by $R_{g}$ to adjust the power loss and EMI noise trade-off for the optimum system design. This paper shows the dynamic avalanche and negative gate capacitance can be suppressed by management of electric field concentration and hole current flow around the trench gate by proposed Alternated Trench (AT) structure and both good switching controllability and low power loss can be obtained..
69.	N. Shigyo, M. Watanabe, K. Kakushima, T. Hoshii, K. Furukawa, A. Nakajima, K. Satoh, T. Matsudai, T. Saraya, T. Takakura, K. Itou, M. Fukui, S. Suzuki, K. Takeuchi, I. Muneta, H. Wakabayashi, S. Nishizawa, K. Tsutsui, T. Hiramoto, H. Ohashi, H. Iwai, Modeling and simulation of Si IGBTs, International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, 10.23919/SISPAD49475.2020.9241627, 2020-September, 129-132, 2020.09, Technology CAD (TCAD) has been recognized as a powerful design tool for Si insulated gate bipolar transistors (IGBTs). Here, physical models, such as a mobility model for carrier-carrier scattering, were investigated for a predictive TCAD. Simulated currentvoltage characteristics of the trench-gate IGBTs were compared with measurements. The difference between 3D- and 2D-TCAD simulations was observed in a high current region, which was explained by a bias-dependent current flow. A test element group (TEG) for separation of the emitter currents for holes and electrons was also determined as effective for calibration of lifetime model parameters..
70.	Peng Luo, Sankara Narayanan Ekkanath Madathil, Shin-Ichi Nishizawa, Wataru Saito, Evaluation of Dynamic Avalanche Performance in 1.2-kV MOS-Bipolar Devices, IEEE Transactions on Electron Devices, 10.1109/TED.2020.3007594, 67, 9, 3691-3697, 2020.09.
71.	Wataru Saito, Shin-ichi Nishizawa, Alternated Trench-Gate IGBT for Low Loss and Suppressing Negative Gate Capacitance, IEEE Transactions on Electron Devices, 10.1109/TED.2020.3002510, 67, 8, 3285-3290, 2020.08, [URL], A new gate structure in the trench-gate insulated-gate bipolar transistor (IGBT) design is proposed and analyzed for power-loss reduction and the suppression of electromagnetic-interference (EMI) noise. Although the turn-off loss and the ON-state voltage drop {V}_{ ext {ce(sat) } } are improved by the injection-enhancement (IE) effect, the IE effect caused dynamic avalanche that limits the turn-off loss reduction. In addition, EMI noise is induced by high dI/dt and large surge current due to the negative gate capacitance. This article shows that the dynamic avalanche and the negative gate capacitance can be suppressed by the management of the electric field concentration and hole current flow around the trench gate by the proposed alternated trench-gate (AT) IGBT structure, and both low power loss and good switching controllability can be obtained. The device simulation results show that the AT-IGBT improves the turn-on surge current {I}_{ ext {surge } } - {V}_{ ext {ce(sat) } } tradeoff compared with the conventional IGBTs..
72.	Wataru Saito, Shin-ichi Nishizawa, Surface Buffer IGBT for High Total Performance, IEEE Transactions on Electron Devices, 10.1109/TED.2020.2999874, 67, 8, 3263-3269, 2020.08, [URL], A new structure in trench-gate insulated gate bipolar transistor (IGBT) design is proposed and analyzed not only for power loss reduction but also for long-term stability and suppressing electromagnetic interference (EMI) noise using a device simulation. Although turn-off loss and ON-state voltage drop {V}_{ ext {ce(sat) } } are improved by injection enhancement (IE) effect, IE effect causes dynamic avalanche that limits turn-off loss reduction and degrades long-term stability by the charge trap at the trench gate oxide interface. In addition, hole current around the gate induces EMI noise due to the negative gate capacitance. This article shows that the proposed surface buffer (SB) IGBT suppresses dynamic avalanche and negative gate capacitance maintaining low power loss by covering the trench gate bottom and hole evacuation from the pMOS channel..
73.	Wataru Saito, Shin-Ichi Nishizawa, Alternated Trench-Gate IGBT for Low Loss and Suppressing Negative Gate Capacitance, IEEE Transactions on Electron Devices, 10.1109/TED.2020.3002510, 67, 8, 3285-3290, 2020.08, A new gate structure in the trench-gate insulated-gate bipolar transistor (IGBT) design is proposed and analyzed for power-loss reduction and the suppression of electromagnetic-interference (EMI) noise. Although the turn-off loss and the ON-state voltage drop V-ce(sat) are improved by the injection-enhancement (IE) effect, the IE effect caused dynamic avalanche that limits the turn-off loss reduction. In addition, EMI noise is induced by high dI/dt and large surge current due to the negative gate capacitance. This article shows that the dynamic avalanche and the negative gate capacitance can be suppressed by the management of the electric field concentration and hole current flow around the trench gate by the proposed alternated trench-gate (AT) IGBT structure, and both low power loss and good switching controllability can be obtained. The device simulation results show that the AT-IGBT improves the turn-on surge current I-surge - V-ce(sat) tradeoff compared with the conventional IGBTs..
74.	Wataru Saito, Shin-Ichi Nishizawa, Surface Buffer IGBT for High Total Performance, IEEE Transactions on Electron Devices, 10.1109/TED.2020.2999874, 67, 8, 3263-3269, 2020.08, A new structure in trench-gate insulated gate bipolar transistor (IGBT) design is proposed and analyzed not only for power loss reduction but also for long-termstability and suppressing electromagnetic interference (EMI) noise using a device simulation. Although turn-off loss and ON-state voltage drop V-ce(sat) are improved by injection enhancement(IE) effect, IE effect causes dynamic avalanche that limits turn-off loss reduction and degrades long-term stability by the charge trap at the trench gate oxide interface. In addition, hole current around the gate induces EMI noise due to the negative gate capacitance. This article shows that the proposed surface buffer (SB) IGBT suppresses dynamic avalanche and negative gate capacitance maintaining low power loss by covering the trench gate bottom and hole evacuation from the pMOS channel..
75.	Wataru Saito, Shin-ichi Nishizawa, Assist Gate MOSFETs for Improvement of On-Resistance and Turn-Off Loss Trade-Off, IEEE Electron Device Letters, 10.1109/LED.2020.2991927, 41, 7, 1060-1062, 2020.07, [URL], Assist Gate (AG) MOSFET is proposed for low power loss operation of low-voltage power MOSFETs by a new structure with the optimum gate control. The second channel and accumulation layer reduce the channel and drift resistances. In addition, the gate control of AG-MOSFET decreases turn-off loss. 40 and 100 V-class AG-MOSFET characteristics were analyzed using TCAD simulation. The AG-MOSFET improves on-resistance and turn-off loss trade-off. The simulation results show 34% lower on-resistance with 16% lower turn-off loss for 40 V-class device and 21% lower on-resistance with 10% lower turn-off loss for 100 V-class device..
76.	Katsumi Nakamura, Ze Chen, Shin ichi Nishizawa, Akihiko Furukawa, CSTBT™ technology for high voltage applications with high dynamic robustness and low overall loss, Microelectronics Reliability, 10.1016/j.microrel.2020.113635, 110, 2020.07, [URL], This paper discusses the edge termination design of high-voltage insulated gate bipolar transistors with large current turn-off switching operation. We discovered that the phenomena of current crowding and impact ionization act as separated heat sources and induce one local hot spot that causes thermal destruction in the edge termination during the turn-off switching period. Optimizing the backside hole injection efficiency and relaxing the electric field of the surface pn junction edge at the edge termination region prevent the above problems. These concepts benefit the dynamic ruggedness under hard-switching conditions. This paper presents our novel edge termination design that achieves robust turn-off capability without deteriorating other performances of the device..
77.	Taichi Ogawa, Wataru Saito, Shin-ichi Nishizawa, On-Resistance Limit Estimation of 100 V-class Field-Plate Trench Power MOSFETs Optimized Oxide Thickness, IEEE Electron Device Letters, 10.1109/LED.2020.3000239, 41, 7, 1063-1065, 2020.07, [URL], The on-resistance limit of 100 V-class Field-Plate (FP) trench power MOSFETs was analyzed by TCAD simulation. In the previous works, the lateral pitch narrowing effect to reduce the on-resistance has been studied from the viewpoint of charge compensate concept. This work focused on optimization of FP oxide thickness, which affects both the breakdown voltage and the stress induced electron mobility enhancement. The simulation results show that thin oxide structure is desired for low on-resistance design due to lateral pitch narrowing, although thick oxide enhances the increase of the electron mobility. However, the on-resistance reduction by lateral pitch narrowing is limited by increase of the drift layer thickness for maintain the breakdown voltage. As a limit value, the on-resistance of 24.7mOmm² at the breakdown voltage of 114 V was estimated and corresponds to 13%-24% improvement of Figure-of-Merit, which is V_B^2.5/R_on, compared with the previous works of two step and multiple step oxide structures..
78.	Taichi Ogawa, Wataru Saito, Shin-Ichi Nishizawa, On-Resistance Limit Estimation of 100 V-class Field-Plate Trench Power MOSFETs Optimized Oxide Thickness, IEEE Electron Device Letters, 10.1109/LED.2020.3000239, 41, 7, 1063-1065, 2020.07.
79.	Peng Luo, Sankara Narayanan Ekkanath Madathil, Shin-ichi Nishizawa, Wataru Saito, High dV/dt Controllability of 1.2kV Si-TCIGBT for High Flexibility Design with Ultra-low Loss Operation, 2020 IEEE Applied Power Electronics Conference and Exposition (APEC), 10.1109/APEC39645.2020.9124293, 2020-March, 686-689, 2020.06, High dV/dt controllability of IGBT is an important factor for flexible design as well as low switching loss in power electronics systems. However, Dynamic Avalanche (DA) phenomenon poses a fundamental limit on their dV/dt control range, operating current density, turn-off power loss as well as reliability. Overcoming this phenomenon is essential to ensure their safe operation and high robustness in emerging electric transport. In this work, detailed analysis of 1.2 kV trench gated IGBTs is undertaken through experiments and calibrated TCAD 3-dimensional simulations to show the fundamental cause of the low dV/dt controllability of conventional IGBTs and a method to achieve DA free design by Trench Clustered IGBT (TCIGBT). The potential of TCIGBT for ultra-high current density operation with high dV/dt controllability is also presented..
80.	Katsumi Nakamura, Shin Ichi Nishizawa, Akihiko Furukawa, N-Buffer Design for Silicon-Based Power Diode Targeting High Dynamic Robustness and High Operating Temperature over 448 K, IEEE Transactions on Electron Devices, 10.1109/TED.2020.2990387, 67, 6, 2437-2444, 2020.06, [URL], In this article, we investigated the destructive behavior of the latest power diode when operating a hard-switching process. From the numerical simulation analysis, the destruction behavior originates in the enhanced impact ionization at the p-n junction on the anode side and current filament in the active region. A relaxing electric field on the anode side and a moderated electric field on the cathode side prevent the above-mentioned behavior. These improvements result from controlling the carrier-plasma layer in the n-buffer layer on the cathode side. This article demonstrates the effective n-buffer technology for the power diode that achieves superior dynamic robustness and high operating temperature over 448 K..
81.	Katsumi Nakamura, Shin-Ichi Nishizawa, Akihiko Furukawa, N-Buffer Design for Silicon-Based Power Diode Targeting High Dynamic Robustness and High Operating Temperature Over 448 K, IEEE Transactions on Electron Devices, 10.1109/TED.2020.2990387, 67, 6, 2437-2444, 2020.06.
82.	Kiyoshi Takeuchi, Munetoshi Fukui, Takuya Saraya, Kazuo Itou, Toshihiko Takakura, Shinichi Suzuki, Yohichiroh Numasawa, Naoyuki Shigyo, Kuniyuki Kakushima, Takuya Hoshii, Kazuyoshi Furukawa, Masahiro Watanabe, Hitoshi Wakabayashi, Kazuo Tsutsui, Hiroshi Iwai, Atsushi Ogura, Wataru Saito, Shin Ichi Nishizawa, Masanori Tsukuda, Ichiro Omura, Hiromichi Ohashi, Toshiro Hiramoto, Bipolar Transistor Test Structures for Extracting Minority Carrier Lifetime in IGBTs, IEEE Transactions on Semiconductor Manufacturing, 10.1109/TSM.2020.2972369, 33, 2, 159-165, 2020.05, [URL], Vertical PNP bipolar transistor test structures were fabricated and measured, attempting to electrically obtain information on carrier lifetime in the voltage-supporting base region of Insulated Gate Bipolar Transistors (IGBTs). Owing to the structural similarity, the test structures and functional IGBTs can be integrated on the same wafers, making it possible to directly correlate lifetime data and IGBT characteristics. To solve a problem of leaky backside PN junction, common base current gain of the test devices was measured without applying a reverse bias between the collector and base terminals, which suppressed the leakage to an acceptable level. A simple analytical formula to convert the current gain to hole lifetime in the N-type base region was proposed and used, that takes into account the existence of a commonly used N-buffer layer adjacent to the backside P-collector layer. The validity of the formula was confirmed using TCAD simulations. This method was applied to IGBT wafers with two different wafer thicknesses (i.e., base lengths): 120~{ { mu } }text{m} and 360~{ { mu } }text{m}. Consistent lifetime values extracted in spite of the largely different thicknesses supports the validity of the proposed lifetime estimation method..
83.	Jeffrey J. Derby, Koichi Kakimoto, Shin ichi Nishizawa, Editorial, Journal of Crystal Growth, 10.1016/j.jcrysgro.2020.125594, 538, 2020.05, [URL].
84.	Takuya Saraya, Kazuo Itou, Toshihiko Takakura, Munetoshi Fukui, Shinichi Suzuki, Kiyoshi Takeuchi, Kuniyuki Kakushima, Takuya Hoshii, Kazuo Tsutsui, Hiroshi Iwai, Shin Ichi Nishizawa, Ichiro Omura, Toshiro Hiramoto, Impact of structural parameter scaling on on-state voltage in 1200 v scaled IGBTs, Japanese Journal of Applied Physics, 10.35848/1347-4065/ab7414, 59, SG, 2020.04, [URL], In this work, effects of structural parameter scaling on IGBT performance were systematically studied for both 1200 V non-scaled (k = 1) and scaled (k = 3) IGBTs. Relatively small area IGBT test devices with varied device parameters were fabricated on 3 inch wafers simultaneously with full size IGBTs. Mesa width, trench depth, p-base depth (MOS channel length) and gate oxide thickness were varied to clarify the contribution of each scaling parameter. P-collector dose was also varied for both k = 1 and k = 3 IGBTs to control the on-sate voltage. Clear on-state voltage improvement was verified in scaled IGBTs, in agreement with TCAD simulations. The origin of the performance improvement and the possibility of further improvement by scaling are discussed..
85.	Mitsuhiko Sagara, Keiji Wada, Shin-ichi Nishizawa, Evaluation of SiC-MOSFET by repetitive UIS tests for solid state circuit breaker, International Conference on Silicon Carbide and Related Materials 2019, 10.4028/www.scientific.net/MSF.1004.1010, 1004 MSF, 1010-1015, 2020.03, This paper investigates a degradation of SiC power device for DC circuit breaker through repetitive unclamped inductive switching (UIS) tests. Being lower ONresistance compared with Si devices, it has been considered an application for DC circuit breakers using SiC semiconductor. In order to use for the DC breaker, it is essential to evaluate the destructive endurance for UIS test. This paper evaluates a deterioration phenomenon by paying attention to the decrease of the gate voltage of the SiCMOSFETs under the degradation at repetitive UIS test..
86.	Xin Liu, Hirofumi Harada, Yoshiji Miyamura, Xue feng Han, Satoshi Nakano, Shin ichi Nishizawa, Koichi Kakimoto, Transient global modeling for the pulling process of Czochralski silicon crystal growth. II. Investigation on segregation of oxygen and carbon, Journal of Crystal Growth, 10.1016/j.jcrysgro.2019.125404, 532, 2020.02, [URL], We conducted the transient global simulations for the crystal pulling process of Czochralski silicon (CZ-Si) growth with the cusp-shaped magnetic field (CMF). The generation, transport, and segregation of oxygen (O) were considered for the crystal growing process. Further, the incorporation, accumulation, and segregation of carbon (C) were also predicted based on our previous studies on CZ-Si growth. The distributions of O and C at the growth interface were dynamically predicted for the diameter pulling stages, and their segregations were plotted as a function of solidified fraction and crystal length. The O level and uniformities at the growth interface exhibit a strong correlation with the depth of melt in the crucible and the flow structures inside the melt. The comparisons of different CMFs indicated that adjustments of the zero-Gauss plane (ZGP) have the potential to optimize the O segregation into the pulling crystal from the level, axial, and radial uniformities. Further, the C concentration increased with the increase in the crystal length because of the continuous contamination and the lower segregation coefficient. Hence, the developed dynamic global model also has applications in the segregation prediction of other dopants and impurities in the CZ-Si growing process..
87.	Xin Liu, Hirofumi Harada, Yoshiji Miyamura, Xue feng Han, Satoshi Nakano, Shin ichi Nishizawa, Koichi Kakimoto, Transient global modeling for the pulling process of Czochralski silicon crystal growth. I. Principles, formulation, and implementation of the model, Journal of Crystal Growth, 10.1016/j.jcrysgro.2019.125405, 532, 2020.02, [URL], A transient global model for the crystal pulling process was developed for magnetic-field-applied Czochralski silicon (CZ-Si) growth. Heat transfer by solid conduction, melt convection, and diffuse gray radiation is taken into account for the crystal, melt, and other components in the furnace. The mesh adaption and view factor updating for the dynamic pulling process were realized by the structured grid deformations for different domains. By imposing the thermal boundary conditions in the vicinity of the triple point, the inverse control by the virtual proportional integral derivative controller and heat flux is acceptable for the transient global simulation of the pulling process in CZ-Si crystal growth. The applied cusp-shaped magnetic field (CMF) suppressed the turbulent melt flow and stabilized the heat and mass transport. CMF with different zero-Gauss-plane locations resulted in different flow patterns, which could affect the impurity transport during the pulling process. This developed transient global model can be applied for the segregation predictions of impurities (oxygen and carbon) and dopants in the CZ-Si growing process..
88.	Peng Luo, Sankara Narayanan Ekkanath Madathil, Shin Ichi Nishizawa, Wataru Saito, Dynamic Avalanche Free Design in 1.2kV Si-IGBTs for Ultra High Current Density Operation, 65th Annual IEEE International Electron Devices Meeting, IEDM 2019, 10.1109/IEDM19573.2019.8993596, 2019-December, 2019.12, [URL], Dynamic Avalanche (DA) phenomenon poses a fundamental limit on the operating current density, turn-off power loss as well as reliability of MOS-bipolar devices. Overcoming this phenomenon is essential to ensure their safe operation in emerging electric transport. In this work, detailed analysis of 1.2 kV trench gated IGBTs are undertaken through experiments and calibrated TCAD simulations to show the fundamental cause of the DA as well as a method to achieve DA free design for ultra-high current density operation and reliability in 1.2 kV Si-IGBTs..
89.	Katsumi Nakamura, Fumihito Masuoka, Akito Nishii, Shin Ichi Nishizawa, Akihiko Furukawa, Freewheeling Diode Technology with Low Loss and High Dynamic Ruggedness in High-Speed IGBT Applications, IEEE Transactions on Electron Devices, 10.1109/TED.2019.2941710, 66, 11, 4842-4849, 2019.11, [URL], In this article, we investigated two typical destruction modes during reverse recovery in power diodes. These phenomena originated, while using numerical simulation analysis, in snap-off behavior and local heating during the recovery period in modern high-frequency power application. A relaxing electric field and optimizing electron injection efficiency at the cathode region prevent the above behavior. These improvements are the result of controlling the carrier plasma layer and its interaction with the electric field in the drift region during the recovery process. This article demonstrates the effective diode technology that achieves superior dynamic ruggedness with low overall loss..
90.	T. Hiramoto, K. Satoh, T. Matsudai, W. Saito, K. Kakushima, T. Hoshii, K. Furukawa, M. Watanabe, N. Shigyo, H. Wakabayashi, K. Tsutsui, T. Sarava, H. Iwai, A. Ogura, S. Nishizawa, I. Omura, H. Ohash, K. Itou, T. Takakura, M. Fukui, S. Suzuki, K. Takeuchi, M. Tsukuda, Y. Numasawa, Switching of 3300v scaled igbt by 5v gate drive, 13th IEEE International Conference on ASIC, ASICON 2019, 10.1109/ASICON47005.2019.8983633, 2019.10, [URL], In this work, the switching of 3300V IGBTs by 5V gate drive voltage has been successfully demonstrated for the first time. IGBT was designed based on a scaling principle. Comparing with conventional 15V-driven non-scaled IGBTs, the tum-off tail current of the scaled devices significantly decreased. The improvement of E-{mathrm{off } } vs V-{mathrm{cesat } } relationship by 35% was achieved..
91.	Mitsuhiko Sagara, Keiji Wada, Shin ichi Nishizawa, Degradation characteristics of SiC power devices for DC circuit breaker by repetitive unclamped inductive switching test, Microelectronics Reliability, 10.1016/j.microrel.2019.113417, 100-101, 2019.09, [URL], This paper investigates the degradation of SiC power devices for DC circuit breaker through repetitive unclamped inductive switching (UIS) tests. The ON resistance of SiC power devices such as MOSFET and JFET are lower compared with Si devices. Therefore, SiC power devices are suitable for use as DC circuit breakers. Several papers have discussed degradation of SiC power devices; however, few studies have determined a suitable power device for a DC breaker from a degradation standpoint. In this paper, four types of SiC devices were subjected to repetitive UIS tests. Our research demonstrated SiC-JFET to be suitable for a DC breaker..
92.	Shinichi Nishizawa, F.Mercier, Effect of nitrogen and aluminium on silicon carbide polytype stability, Journal of Crystal Growth, 10.1016/j.jcrysgro.2019.04.018, 518, 99-102, 2019.07, [URL], In this study, effects of nitrogen and aluminium dopant on the SiC crystal structure and polytype stability were investigated by density functional theory. With taking account of the stacking energy of additional bilayer, the carbon terminated surface as seed surface with nitrogen doped condition is the only condition of 4H single polytype SiC growth. Under the other conditions, polytype conversion and inclusion might occurre..
93.	Takuya Hoshii, Akira Nakajima, Shin-ichi Nishizawa, Hiromichi Ohashi, Kuniyuki Kakushima, Hitoshi Wakabayashi, Kazuo Tsutsui, Analysis of back-gate effect on threshold voltage of p-channel GaN MOSFETs on polarization-junction substrates, Japanese Journal of Applied Physics, 10.7567/1347-4065/ab1c78, 58, 6, 061006-061006, 061006, 2019.06, [URL], GaN-based p-channel devices using a two-dimensional hole gas are of interest for the realization of GaN CMOS circuits, and threshold voltage control using a back-gate is useful for the circuit design of these devices. In this paper, the back-gate effect on p-channel GaN MOSFETs on polarization-junction substrates is studied. The results show that the obtained dependence of the threshold voltage on the back-gate voltage can be derived by a model equation considering the back surface channel. Also, by comparing the measured characteristics with the simulation result under ideal conditions, it is found that the amount of interfacial charges can be quantitatively evaluated for the fabricated device. (C) 2019 The Japan Society of Applied Physics.
94.	Kazunori Hasegawa, Shinichi Nishizawa, Ichiro Omura, A Condition-Monitoring Method of DC-Link Capacitors Used in a High-Power Three-Phase PWM Inverter with an Evaluation Circuit, IEEJ Journal of Industry Applications, 10.1541/ieejjia.8.480, 8, 3, 480-487, 2019.05, [URL], This paper presents a condition-monitoring method of dc-link capacitors used in a high-power three-phase PWM inverter with an evaluation circuit intended for ageing tests. Although its power rating is 1/25 of the inverter, the evaluation circuit provides the equivalent ripple current waveform and dc-bias voltage to the high-power inverter. The monitoring method independently extracts the capacitance and ESR of the dc-link capacitor, where the fast Fourier transform is introduced to the ripple current waveform and the dc-link voltage of the evaluation circuit. Experimental results verify that the monitoring method obtains both the ESR and capacitance changes of a capacitor under test..
95.	Takuya Saraya, Kazuo Itou, Toshihiko Takakura, Munetoshi Fukui, Shinichi Suzuki, Kiyoshi Takeuchi, Masanori Tsukuda, Yohichiroh Numasawa, Katsumi Satoh, Tomoko Matsudai, Wataru Saito, Kuniyuki Kakushima, Takuya Hoshii, Kazuyoshi Furukawa, Masahiro Watanabe, Naoyuki Shigyo, Hitoshi Wakabayashi, Kazuo Tsutsui, Hiroshi Iwai, Atsushi Ogura, Shin-Ichi Nishizawa, Ichiro Omura, Hiromichi Ohashi, Toshiro Hiramoto, 3300V Scaled IGBTs Driven by 5V Gate Voltage, 2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD), 10.1109/ispsd.2019.8757626, 43-46, 2019.05, [URL], In this work, 5V gate drive 3300V IGBTs, designed based on a scaling principle, have been demonstrated. Turn-off characteristics without noticeable degradation in the gate voltage waveforms were confirmed. Turn-off tail current of the scaled devices significantly decreased than conventional 15V-driven devices. As a result of both Vce and turn-off loss reduction, 35% improvement in Eoff vs Vcesat relationship was achieved..
96.	Masahiro Watanabe, Naoyuki Shigyo, Takuya Hoshii, Kazuyoshi Furukawa, Kuniyuki Kakushima, Katsumi Satoh, Tomoko Matsudai, Takuya Saraya, Toshihiro Takakura, Kazuo Itou, Munetoshi Fukui, Shinichi Suzuki, Kiyoshi Takeuchi, Iriya Muneta, Hitoshi Wakabayashi, Akira Nakajima, Shin-Ichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, Hiromichi Ohashi, Hiroshi Iwai, Impact of three-dimensional current flow on accurate TCAD simulation for trench-gate IGBTs, 2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD), 10.1109/ispsd.2019.8757640, 311-314, 2019.05, [URL], TCAD simulation has been recognized as a powerful design tool for insulated gate bipolar transistors (IGBTs). In this work, excellent agreement between 3D TCAD simulations and experimental current-voltage characteristics were obtained in the up to 1000 A/cm(2) region for IGBTs with scaled trench-gates. The results of 2D and 3D simulations are compared to discuss the difference in current-voltage characteristics and their physical origins. A method to evaluate the saturation current (J(Csat)) using a 2D simulation is also presented with an appropriate correction..
97.	Kobayashi, Hiroto, Yokogawa, Ryo, Kinoshita, Kosuke, Numasawa, Yohichiroh, Ogura, Atsushi, Nishizawa, Shin-ichi, Saraya, Takuya, Ito, Kazuo, Takakura, Toshihiko, Suzuki, Shin-ichi, Fukui, Munetoshi, Takeuchi, Kiyoshi, Hiramoto, Toshiro, Evaluations of minority carrier lifetime in floating zone Si affected by Si insulated gate bipolar transistor processes, JAPANESE JOURNAL OF APPLIED PHYSICS, 10.7567/1347-4065/aafd90, 58, 2019.04, [URL], This study evaluates minority carrier lifetime in floating zone Si affected by advanced and conventional Si IGBT (insulated gate bipolar transistor) processes. Si gate oxidations reduce lifetime due to the formation of interface states between the Si and the oxide. As a result, cross-sectional photoluminescence imaging shows that the lifetime around a trench is lower than that in the bulk region. The high temperature thermal treatment for B-base/P-emitter layer activation after gate oxidation improved the interface, thus resulting in the recovery of the lifetime. TEM observations reveal that the (110) trench surface shows irregular contrast while the (100) surface shows relatively smooth contrast, which is consistent with the lifetime result of "trench side wall surface (100)" > "trench side wall surface (110)." Our study conclusively clarifies that lifetime is correlated with the SiO2 surface state. (C) 2019 The Japan Society of Applied Physics.
98.	Kobayashi, Hiroto, Yokogawa, Ryo, Kinoshita, Kosuke, Numasawa, Yohichiroh, Ogura, Atsushi, Nishizawa, Shin-ichi, Saraya, Takuya, Ito, Kazuo, Takakura, Toshihiko, Suzuki, Shin-ichi, Fukui, Munetoshi, Takeuchi, Kiyoshi, Hiramoto, Toshiro, Evaluations of minority carrier lifetime in floating zone Si affected by Si insulated gate bipolar transistor processes, JAPANESE JOURNAL OF APPLIED PHYSICS, 10.7567/1347-4065/aafd90, 58, 2019.04, This study evaluates minority carrier lifetime in floating zone Si affected by advanced and conventional Si IGBT (insulated gate bipolar transistor) processes. Si gate oxidations reduce lifetime due to the formation of interface states between the Si and the oxide. As a result, cross-sectional photoluminescence imaging shows that the lifetime around a trench is lower than that in the bulk region. The high temperature thermal treatment for B-base/P-emitter layer activation after gate oxidation improved the interface, thus resulting in the recovery of the lifetime. TEM observations reveal that the (110) trench surface shows irregular contrast while the (100) surface shows relatively smooth contrast, which is consistent with the lifetime result of "trench side wall surface (100)" > "trench side wall surface (110)." Our study conclusively clarifies that lifetime is correlated with the SiO2 surface state. (C) 2019 The Japan Society of Applied Physics.
99.	K. Takeuchi, M. Fukui, T. Saraya, K. Itou, T. Takakura, S. Suzuki, Y. Numasawa, K. Kakushima, T. Hoshii, K. Furukawa, M. Watanabe, N. Shigyo, H. Wakabayashi, M. Tsukuda, A. Ogura, K. Tsutsui, H. Iwai, Shinichi Nishizawa, I. Omura, H. Ohashi, T. Hiramoto, Vertical bipolar transistor test structure for measuring minority carrier lifetime in IGBTs, 32nd IEEE International Conference on Microelectronic Test Structures, ICMTS 2019 2019 IEEE 32nd International Conference on Microelectronic Test Structures, ICMTS 2019, 10.1109/ICMTS.2019.8730922, 98-101, 2019.03, [URL], Vertical PNP bipolar transistor test structures were fabricated, which can be integrated on the same wafer with functional IGBTs. Common-base current gain was measured by applying zero voltage to the leaky back side junction, from which minority carrier lifetime in the base region was extracted. The structure makes it possible to measure the lifetime after a real IGBT fabrication process flow, and to correlate it with the characteristics of IGBTs on the same wafer..
100.	Y. Miyamura, H. Harada, X. Liu, S. Nakano, Shinichi Nishizawa, Koichi Kakimoto, In-situ measurement of CO gas concentration in a Czochralski furnace of silicon crystals, Journal of Crystal Growth, 10.1016/j.jcrysgro.2018.11.017, 507, 154-156, 2019.02, [URL], Power devices with high-performance require long carrier lifetimes within their silicon crystals. This paper reports the in-situ measurement of carbon monoxide in a Czochralski growth furnace of silicon single crystals. Moreover, this paper reports analytical investigation on contamination to silicon melt as functions of pressure in the furnace, argon gas flow velocity and gap width between the melt and a thermal shield. The experimental results show the carbon contamination to the melt increases when the pressure increases and the flow rate decreases. Increase of the gap width increases the contamination of carbon. We could explain the results qualitatively using a simple transport model..
101.	T. Saraya, K. Itou, T. Takakura, M. Fukui, S. Suzuki, K. Takeuchi, M. Tsukuda, Y. Numasawa, K. Satoh, T. Matsudai, W. Saito, K. Kakushima, T. Hoshii, K. Furukawa, M. Watanabe, N. Shigyo, K. Tsutsui, H. Iwai, A. Ogura, Shinichi Nishizawa, I. Omura, H. Ohashi, T. Hiramoto, Demonstration of 1200V Scaled IGBTs Driven by 5V Gate Voltage with Superiorly Low Switching Loss, 64th Annual IEEE International Electron Devices Meeting, IEDM 2018 2018 IEEE International Electron Devices Meeting, IEDM 2018, 10.1109/IEDM.2018.8614491, 8.4.1-8.4.4, 2019.01, [URL], Functional trench-gated 1200V-10A class Si-IGBTs, designed based on a three dimensional (3D) scaling concept, were fabricated, and 5V gate voltage switching operation has been demonstrated for the first time. 33% reduction of turn-off loss and 100mV improvement of on-state voltage were achieved, while keeping 1.2kV forward blocking voltage..
102.	Nobuyuki Shishido, Masanori Tsukuda, Shin Ichi Nishizawa, Trend in thermal resistance of advanced power modules, International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, PCIM Europe 2019, 104-108, 2019.01, Thermal management is essential to reliable design of power modules. In this report, a trend in the thermal resistance of power modules was examined by reviewing the current cooling technologies. The thermal resistance of power modules has decreased to approximately 1/3x in 10 years. Our numerical simulation about cooling suggests that a straightforward development in liquid cooling technology can achieve the update corresponds to the expected change in next 5 year when it keeps this trend in next decades. However, further progress in thermal resistance shall require higher thermal-conductive materials for spreader and two-phase cooling technologies..
103.	K. Kakushima, T. Hoshii, M. Watanabe, N. Shizyo, K. Furukawa, T. Saraya, T. Takakura, K. Itou, M. Fukui, S. Suzuki, K. Takeuchi, I. Muneta, H. Wakabayashi, Y. Numasawa, A. Ogura, Shinichi Nishizawa, K. Tsutsui, T. Hiramoto, H. Ohashi, H. Iwai, New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment, 32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018, 10.1109/VLSIC.2018.8502399, 105-106, 2018.10, [URL], A new methodology to evaluate the process temperature dependence of the minority carrier lifetime has been developed. A TEG layout with p+-stripes on an n-Si substrate was designed. When all the p+n junctions are made forward, the minority carrier diffusion current flows one dimensionally into the substrate. On the other hand, for making only the one center p+n junction forward, the current spreads laterally and flows cylindrically into the substrate. By the difference in the flow path of the minority carrier diffusion, we can successfully extract the minority carrier lifetime. We applied this methodology to the evaluation of the minority carrier lifetime depending on process temperatures and confirmed the lifetime degradation for high temperature process..
104.	Xin Liu, Hirofumi Harada, Yoshiji Miyamura, Xue feng Han, Satoshi Nakano, Shinichi Nishizawa, Koichi Kakimoto, Numerical analyses and experimental validations on transport and control of carbon in Czochralski silicon crystal growth, Journal of Crystal Growth, 10.1016/j.jcrysgro.2018.07.020, 499, 8-12, 2018.10, [URL], Czochralski silicon (CZ-Si) crystal growth is invariably accompanied by the generation and transport of impurities, such as carbon (C) and oxygen (O), from chemical reactions in the high-temperature range. Reduction of C contamination in the grown crystal is required for the production of a high-quality Si wafer. Therefore, we systematically performed the transient global simulations and in situ measurements of CO concentrations in argon (Ar) gas domain. Parametric studies on the furnace pressure, flow rate of argon gas, and gap width were conducted for the transport of CO and accumulation of C during the melting process of Si feedstock. SiO etching reactions on graphite and SiC coating are the major sources of CO production. The contact reaction between the crucible and susceptor is an additional source of CO and SiO. Furthermore, the control mechanisms of gas flow on the incorporation of the generated CO and the accumulation of C in Si feedstock were clarified by comparison of different parameter settings. According to the mechanisms of C transport, the final C content of the melting process depends on the contamination flux at the gas/melt interface which could be controlled by the Péclet number of the gas flow and diffusion distance of CO..
105.	T. Hoshii, K. Furukawa, K. Kakushima, M. Watanabe, N. Shigvo, T. Saraya, T. Takakura, K. Ltou, M. Fukui, S. Suzuki, K. Takeuchi, I. Muneta, H. Wakabayashi, Shinichi Nishizawa, K. Tsutsui, T. Hiramoto, H. Ohashi, H. Lwai, Verification of the injection enhancement effect in IGBTs by measuring the electron and hole currents separately, 48th European Solid-State Device Research Conference, ESSDERC 2018 2018 48th European Solid-State Device Research Conference, ESSDERC 2018, 10.1109/ESSDERC.2018.8486870, 26-29, 2018.10, [URL], The injection enhancement effect in IGBTs was experimentally verified by separately measuring emitter electron-and hole-currents for the first time. Finger contacts were employed as ladder-like periodic n+ and p+ emitters to allow the independent measurement of these currents. Both reducing the mesa width and increasing the cell pitch were found to increase electron injection from the emitter, demonstrating the injection enhancement effect. These experimental results agreed well with the simulation results..
106.	K. Hasegawa, Shinichi Nishizawa, I. Omura, ESR and capacitance monitoring of a dc-link capacitor used in a three-phase PWM inverter with a front-end diode rectifier, Microelectronics Reliability, 10.1016/j.microrel.2018.07.023, 88-90, 433-437, 2018.09, [URL], Condition monitoring plays an important role in estimating health condition of capacitors because the ageing of the capacitors is usually accompanied by an increase in equivalent series resistance (ESR) and a decrease in capacitance. Either capacitance or ESR cannot be a unique indicator of the lifetime of capacitors in some cases. This paper presents a condition monitoring method of a dc-link capacitor used in a three-phase PWM inverter with a front-end diode rectifier intended for motor drives. The monitoring method extracts both the ESR and capacitance of a capacitor under test from the actual ripple current and voltage without disconnecting the capacitor nor injecting an additional current. The monitoring method, therefore, can be implemented online. Experimental results verify that the monitoring method independently obtains the ESR and capacitance changes of the capacitor under test. This contributes to accurate lifetime estimation of dc-link capacitors..
107.	Y. Miyamura, H. Harada, S. Nakano, Shinichi Nishizawa, Koichi Kakimoto, Do thermal donors reduce the lifetimes of Czochralski-grown silicon crystals?, Journal of Crystal Growth, 10.1016/j.jcrysgro.2018.02.034, 489, 1-4, 2018.05, [URL], High-performance electronics require long carrier lifetimes within their silicon crystals. This paper reports the effects of thermal donors on the lifetimes of carriers in as-grown n-type silicon crystals grown by the Czochralski method. We grew silicon crystals with two different concentrations of thermal donors using the following two cooling processes: one was cooled with a 4-h halt after detaching the crystal from the melt, and the other was cooled continuously. The crystal grown with the cooling halt contained higher concentrations of thermal donors of the order of 1 × 10¹³ cm⁻³, while the crystal without the halt had no thermal donors. The measured bulk lifetimes were in the range of 15–18 ms. We concluded that thermal donors in Czochralski-grown silicon crystals do not act to reduce their lifetimes..
108.	Akira Nakajima, Shunsuke Kubota, Kazuo Tsutsui, Kuniyuki Kakushima, Hitoshi Wakabayashi, Hiroshi Iwai, Shinichi Nishizawa, Hiromichi Ohashi, GaN-based complementary metal-oxide- semiconductor inverter with normally off Pch and Nch MOSFETs fabricated using polarisation-induced holes and electron channels, IET Power Electronics, 10.1049/iet-pel.2017.0376, 11, 4, 689-694, 2018.04, [URL], Gallium nitride (GaN)-based P-channel (Pch) and N-channel (Nch) metal-oxide-semiconductor field-effect transistors (MOSFETs) with normally off operations were realised. Both Pch and Nch MOSFETs were monolithically fabricated in a polarisation-junction platform wafer. The platform wafer was constructed with a GaN/aluminium GaN/GaN double heterostructure, which has both two-dimensional hole gas (2DHG) and 2D electron gas (2DEG). The drain currents of Pch and Nch MOSFETs flow through 2DHG and 2DEG, respectively. The threshold gate voltages of the fabricated Pch and Nch MOSFETs were -2.7 and 6.7 V, respectively. It was shown that the threshold voltage and the on-state resistance of the Pch MOSFET can be controlled by adjusting the 2DEG potential. Furthermore, using Pch and Nch MOSFETs, complementary MOS inverter operation was demonstrated..
109.	K. Hasegawa, K. Tsuzaki, Shinichi Nishizawa, DC-bias-voltage dependence of degradation of aluminum electrolytic capacitors, Microelectronics Reliability, 10.1016/j.microrel.2018.02.012, 83, 115-118, 2018.04, [URL], Attention has been paid to reliability-related issues for dc-link capacitors such as monitoring methods, power-loss estimation, and ageing tests. The degradation of the capacitors depends on their operating condition including temperature, ripple current, and dc-bias voltage, which has a strong influence on failures as well. In design stages of power converters, it is desirable to know the relation between the degradation and electrolytic parameters. This paper makes an intensive discussion on the voltage dependence of the degradation of a small aluminum electrolytic capacitor with an ageing test and a leakage-current measurement. The ageing test reveals that a higher dc-bias voltage brings a faster increase in ESR but results in a slower drop in capacitance in a range within the rated voltage. This result implies that either capacitance or ESR cannot be a unique indicator of the lifetime. Attention should be paid both to the ESR and to the capacitance when one monitors the capacitor condition. On the other hand, more than the rated voltage leads a rapid degradation of the capacitor, which can be confirmed by a leakage-current measurement instead of the ageing test..
110.	Y. Miyamura, H. Harada, S. Nakano, Shinichi Nishizawa, Koichi Kakimoto, Relationship between carbon concentration and carrier lifetime in CZ-Si crystals, Journal of Crystal Growth, 10.1016/j.jcrysgro.2018.01.020, 486, 56-59, 2018.03, [URL], This paper aims to clarify the effect of carbon concentration on carrier lifetime in as-grown n-type and non-doped silicon crystals produced via the Czochralski (CZ) method. We grew n-type and non-doped silicon single crystals with 3-in. diameters along with different carbon and phosphorous contents. The resistivity, concentrations of oxygen and carbon, and lifetime were measured using four-point measurements, Fourier-transform infrared spectroscopy, and the eddy current method, respectively. The oxygen concentrations of the crystals were 6–8 × 10¹⁷ atoms/cm³, and the bulk lifetimes ranged from 10 to 20 ms. The carrier lifetime of CZ silicon crystals depended on dopant concentration but had no significant dependence on carbon concentration..
111.	K. Tsutsui, K. Kakushima, T. Hoshii, A. Nakajima, Shinichi Nishizawa, H. Wakabayashi, I. Muneta, K. Sato, T. Matsudai, W. Saito, T. Saraya, K. Itou, M. Fukui, S. Suzuki, M. Kobayashi, T. Takakura, T. Hiramoto, A. Ogura, Y. Numasawa, I. Omura, H. Ohashi, H. Iwai, 3D scaling for insulated gate bipolar transistors (IGBTs) with low V_ce(sat), 12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017 Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017, 10.1109/ASICON.2017.8252681, 2017-October, 1137-1140, 2018.01, [URL], Three dimensionally (3D) scaled IGBTs that have a scaling factor of 3 (k=3) with respect to current commercial products (k=1) were fabricated for the first time. The scaling was applied to the lateral and vertical dimensions as well as the gate voltage. A significant decrease in ON resistance, - V_ce(sat) reduction from 1.70 to 1.26 V - was experimentally confirmed for the 3D scaled IGBTs..
112.	Kazunori Hasegawa, Ichiro Omura, Shinichi Nishizawa, An evaluation circuit for DC-link capacitors used in a single- phase PWM inverter, 2017 International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, PCIM Europe 2017 PCIM Europe 2017 - International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, 10.1109/SBMicro.2017.7990846, 2017.01, [URL], High-power conversion systems are based not only on three-phase inverters but also on singlephase inverters because modular multilevel cascade converters (MMCC) consist of half- or fullbridge single-phase converters. Their DC-link capacitors are a major constraint on the improvement of power density as well as of reliability. Evaluation of dc-link capacitors in terms of power loss, ageing, and failure rate will play an important role in the next-generation power converters. This paper presents an evaluation circuit for dc-link capacitors used in a high-power single-phase PWM inverter. The evaluation circuit produces a practical ripple current waveform and a dc bias voltage into a capacitor under test with a downscaled voltage-rating inverter, which is equivalent to those of the full-scale inverter. Theoretical analysis and experimental results verify the effectiveness of the evaluation circuit..
113.	筒井一生, 角嶋邦之, 星井拓也, 中島昭, 西澤伸一, 若林整, 宗田伊理也, 佐藤克己, 末代知子, 齋藤渉, 更屋拓哉, 伊藤一夫, 福井宗利, 鈴木慎一, 小林正治, 高倉俊彦, 平本俊郎, 小椋厚志, 沼沢陽一郎, 大村一郎, 大橋弘通, 岩井洋, 三次元スケーリングによるIGBTのV_CEsat低減の実験的検証, 電気学会電子デバイス研究会資料, 10.1109/IEDM.2016.7838390, EDD-17, 74-86, 10.6.1-10.6.4, 2017.01, [URL].
114.	K. Hasegawa, K. Kozuma, K. Tsuzaki, I. Omura, Shinichi Nishizawa, Temperature rise measurement for power-loss comparison of an aluminum electrolytic capacitor between sinusoidal and square-wave current injections, Microelectronics and Reliability, 10.1016/j.microrel.2016.07.049, 64, 98-100, 2016.09, [URL], DC-link capacitors are a major factor of degrading reliability of power electric converters because they usually have a shorter lifetime and higher failure rate than those of semiconductor devices or magnetic devices. Characteristics of the capacitors are usually evaluated by a single sinusoidal current waveform. However, actual current flowing out of the converter into the capacitor is a modulated square current waveform. This paper provides experimental comparison of the power loss dissipated in an aluminum electrolytic capacitor between sinusoidal and square-wave current injections. Power loss is estimated by temperature rise of the capacitor. Experimental results confirm that power losses of the square-wave current injection were always lower than those of the sinusoidal current injection by 10–20%. Moreover, the power losses of the square-wave current injection can be estimated by a synthesis of fundamental and harmonic currents based on the Fourier series expansion, which brings a high accuracy less than 1% when more than fifth harmonic current is introduced. This comparison will be useful for estimating power loss and life time of electrolytic capacitors..
115.	Kazunori Hasegawa, Ichiro Omura, Shinichi Nishizawa, A new evaluation circuit with a low-voltage inverter intended for capacitors used in a high-power three-phase inverter, 31st Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2016 2016 IEEE Applied Power Electronics Conference and Exposition, APEC 2016, 10.1109/APEC.2016.7468295, 2016-May, 3032-3037, 2016.05, [URL], DC-link capacitors in power electronic converters are a major constraint on improvement of power density as well as reliability. Evaluation of the dc-link capacitors in terms of power loss, ageing, and failure rate will play an important role in design stages of the next-generation power converters. This paper proposes a new evaluation circuit for dc-link capacitors used in a high-power three-phase inverter, which is intended for testing power loss, failure rate, ageing, and so on. The evaluation circuit produces a practical ripple current waveform and a dc bias voltage into a capacitor under test, in which the ripple current is equivalent to that generated by the three-phase inverter on the dc link. The evaluation circuit employs a full-scale current-rating and downscaled voltage-rating inverter for producing the ripple current, so that the power rating of the evaluation circuit is much smaller than that of a full-scale current rating and full-scale voltage rating inverter..
116.	Hasegawa Kazunori, Omura Ichiro, Nishizawa Shin-ichi, Design and Analysis of a New Evaluation Circuit for Capacitors Used in a High-Power Three-Phase Inverter, IEEE Transactions on Industrial Electronics, 10.1109/TIE.2015.2511097, 63, 5, 2679-2687, 2016.05, [URL], DC-link capacitors in power electronic converters are a major constraint on improvement of power density as well as reliability. Evaluation of the dc-link capacitors in terms of power loss, ageing, and failure rate will play an important role in design stages of the next-generation power converters. This paper proposes a new evaluation circuit for dc-link capacitors used in a high-power three-phase inverter, which is intended for testing power loss, failure rate, ageing, and so on. The evaluation circuit produces a practical ripple current waveform and a dc bias voltage into a capacitor under test, in which the ripple current is equivalent to that generated by the three-phase inverter on the dc link. The evaluation circuit employs a full-scale current-rating and downscaled voltage-rating inverter for producing the ripple current, so that the power rating of the evaluation circuit is much smaller than that of a full-scale current-rating and full-scale voltage-rating inverter. Theoretical analysis and simulated results verify the effectiveness of new evaluation circuit.
117.	S. Araki, B. Gao, Shinichi Nishizawa, S. Nakano, Koichi Kakimoto, Total pressure-controlled PVT SiC growth for polytype stability during using 2D nucleation theory, Crystal Research and Technology, 10.1002/crat.201500344, 51, 5, 344-348, 2016.05, [URL], A total pressure-controlled physical vapor transport growth method that stabilizes SiC polytype is proposed. The supersaturation of carbon during SiC growth changed as a function of the growth time due to changes in the temperature difference between the surfaces of the source and the grown crystal. Supersaturation also varied as a function of the pressure inside the furnace. Therefore, modification of the pressure as a function of growth time allowed for constant supersaturation during growth. The supersaturation was calculated based on classical thermodynamic nucleation theory using data for heat and species of Si₂C and SiC₂ transfer in a furnace obtained from a global model. Based on this analysis, a method for polytype-stabilized SiC growth was proposed that involves decreasing the pressure as a function of growth time. The 4H-SiC prepared using this pressure-controlled method was more stable than that of 4H-SiC formed using the conventional constant-pressure method..
118.	長谷川一徳, 大村一郎, 西澤伸一, 三相インバータ用直流リンクコンデンサに適した評価回路の実験検証 (電力技術電力系統技術半導体電力変換合同研究会電力技術一般ならびに半導体電力変換一般), 電気学会研究会資料. PSE = The papers of Technical Meeting on "Power Systems Engineering", IEE Japan, 2016, 21, 43-48, 2016.03.
119.	Shinichi Nishizawa, Wafer requirement for future power devices, 35th IEEE Region 10 Conference, TENCON 2015 TENCON 2015 - 2015 IEEE Region 10 Conference, 10.1109/TENCON.2015.7372890, 2016-January, 2016.01, [URL], For the future power electronics system, one of the key issues is to achieve more high power densities. At the moment, several types of silicon devices are widely used from the low voltage to high voltage ranges. To achieve more high power densities by size reduction and more high operating temperature, not only the device but also wafer material should be improved. The current status and future prospect of PE system with silicon technology will be discussed. Then, the role of compound semiconductor and its devices will be also discussed by comparison with silicon PE system..
120.	Akira Nakajima, Shinichi Nishizawa, Shunsuke Kubota, Rei Kayanuma, Kazuo Tsutsui, Hiromichi Ohashi, Kuniyuki Kakushima, Hitoshi Wakabayashi, Hiroshi Iwai, An Overview of GaN-Based Monolithic Power Integrated Circuit Technology on Polarization-Junction Platform, 37th IEEE International Symposium on Workload Characterization, IISWC 2015 2015 IEEE Compound Semiconductor Integrated Circuit Symposium, CSICS 2015, 10.1109/CSICS.2015.7314489, 2015.10, [URL], This paper gives an overview of GaN-based polarization-junction (PJ) technologies. PJ platform wafers have both high-density 2D hole gas (2DHG) and 2D electron gas (2DEG) respectively induced by negative and positive polarization charges in undoped GaN/AlGaN/GaN double heterostructures. On the platform, monolithic operations of GaN-based n-channel transistors and p-channel transistors have been demonstrated. Because of temperature independent properties of the 2DHG and 2DEG, the GaN devices can operate in wide temperature range. In addition, high voltage transistors and diode are also available on the platform by using polarization-superjunction concept..
121.	Sethavut Duangchan, Yusuke Uchikawa, Yusuke Koishikawa, Baba Akiyoshi, Kentaro Nakagawa, Satoshi Matsumoto, Masataka Hasegawa, Shinichi Nishizawa, The silicon on diamond structure by low-temperature bonding technique, 2015 65th IEEE Electronic Components and Technology Conference, ECTC 2015 2015 IEEE 65th Electronic Components and Technology Conference, ECTC 2015, 10.1109/ECTC.2015.7159590, 2015-July, 187-192, 2015.07, [URL], We demonstrate fabrication a silicon on diamond structure at around room temperature using a plasma-activated bonding (PAB) method. Thin and flat silicon-dioxide (SiO₂) film was used as an activation layer for PAB. The SiO₂ film was prepared by a chemical vapor deposition and then a chemical mechanical polishing (CMP). The surface roughness after the CMP were average ∼1 nm rms at 300 nm thick. Thinning of the SiO₂ film was carried out using 2.5%HF solution. We found that there are no significant change in the surface roughness after the thinning process. The roughness of SiO₂ less than or equal to 1 nm is required for success bonding at low-temperature with vacuum environment. The scanning electron microscope has shown seamless at the bonding interface that proves to good bonding result..
122.	Akira Nakajima, Shinichi Nishizawa, Hiromichi Ohashi, Rei Kayanuma, Kazuo Tsutsui, Shunsuke Kubota, Kuniyuki Kakushima, Hitoshi Wakabayashi, Hiroshi Iwai, GaN-based monolithic power integrated circuit technology with wide operating temperature on polarization-junction platform, 27th IEEE International Symposium on Power Semiconductor Devices and IC's, ISPSD 2015 2015 IEEE 27th International Symposium on Power Semiconductor Devices and IC's, ISPSD 2015, 10.1109/ISPSD.2015.7123463, 2015-June, 357-360, 2015.06, [URL], Polarization junction platforms have high-density 2D hole gas (2DHG) and 2D electron gas (2DEG) respectively induced by negative and positive polarization charges in undoped GaN/AlGaN/GaN double heterostructures. Sheet resistance measurements in a wide temperature range (6-460 K) revealed that 2DHG and 2DEG resistances were monotonically enhanced with the temperature reduction. On the platform, monolithic operations of GaN-based devices including high-voltage n-channel (N-ch) transistors, N-ch Schottky diodes, low-voltage N-ch transistors and p-channel transistors has been demonstrated..
123.	Nakajima, Akira, Nishizawa, Shin-Ichi, Ohashi, Hiromichi, Saito, Wataru, Theoretical Loss analysis of power converters with 1200 v class Si-IGBT and SiC-MOSFET, PCIM Europe 2015; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management; Proceedings of, 2015.05.
124.	Nakajima, Akira, Murakami, Hiroshi, Nishizawa, Shin-Ichi, Ohashi, Hiromichi, Kosugi, Ryoji, Mitani, Takeshi, Tateishi, Yosuke, Takahashi, Hidetomo, Ota, Michiharu, High-speed dicing of SiC wafers by femtosecond pulsed laser, Materials Science Forum, 10.4028/www.scientific.net/MSF.821-823.524, 821-823, 524-527, 2015.01, [URL].
125.	Akira Nakajima, Pucheng Liu, Masahiko Ogura, Toshiharu Makino, Kuniyuki Kakushima, Shinichi Nishizawa, Hiromichi Ohashi, Satoshi Yamasaki, Hiroshi Iwai, Generation and transportation mechanisms for two-dimensional hole gases in GaN/AlGaN/GaN double heterostructures, Journal of Applied Physics, 10.1063/1.4872242, 115, 15, 2014.04, [URL], The electrical properties of two-dimensional hole gases (2DHGs) in GaN/AlGaN/GaN double heterostructures were investigated. The layers were grown on sapphire substrates and a high-quality bulk GaN substrate. The coexistence of 2DHG and 2D electron gases on both sides of the AlGaN layer was confirmed by Hall effect measurements at 80-460 K. It was also verified that the 2DHGs were generated by negative polarization at the undoped GaN/AlGaN interface, which did not have a doped Mg acceptor. It was also demonstrated that the 2DHG density could be controlled by varying the AlGaN layer thickness and was inversely related to the 2DHG mobility. The measured relation indicated that the 2DHG mobility is mainly limited by phonon scatterings at around room temperature. As a result, the maximum 2DHG mobility of 16 cm/Vs at 300 K was achieved with a density of 1 × 10 cm^-2..
126.	Nakagawa Kentaro, Kodama Takuya, Matsumoto Satoshi, Yamada Takatoshi, Hasegawa Masataka, Nishizawa Shinichi, Erratum: “Impact of semiconductor on diamond structure for power supply on chip applications”, Jpn. J. Appl. Phys., 10.7567/JJAP.53.069202, 53, 6, 69202-69202, 2014.06, [URL].
127.	Yuji Matsuoka, Keiji Wada, Mizuki Nakahara, Kazuto Takao, Kyungmin Sung, Hiromichi Ohashi, Shinichi Nishizawa, 2.5kV, 200kW bi-directional isolated DC/DC converter for medium-voltage applications, 7th International Power Electronics Conference, IPEC-Hiroshima - ECCE Asia 2014 2014 International Power Electronics Conference, IPEC-Hiroshima - ECCE Asia 2014, 10.1109/IPEC.2014.6869671, 744-749, 2014.01, [URL], A bi-directional isolated DC/DC converter for medium-voltage applications have been discussed for the next-generation electrical grid, such as smart girds. To realize the DC/DC converter for installing on a power distribution system, it should be achieved higher-efficiency and lower-volume. Higher switching frequency enables to reduce the volume of the transformer. However, it is difficult to realize the both higher-efficiency and lower-volume of the DC/DC converter, because it could not operate higher frequency with high power devices such as medium-voltage IGBTs. This paper discusses switching losses and operation limitations for the actual medium-voltage isolated DC/DC converter, in the case of using Si-IGBT. In addition, the experimental system rated at 2.5 kV, 200 kW, and 5kH of the DC/DC converter with a medium-frequency transformer is designed, and the experimental results are shown..
128.	Nakagawa Kentaro, Kodama Takuya, Matsumoto Satoshi, Yamada Takatoshi, Hasegawa Masataka, Nishizawa Shinichi, Impact of semiconductor on diamond structure for power supply on chip applications, Jpn. J. Appl. Phys., 10.7567/JJAP.53.04EP16, 53, 4 SPEC. ISSUE, 04EP16, 2014.01, [URL].
129.	T. Shiramomo, B. Gao, F. Mercier, Shinichi Nishizawa, S. Nakano, Koichi Kakimoto, Study of the effect of doped impurities on polytype stability during PVT growth of SiC using 2D nucleation theory, Journal of Crystal Growth, 10.1016/j.jcrysgro.2013.03.036, 385, 95-99, 2014.01, [URL], The effect of nitrogen and aluminum as doped impurities on the stability of SiC polytypes (C- or Si-face 4H and 6H substrates) formed by physical vapor transport (PVT) was investigated. The stability of the polytypes was analyzed using classical thermodynamic nucleation theory with numerical results obtained from a global model including heat, mass and species transfer in a PVT furnace. The results reveal that the formation of 4H-SiC was more stable than that of 6H-SiC when a grown crystal was doped with nitrogen using C-face 4H- and 6H-SiC as seed crystals. In contrast, formation of 6H-SiC was favored over 4H-SiC when Si-face 4H- and 6H-SiC seed crystals were used. Meanwhile, the formation of 4H-SiC was more stable than that of 6H-SiC when aluminum was the dopant and C- and Si-faces of 6H-SiC were used as seed crystals. Formation of 6H-SiC occurred over that of 4H-SiC in the cases of C- and Si-faces of 4H-SiC as seed crystals..
130.	S. Nakashima, T. Tomita, N. Kuwahara, T. Mitani, M. Tomobe, Shinichi Nishizawa, H. Okumura, Raman intensity profiles of zone-folded modes in SiC Identification of stacking sequence of 10H-SiC, Journal of Applied Physics, 10.1063/1.4828996, 114, 19, 2013.11, [URL], Raman intensity profiles are measured for 10H-SiC crystals, for which various zone-folded phonon modes are observed. Raman intensity profiles are calculated based on a bond polarizability model assuming several stacking sequences for the 10H polytype using a linear chain model. Among several candidates for the stacking sequences, the 3322 stacking structure provides the best-fit profile for experimental spectral profiles. The hexagonality value of 0.4 predicted from the stacking sequence of this polytype is consistent with that derived from the frequency splitting between the experimental A₁ and E-type transverse optical modes. This fact is consistent with an empirical rule that the value of the reduced wavevector for the strongest folded transverse acoustic and optical modes are equal to the hexagonality of the polytype. In the present analysis of the Raman intensity profiles, the calculated intensity profiles for specified folded transverse optical modes are found to be relatively strong and strikingly dependent on force-field parameters in α-SiC that consists of the mixture of the cubic and hexagonal stacking structures. These force-field parameters can reproduce well the experimental Raman intensity profiles of various SiC polytypes including 10H-SiC..
131.	Akira Nakajima, Pucheng Liu, Masahiko Ogura, Toshiharu Makino, Shinichi Nishizawa, Satoshi Yamasaki, Hiromichi Ohashi, Kuniyuki Kakushima, Hiroshi Iwai, Temperature-independent two-dimensional hole gas confined at GaN/AlGaN heterointerface, Applied Physics Express, 10.7567/APEX.6.091002, 6, 9, 2013.09, [URL], The electrical properties at the GaN(0001)/AlGaN(0001) heterointerface have been investigated. Capacitance-voltage measurement and theoretical simulation results verify the existence of a two-dimensional (2D) hole gas, which is highly confined to the GaN/AlGaN interface with a peak carrier density of over 10 ¹⁹ cm^-3. Hall-effect measurements in the 80-460 K temperature range reveal that the 2D hole gas has zero activation energy and positive sheet-resistance temperature coefficients..
132.	Frédéric Mercier, Shinichi Nishizawa, Comparative numerical study of the effects of rotating and traveling magnetic fields on the carbon transport in the solution growth of SiC crystals, Journal of Crystal Growth, 10.1016/j.jcrysgro.2011.11.019, 362, 1, 99-102, 2013.01, [URL], We present numerical simulations of the high temperature solution growth (HTSG) of silicon carbide (SiC) crystals. From a global simulation model, we investigate the influence of rotating magnetic fields (RMFs) and traveling magnetic fields (TMFs) on the crystal growth rate. The results reveal that heat and mass transfers are affected by magnetic fields. We show that direction of the solute flux must be controlled to increase the growth rate. For example, in presence of TMFs directed downwards the growth rate increases up to three times compared with the pure thermal HTSG. The proposed HTSG system coupled with magnetic fields has the same growth rate possibility as in the sublimation technique..
133.	S. Leone, A. Henry, E. Janzén, Shinichi Nishizawa, Epitaxial growth of SiC with chlorinated precursors on different off-angle substrates, Journal of Crystal Growth, 10.1016/j.jcrysgro.2011.09.061, 362, 1, 170-173, 2013.01, [URL], This study focuses on the epitaxial growth of silicon carbide (SiC) epitaxial layers, adopting the chloride-based chemical-vapor-deposition (CVD) process, which allows to achieve ten times higher growth rate compared to the standard process based on the mixture of a silicon-containing gas and a hydrocarbon. In order to improve the material quality, substrates with different off-angles were used, since low off-angle substrates result in a reduction of killer defects for specific devices. Different growth mechanisms dominate for different substrate off-cut and an accurate set up of dedicated surface preparation procedures and tuning of growth parameters are needed. This study demonstrates that silicon-rich gas inputs are favorable for lower off-angle (nominally on-axis) substrates, while carbon-rich are beneficial for higher off-angles (usually 8° off-axis for 4H-SiC). Methyltrichlorosilane (MTS) is shown to be the best precursor to achieve the presented results..
134.	Frédéric Mercier, Shinichi Nishizawa, Role of surface effects on silicon carbide polytype stability, Journal of Crystal Growth, 10.1016/j.jcrysgro.2011.11.052, 360, 1, 189-192, 2012.12, [URL], We investigated with ab initio calculations the energetics of the most common silicon carbide (SiC) polytypes. We considered the (0001) Si face and the (0001̄) C face of 3C-, 6H-, 4H- and 2H-SiC. Our investigation reveals that the energy differences among SiC polytypes are enhanced at the surface with respect to the bulk. We discuss the relevant role played by the surface for the crystal growth of SiC..
135.	高尾和人, 大田千春, 四戸孝, 和田圭二, 成慶〓, 松岡祐司, 金井丈雄, 田中保宣, 西澤伸一, 大橋弘通, 4.5kV-400A Si-IEGT+SiC-PiN ダイオードハイブリッドペアモジュールによる高電圧大電力変換器の4kHzスイッチング動作の実証, 電気学会研究会資料. SPC, 半導体電力変換研究会, 2012, 115, 13-17, 2012.10.
136.	児玉拓也, 松本聡, 西澤伸一, ダイヤモンド薄膜を絶縁膜として用いたパワーSoC用SOI基板のシミュレーションによる検討, 電気学会研究会資料. EDD, 電子デバイス研究会, 2012, 59, 13-17, 2012.10.
137.	T. Shiramomo, B. Gao, F. Mercier, Shinichi Nishizawa, S. Nakano, Yoshihiro Kangawa, Koichi Kakimoto, Thermodynamical analysis of polytype stability during PVT growth of SiC using 2D nucleation theory, Journal of Crystal Growth, 10.1016/j.jcrysgro.2012.01.023, 352, 1, 177-180, 2012.08, [URL], We studied dependence of process parameters, such as temperature of a seed, pressure in a furnace and surface polarity of a substrate, on polytypes of SiC in a process of physical vapor transport. The analysis was based on a classical thermodynamic nucleation theory in conjunction with numerical results obtained from a global model. We investigated which polytype was more stable in the nucleation stage by a comparison of nucleation energies of each polytype. The results show that the formation of 4H-SiC was more stable than that of 6H-SiC when we used C-face SiC as a seed. Furthermore, the most stable polytype could change from 4H-SiC to 6H-SiC in a condition of higher supersaturation, with a condition of higher temperature of a seed and lower pressure in a furnace. Meanwhile, the formation of 6H-SiC was more stable than 4H-SiC when Si-face of a seed was used..
138.	Henrik Pedersen, Stefano Leone, Olof Kordina, Anne Henry, Shinichi Nishizawa, Yaroslav Koshka, Erik Janzén, Chloride-based CVD growth of silicon carbide for electronic applications, Chemical Reviews, 10.1021/cr200257z, 112, 4, 2434-2453, 2012.04, [URL], A study was conducted to demonstrate chloride-based chemical vapor deposition (CVD) growth of silicon carbide (SiC) for electronic applications. SiC homoepitaxial growth was done using CVD with silane (SiH ₄) as the silicon precursor and light hydrocarbons, including ethylene (C ₂H ₄) or propane (C ₃H ₈) as the carbon precursor. Simulation was an invaluable tool along with comparisons between different chlorinated chemistries to obtain a deeper understanding of the chloride-based process and provide more information. A number of approaches were selected to add chlorine to the gas mixture for the growth of SiC epitaxial layers using a chloride-based chemistry..
139.	Stefano Leone, Olof Kordina, Anne Henry, Shinichi Nishizawa, Örjan Danielsson, Erik Janzén, Gas-phase modeling of chlorine-based chemical vapor deposition of silicon carbide, Crystal Growth and Design, 10.1021/cg201684e, 12, 4, 1977-1984, 2012.04, [URL], Kinetic calculations of the chemical phenomena occurring in the epitaxial growth of silicon carbide are performed in this study. The main process parameters analyzed are precursor types, growth temperature, Cl/Si ratio, and precursors' concentration. The analysis of the gas-phase reactions resulted in a model which could explain most of the already reported experimental results, performed in horizontal hot-wall reactors. The effect of using different carbon or silicon precursors is discussed, by comparing the gas-phase composition and the resulting C/Si ratio inside the hot reaction chamber. Chlorinated molecules with three chlorine atoms seem to be the most efficient and resulting in a uniform C/Si ratio along the susceptor coordinate. Further complexity in the process derives from the use of low temperatures, which affects not only the gas-phase composition but also the risk of gas-phase nucleation. The Cl/Si ratio is demonstrated to be crucial not only for the prevention of silicon clusters but also for the uniformity of the gas-phase composition..
140.	中川徹也, 和田圭二, 西澤伸一, 大橋弘通, パワーMOSFETの信頼性評価を目的とした非破壊試験回路の検討, 電気学会研究会資料. SPC, 半導体電力変換研究会, 2012, 1, 115-120, 2012.01.
141.	Koichi Kakimoto, B. Gao, T. Shiramomo, S. Nakano, Shinichi Nishizawa, Thermodynamic analysis of SiC polytype growth by physical vapor transport method, Journal of Crystal Growth, 10.1016/j.jcrysgro.2011.03.059, 324, 1, 78-81, 2011.06, [URL], Crystal growth of a certain polytype of SiC in a process of physical vapor transport was studied on the basis of classical thermodynamic nucleation theory in conjunction with numerical results obtained from a global model. Formation of a certain polytype in the nucleation stage is determined by the energy balance among surface energy, formation energy and supersaturation. The preferential growth condition of a certain polytype was estimated. The value of supersaturation was estimated using a numerical model obtained by a global model that includes species transport as well as heat transport in a furnace. The results of calculation showed that 4H polytype is more stable than 15R, 6H and 3C polytypes. Free energy difference between 4H and 6H polytypes decreased when total pressure in the furnace decreased..
142.	Mercier Frederic, Nishizawa Shin-ichi, Numerical Investigation of the Growth Rate Enhancement of SiC Crystal Growth from Silicon Melts, Jpn J Appl Phys, 10.1143/JJAP.50.035603, 50, 3, 35603-035603-5, 2011.03, [URL], Numerical study has been applied to analyze the high temperature solution growth process for bulk silicon carbide (SiC) crystal growth. A two-dimensional axisymmetric model for 2-in. SiC crystal growth was used for this study. The purpose of this paper is to investigate the possible approaches to enhance the growth rate in this process. In particular, we studied the effect of an AC magnetic field on the carbon transport to the crystal growth interface. The results revealed that the carbon flux to the growing crystal is strongly affected by the coil position and the applied frequency. If these two process parameters are properly chosen, we show that the carbon flux at the growing front, and thus the growth rate of SiC, can be enhanced..
143.	Frédéric Mercier, Shinichi Nishizawa, Solution growth of SiC from silicon melts Influence of the alternative magnetic field on fluid dynamics, Journal of Crystal Growth, 10.1016/j.jcrysgro.2010.10.022, 318, 1, 385-388, 2011.03, [URL], We studied numerically the fluid dynamics of the silicon melt in the high temperature solution growth of silicon carbide (SiC) with the presence of alternative magnetic fields. A 2D-axisymmetric model for 2 in SiC crystal growth was used for this study. The results revealed that the melt convection is strongly affected by the coil position and the applied frequency. Results on the effect of electromagnetic convection in the presence of buoyancy convection are also given in this paper..
144.	B. Gao, X. J. Chen, S. Nakano, Shinichi Nishizawa, Koichi Kakimoto, Analysis of SiC crystal sublimation growth by fully coupled compressible multi-phase flow simulation, Journal of Crystal Growth, 10.1016/j.jcrysgro.2010.08.032, 312, 22, 3349-3355, 2010.11, [URL], A fully coupled compressible multi-phase flow solver was developed to effectively design a large furnace for producing large-size SiC crystals. Compressible effect, convection and buoyancy effects, flow coupling between argon gas and species, and the Stefan effect are included. A small and experimental furnace is used to validate the solver. First, the essentiality of 2D flow calculation and the significance of incorporating buoyancy effect and gas convection, the Stefan effect, and flow interaction between argon gas and species were investigated by numerical results. Then the effects of argon gas on deposition rate, growth rate, graphitization on the powder source, and supersaturation and stoichiometry on the seed were analyzed. Finally, the advantages of an extra chamber design were explained, and improvement of growth rate was validated by the present solver..
145.	Xuejiang Chen, Shinichi Nishizawa, Koichi Kakimoto, Numerical simulation of a new SiC growth system by the dual-directional sublimation method, Journal of Crystal Growth, 10.1016/j.jcrysgro.2010.02.027, 312, 10, 1697-1702, 2010.05, [URL], A new SiC growth system using the dual-directional sublimation method was investigated in this study. Induction heating and thermal conditions were computed and analyzed by using a global simulation model, and then the values of growth rate and shear stress in a growing crystal were calculated and compared with those in a conventional system. The results showed that the growth rate of SiC single crystals can be increased by twofold by using the dual-directional sublimation method with little increase in electrical power consumption and that thermal stresses can be reduced due to no constraint of the crucible lid and low temperature gradient in crystals..
146.	西澤伸一, 大橋弘通, パワーエレクトロニクス用基板の開発動向と加工技術課題 (特集グリーンエネルギー時代を支える先進加工技術とその課題), 機械と工具, 53, 8, 15-19, 2009.08.
147.	Shinichi Nishizawa, Numerical modeling of SiC single crystal growth-sublimation and hot-wall epitaxy, Journal of Crystal Growth, 10.1016/j.jcrysgro.2008.09.105, 311, 3, 871-874, 2009.01, [URL], On the engineering point of view, it is important to develop a design technology of the furnace for SiC single crystal growth. In this point of view, the recent progress of modeling on both sublimation bulk growth and hot-wall epitaxy were presented. For the sublimation, the active control of grown crystal shape by modifying crucible geometry was demonstrated. The effect of nitrogen doping on the heat transfer in a growing crystal were also investigated. For the hot-wall epitaxy, growth rate, surface morphology, and doping concentration could be predicted qualitatively with taking account of the depositing surface conditions. Chlorine-containing system was supposed to provide more stable and uniform process than the common SiH₄-based system..
148.	K. Fukuda, S. Harada, J. Senzaki, M. Okamoto, Y. Tanaka, A. Kinoshita, R. Kosugi, K. Kojima, M. Kato, A. Shimozato, K. Suzuki, Y. Hayashi, K. Takao, T. Kato, Shinichi Nishizawa, T. Yatsuo, H. Okumura, H. Ohashi, K. Arai, Challenges of 4H-SiC MOSFETs on the C(000-1) face toward the achievement of ultra low on-resistance, Materials Science Forum, 10.4028/3-908453-11-9.907, 600-603, 907-912, 2008.09, [URL], The C(000-1) face of 4H-SiC has a lot of advantages for the power device fabrication such as the highest oxidation ratio and a smooth surface. However, the DMOS type power MOSFETs on the C(000-1) face have not been realized because of the difficulty of epitaxial growth and of high quality MOS interface formation. We have systematically investigated the device fabrication techniques for power MOSFETs on the C(000-1) face, and succeeded with the IEMOS which have blocking voltage of 660V and an on-resistance of 1.8mΩcm² and excellent dynamic characteristics..
149.	Michel Pons, Shinichi Nishizawa, Peter Wellmann, E. Blanquet, D. Chaussende, J. M. Dedulle, R. Madar, Silicon carbide growth C/Si ratio evaluation and modeling, Materials Science Forum, 10.4028/3-908453-11-9, 600-603, 83-88, 2008.09, [URL], Modeling and simulation of the SiC growth processes, Physical Vapor Transport (PVT), Chemical Vapor Deposition (CVD), are sufficiently mature to help building new process equipment or up-scaling old ones. It is possible (i) to simulate accurately temperature and deposition distributions, as well as doping (ii) to quantify the limiting phenomena, (iii) to understand the important role of different precursors in CVD and hydrogen additions in PVT. The first conclusion of this paper is the importance of the "effective" C/Si ratio during CVD epitaxy in hot-wall reactors and its capability to explain the doping concentrations. The second conclusion is the influence of the C/Si ratio in alternative bulk growth technique involving gas additions..
150.	Johji Nishio, Chiharu Ota, Tetsuo Hatakeyama, Takashi Shinohe, Kazutoshi Kojima, Shinichi Nishizawa, Hiromichi Ohashi, Ultralow-loss SiC floating junction Schottky barrier diodes (Super-SBDs), IEEE Transactions on Electron Devices, 10.1109/TED.2008.926666, 55, 8, 1954-1960, 2008.08, [URL], We have applied the floating junction (FJ) structure, which has been confirmed to be effective in reducing the on-resistance of Si power devices, to SiC FJ Schottky barrier diodes (SiC Super-SBDs). Optimization of the device parameters, which are derived by making improvements in the device simulator, and development of the fabrication process have enabled realization of Super-SBDs with a breakdown voltage of 2700 V and a specific on-resistance of 2.57 mΩ · cm². These values correspond to the world record of 11.3 GW/cm² for Baliga's figure-of-merit (BFOM} = 4V_bd²/R_on-sp)..
151.	Tomohisa Kato, Keisuke Wada, Eiji Hozomi, Hiroyoshi Taniguchi, Tomonori Miura, Shinichi Nishizawa, Kazuo Arai, High throughput SiC wafer polishing with good surface morphology, Materials Science Forum, 556-557, 753-756, 2007.09, We report SiC wafer polishing study to achieve high throughput with extremely flat, smooth and damageless surface. The polishing consists of three process, wafer grinding, lapping and chemical mechanical polishing (CMP), which are completed in shortest about 200 minutes in total for 2 inch wafer. Specimens of 4H- and 6H-SiC were provided from slicing single crystal as wafers oriented (0001) with 0 or 8 degrees offset angle toward to 〈1120〉. By the first grinding using a diamond whetstone wheel, we realized flat surface on the wafers with small TTV error of 1 μm in 15 minutes. After second process of lapping, the wafers were finished by CMP using colloidal silica slurry. AFM observation showed not only scratch-free surface but also atomic steps on the wafers after CMP. Rms marks extremely flat value of 0.08 nm in 10 μm square area..
152.	C. Ota, J. Nishio, T. Hatakeyama, T. Shinohe, K. Kojima, Shinichi Nishizawa, H. Ohashi, Simulation, fabrication and characterization of 4H-SiC floating junction schottky barrier diodes (Super-SBDs), Materials Science Forum, 556-557, 881-884, 2007.09, The calculation for 4H-SiC floating junction Schottky barrier diodes (Super-SBDs) was carried out by device simulation and the optimized device structure was fabricated. The best characteristics of the Super-SBDs were breakdown voltage of 2700V and the specific on-resistance of 2.57mΩcm ². The world record of Bariga's Figure of Merit (BFOM) for SiC-SBD expressed by 4V_bd ²/R_on was improved to 11,354MW/cm²..
153.	Akimasa Kinoshita, Kenji Suzuki, Junji Senzaki, Makoto Katou, Shinsuke Harada, Mitsuo Okamato, Shinichi Nishizawa, Kenji Fukuda, Fukuyoshi Morigasa, Tomoyoshi Endou, Takuo Isii, Teruyuki Yashima, Activation of p-type dopants in 4H-SiC using hybrid super-rapid thermal annealing equipment, Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes, 10.1143/JJAP.46.5342, 46, 8 A, 5342-5344, 2007.08, [URL], Rapid thermal annealing (RTA) on areas with diameters as large as 2 in. at high temperatures using hybrid super-RTA (HSRTA) equipment is performed in this study. The HS-RTA equipment consists of an infrared annealing unit and an RF induction annealing unit for uniform annealing over a 2-in.-φ susceptor. As a result of annealing using the HS-RTA equipment, temperature is elevated from RT to a high temperature (1600-1800°C) for less than 1 min. Using aluminum (Al)-implanted silicon carbide (SiC) samples, the performance of the HS-RTA equipment is evaluated. For Al-implanted samples annealed at 1700°C, the sheet resistance distribution on the 2-in.-φ susceptor is 8.0%..
154.	Shinichi Nishizawa, Tomohisa Kato, Kazuo Arai, Effect of heat transfer on macroscopic and microscopic crystal quality in silicon carbide sublimation growth, Journal of Crystal Growth, 10.1016/j.jcrysgro.2006.12.022, 303, 1 SPEC. ISS., 342-344, 2007.05, [URL], Numerical simulation was applied to observe the phenomena inside a crucible in silicon carbide (SiC) sublimation growth. Numerical simulation results show that crystal quality as well as crystal shape strongly depends on the temperature distribution inside the crucible. Numerical simulation also suggested that it is important to reduce the residual stress in the crystal in order to avoid the generation of dislocations. From these results, SiC sublimation growth was controlled actively, and large and high quality SiC single crystal was grown..
155.	Shinichi Nishizawa, Michel Pons, Numerical modeling of silicon carbide epitaxy in a horizontal hot-wall reactor, Journal of Crystal Growth, 10.1016/j.jcrysgro.2006.12.018, 303, 1 SPEC. ISS., 334-336, 2007.05, [URL], Numerical simulation was carried out on SiC-CVD in a horizontal hot-wall reactor. The growth and doping features of both Si- and C-terminated surfaces were analyzed by changing the inlet source gas conditions. The role of conditions at the growing surface on the growth feature was investigated. It was identified that the conditions at the growing surface are good parameters to explain the growth feature..
156.	S. Nakashima, T. Mitani, T. Tomita, T. Kato, Shinichi Nishizawa, H. Okumura, H. Harima, Observation of surface polarity dependent phonons in SiC by deep ultraviolet Raman spectroscopy, Physical Review B - Condensed Matter and Materials Physics, 10.1103/PhysRevB.75.115321, 75, 11, 2007.03, [URL], Backscattering Raman spectra of SiC polytype crystals with SiC{0001} polar faces have been measured using deep ultraviolet (DUV), UV, and visible (VIS) excitation sources. We have found that for DUV excitation the intensity profiles of zone-folded modes differ markedly for Si and C faces. This Raman spectral feature is attributed to the presence of nonpropagating phonon modes confined in the near-surface region. It is concluded that the surface-bound phonon modes created with DUV photon field extend over a region a few hundred nanometers in depth, and that the displacements of the phonon modes are anisotropic in the direction of the polar axis. This surface-orientation-dependent Raman spectrum can be used to identify the surface polarity of SiC polytypes..
157.	Tomohisa Kato, Tomonori Miura, Keisuke Wada, Eiji Hozomi, Hiroyoshi Taniguchi, Shinichi Nishizawa, Kazuo Arai, Defect and growth analysis of SiC bulk single crystals with high nitrogen doping, Materials Science Forum, 556-557, 239-242, 2007.01, In this study, we report defect analysis in 4H-SiC crystals of high nitrogen doping grown by sublimation method, and we discuss key points for defect restraint. The growth was performed in two kinds of growth directions; c-axis and a-axis. In the c-axis grown crystal with carrier density greater than 1 × 10^-19cm^-3, defect propagation was confirmed in the vertical direction for a growth direction affected by the doping by x-ray topography. This phenomenon was not observed in the a-axis grown crystals. In sublimation growth, the quantity of impurities tends to increase as growth rate decreases. Therefore, in the c-axis growth of doped 4H-SiC bulk crystals, we have to be careful so that dopant does not increase too much without intention in grown layers with lower growth rate, for example at the beginning and end of the growth..
158.	Shinichi Nishizawa, Michel Pons, Growth and doping modeling of SiC-CVD in a horizontal hot-wall reactor, Chemical Vapor Deposition, 10.1002/cvde.200606469, 12, 8-9, 516-522, 2006.08, [URL], Modeling and simulation of the SiC epitaxial growth, and doping in a horizontal hot-wall reactor from common precursors (SiH₄; C ₃H₈ diluted in H₂ for growth; N₂ and Al(CH₃)₃ for n-type and p-type doping) are presented. The growth and doping features of SiC thin layers on both Si-terminated and C-terminated surfaces are analyzed as a function of various inlet source gas conditions, i.e., various C/Si ratios. The role of the actual surface mass fluxes of both Si-containing and C-containing species and their ratio is analyzed and compared to the inlet experimental parameters. It is demonstrated that the doping level resulting from lattice site competition effects can be quantified by the actual C/Si ratio calculated above the growing surface. Moreover, the surface morphology of the epitaxial layer is explained on the basis of the mass fluxes at the growing surface..
159.	加藤智久, 山口博隆, 西澤伸一, 荒井和雄, X線可視化・シミュレーションによる単結晶育成過程の追跡, 應用物理, 75, 5, 584-585, 2006.05.
160.	S. Nakashima, T. Kato, Shinichi Nishizawa, T. Mitani, H. Okumura, T. Yamamoto, Deep ultraviolet raman microspectroscopic characterization of polishing-induced surface damage in SiC crystals, Journal of the Electrochemical Society, 10.1149/1.2170546, 153, 4, 2006.04, [URL], We have investigated polishing-induced surface damage in nitrogen-doped {0001} 4H-SiC crystals with silicon and carbon faces through deep ultraviolet Raman microspectroscopy. The structural and electrical properties of the damaged layers were characterized as a function of the abrasive particle size, using pure phonon modes and a longitudinal-optical-phonon plasmon coupled mode as monitor bands. The degree of damage decreased with the size. Although abrasive polishing with finer particles enables the long-range order of the lattice to almost fully recover, the carrier density remains partly reduced in the polished surface layers. The number of defects that induces a reduction in the free carrier density differs between the Si and C faces of 4H-SiC crystals..
161.	Shinichi Nishizawa, Michel Pons, Numerical modeling of SiC-CVD in a horizontal hot-wall reactor, Microelectronic Engineering, 10.1016/j.mee.2005.10.033, 83, 1 SPEC. ISS., 100-103, 2006.01, [URL], A numerical simulation was carried out on SiC-CVD in a horizontal hot-wall reactor. In order to explain the effect of surface polarity, Si-face and C-face, the surface reaction model was improved. Then, the growth processes and doping features of both Si-face and C-face were analyzed. The role of conditions at growing surface, such as surface mass flux of both Si-containing and C-containing species, surface concentration of Si-containing and C-containing species and their ratio, is investigated. Then, the deposition and etching rates, and doping concentration are analyzed as the function of those parameters. In addition, surface morphology of growing epitaxial layer is also investigated in connection with growing surface condition..
162.	Tomohisa Kato, Shinichi Nishizawa, Hirotaka Yamaguchi, Kazuo Arai, In-situ observation of SiC bulk single crystal growth by XRD system, Journal of Rare Earths, 24, SUPPL., 49-53, 2006, In-situ analysis for SiC bulk single crystal growth was reported using vertical X-ray diffraction (XRD) system. A furnace for SiC sublimation growth combined with the XRD system which possessed three kinds of functions including topography, rocking curve measurement and crystal growth rate monitoring was developed. These functions could contribute as a powerful tool finding the optimum growth condition by dynamic observation in the crucible. The in-situ X-ray topography succeeded to capture dynamic elongation of defects and dislocation generated in the SiC growing crystals. The in-situ rocking curve measurement revealed appearance of mosaic structure in the SiC crystal grown with high growth rate. The in-situ growth rate monitoring also succeeded very precisely using the direct X-ray beam absorption. On the base of findings and facts obtained by the in-situ observations, the importance for the SiC growth was discussed..
163.	K. Kojima, Shinichi Nishizawa, S. Kuroda, H. Okumura, K. Arai, Effect of growth condition on micropipe filling of 4H-SiC epitaxial layer, Journal of Crystal Growth, 10.1016/j.jcrysgro.2004.11.071, 275, 1-2, 2005.02, [URL], In this study, we studied the effect of growth conditions on micropipe (MP) filling during 4H-SiC epitaxial growth. We found that an MP in an on-axis substrate was filled during epitaxial growth and that this MP was filled with a spiral growth. The MP filling on on-axis substrates had a high probability and was independent of growth conditions. On the other hand, the probability of MP filling of 8° off-axis substrates showed a strong dependence on the growth pressure and the growth rate. The probability of MP filling increased with decreasing growth pressure or increasing growth rate. The probability of MP filling of the C-face was higher than that of the Si-face. From a comparison of a numerical simulation and experimental results, we found that the concentration of Si species just above the substrate was a crucial factor for MP filling..
164.	Shinichi Nishizawa, Kazutoshi Kojima, Satoshi Kuroda, Kazuo Arai, Michel Pons, Modeling of SiC-CVD on Si-face/C-face in a horizontal hot-wall reactor, Journal of Crystal Growth, 10.1016/j.jcrysgro.2004.11.072, 275, 1-2, 2005.02, [URL], To explain the difference between SiC-CVD on the Si-face and C-face, a heterogeneous model was improved, in which the etching, growth and doping features of SiC-CVD in a horizontal hot-wall reactor were numerically analyzed. The improved model was able to explain the etching and growth features accurately. There was no difference between the Si- and C-face. In addition, we propose the surface C/Si ratio as the universal parameter of the SiC-CVD process. Concerning doping features, the improved model showed that nitrogen and aluminum doping incorporation could be explained by the site competition model, while taking into account the amount of surface silicon and surface carbon, respectively..
165.	西澤伸一, 改良レーリー法によるSiC単結晶成長, セラミックス, 40, 1, 11-13, 2005.01.
166.	Y. Yamada, Shinichi Nishizawa, S. Nakashima, K. Arai, Continuous growth of SiC single crystal by the spray dried powder made of ultra-fine particle precursors, Materials Science Forum, 457-460, I, 131-134, 2004.06, We succeeded in continuous growth of SiC single crystal by CPD (Chemical Particle Deposition) method with the spray dried ultra-fine particle precursor powder. By the introduction of the spray dried spherical powder, we could clarify the mechanism of SiC single crystal growth by CPD method, through the observation of the deformation and the transformation of the spherical precursor powder into the epitaxial SiC grown layer on the seed crystal surface. The SiC layer grown by this method showed promising crystal quality indicated by the rocking curve with FWHM of 70-80 arcsec..
167.	Y. Tanaka, T. Ohno, N. Oyanagi, Shinichi Nishizawa, T. Suzuki, K. Fukuda, T. Yatsuo, K. Arai, Fabrication of mesa-type pn diodes without forward degradation on ultara-high-quality 6H-SiC substrate, Materials Science Forum, 457-460, II, 1009-1012, 2004.06, Using our own substrate growth and epitaxial growth techniques, we fabricated a 1.4 kV mesa-type 6H-SiC pn diode with an ideal avalanche breakdown and without forward degradation. The 6H-SiC substrates were grown on Lely crystals with no micropipes and only minimal defects. A pn junction was fabricated by chemical vapor deposition (CVD) with p⁺/n epitaxial films. We obtained 1.4 kV breakdown voltage, consistent with the ideal breakdown voltage calculated from the thickness (10μm) and doping concentration (2×10¹⁶cm^-3) of the drift layer. The application of 200 A/cm² current stress in the forward direction produced no degradation, which is often observed with pn diodes on normal commercial substrates..
168.	Shinichi Nishizawa, T. Kato, Y. Kitou, N. Oyanagi, F. Hirose, H. Yamaguchi, W. Bahng, K. Arai, High-quality SiC bulk single crystal growth based on simulation and experiment, Materials Science Forum, 457-460, I, 29-34, 2004.06, The numerical simulation and in-situ X-ray topography were applied to observe the phenomena inside a crucible. Numerical simulation pointed out that macroscopic grown crystal quality such as grown crystal shape strongly depends on the temperature distribution inside a crucible. In-situ X-ray topography revealed that when the defects were generated, and how the defects were propagated. Most of defects were generated at the initial growth stage. It is important to control the initial stage in order to obtain a high quality SiC single crystal. Numerical simulation also suggested that it is important reduce the residual stress in a grown crystal in order to avoid the dislocation occurrence. From these results based on numerical simulation and experiment, SiC sublimation growth was controlled actively, and the large and high quality SiC single crystal have been grown..
169.	T. Kato, T. Ohno, F. Hirose, N. Oyanagi, Shinichi Nishizawa, K. Arai, Large diameter and long length growth of SiC single crystal, Materials Science Forum, 457-460, I, 99-102, 2004.06, We report 4H-SiC single crystal growth of 4inch in diameter and micropipe-free crystal growth. Large single crystals were grown along c-axis and enlarged from smaller (0001) seed crystals. We confirmed that the center part of grown crystals is different in defect elongation from the enlarged part by x-ray topography. Especially, micropipes (MP) and screw dislocations (SD) are converted to basal plane dislocations in the enlarged part. By using this phenomenon, we realized a high quality crystal in the enlarged part that has x-ray rocking curve FWHM as small as 10.6arcsec. We also confirmed the crystal did not have MP and SD in a region of about 1 inch in diameter using etch pits observation and synchrotron x-ray topography. We also report the long length growth along a-axis growth on a () seed crystal and succeeded in the MP-free crystal growth..
170.	Norihiko Kiritani, Masakatsu Hoshi, Satoshi Tanimoto, Kazuhiro Adachi, Shinichi Nishizawa, Tsutomu Yatsuo, Hideyo Okushi, Kazuo Arai, Single Material Ohmic Contacts Simultaneously Formed on the Source/P-Well/Gate of 4H-SiC Vertical Mosfets, Materials Science Forum, 433-436, 669-672, 2003.09, We fabricated 4H-SiC vertical MOSFETs with contacts to the source, p-well and polycrystalline silicon (polysilicon) gate and these were simultaneously formed from a single material, using one deposition and a single contact annealing process. Typical specific contact resistances of 4.8×10 ^-5 Ωcm² for the n⁺ source region, 1.5×10^-6 Ωcm² for the gate polysilicon and 5.2×10^-4 Ωcm² for the p-well contact region were obtained using Al/Ni (Al∼6%) as the contact metal. Also, the static characteristics of the vertical MOSFETs indicated that the MOS interface can withstand an even higher temperature process such as that used in ohmic-contact formation..
171.	Shinichi Nishizawa, Yumi Michikawa, Tomohisa Kato, Fusao Hirose, Naoki Oyanagi, Kazuo Arai, Stress Analysis of SiC Bulk Single Crystal Growth by Sublimation Method, Materials Science Forum, 433-436, 13-16, 2003.09, In order to grow a high quality SiC bulk single crystal, it is important to moderate the residual stress in the grown crystal. The residual stress is affected by not only the temperature distribution, but also by the boundary conditions. In this study, firstly, the effect of the polycrystal and of the crucible walls on the stress distribution was numerically analyzed. The effect of the grown crystal shape on the residual stress was also analyzed and compared to the growth experiment. It is pointed out that in order to moderate the residual stress, it is necessary to take care not only of the temperature distribution but also of the boundary conditions..
172.	Yasunori Tanaka, Shinichi Nishizawa, Kenji Fukuda, Kazuo Arai, Toshiyuki Ohno, Naoki Oyanagi, Takaya Suzuki, Tsutomu Yatsuo, Fabrication of 1.4-kV mesa-type p⁺-n diodes with avalanche breakdown and without forward degradation on high-quality 6H-SiC substrate, Applied Physics Letters, 10.1063/1.1591062, 83, 2, 377-379, 2003.07, [URL], A 1.4-kV mesa-type 6H-SiC p⁺-n diode with an ideal avalanche breakdown and without forward degradation was fabricated. The 6H-SiC substrates were grown on Lely crystals with no micropipes and only minimal defects. The 1.4-kV breakdown voltage, consistent with the ideal breakdown voltage calculated from the thickness and doping concentration of the drift layer was obtained..
173.	M. Nasir Khan, Shinichi Nishizawa, Kazuo Arai, Healing defects in SiC wafers by liquid-phase epitaxy in Si melts, Journal of Crystal Growth, 10.1016/S0022-0248(03)01177-1, 254, 1-2, 137-143, 2003.06, [URL], Silicon carbide epitaxial layers were grown by liquid-phase epitaxy on 6H-SiC-modified Lely crystals containing a high density of micropipes (MP) and other defects. The geometrical configuration of the seed crystals inside the crucible during LPE was such that the epitaxial layer growth occurred simultaneously on both the faces of the seed crystals. Layers in the range of 20-30μm thickness were deposited on both the faces of the crystals. X-ray diffraction, optical and scanning electron microscopy analyses were carried out to investigate these layers. It was found that dislocation and MP density in the substrate after LPE growth has been significantly reduced. Several MP were observed to decompose into non-hollow core dislocations. The growth centre associated with MP reduces in size in general and shifts to new centres due to the decomposition of the MP. As a result these new centres dominate the growing surfaces in LPE and make the healed MP completely invisible..
174.	西澤伸一, 加藤智久, 木藤泰男, 廣瀬富佐男, 小柳直樹, 山口博隆, 荒井和雄, 昇華法によるSiCバルク単結晶成長 : 数値解析の活用, 電子情報通信学会論文誌. C, エレクトロニクス = The transactions of the Institute of Electronics, Information and Communication Engineers. C, 86, 4, 334-341, 2003.04, 昇華法によるSiC単結晶成長は,2000℃を超える黒鉛るつぼで閉じられた閉鎖空間でのブラックボックスプロセスであり,これまで経験則に基づく技術開発が行われてきた.そのため,大口径化・高品質化に対して解決すべき技術課題が多数残されている.今回,数値解析を結晶成長炉内の可視化技術として適用し,実際の昇華法による結晶成長時の温度・昇華ガス濃度・応力分布の解析を行い,SiC単結晶品質の向上に資してきたので,その結果を報告する..
175.	K. Jeganathan, M. Shimuzu, H. Okumura, F. Hirose, Shinichi Nishizawa, Initial stage of GaN nucleation on √3 × √3 R 30°-Ga reconstructed 4H-SiC(0 0 0 1)_Si by molecular-beam epitaxy, Surface Science, 10.1016/S0039-6028(03)00016-5, 527, 1-3, 2003.03, [URL], Gallium nitride (GaN) initial nucleation kinetics by the influence of SiC(0 0 0 1)_Si surface structure has been investigated. The Ga induced √3×√3R30° and 3×3 surface reconstructions are found to be more efficacious for GaN growth. During the initial stage of GaN/4H-SiC(0 0 0 1)_Si growth by molecular-beam epitaxy, coherent polygon islands grow wide (∼40 nm) along the lateral directions. These coherent islands develop 2D growth through early coalescence as evidenced by the in situ reflection high-energy electron diffraction observation. The control of Ga-adatom migration and the adsorption of 1/3 and 1 monolayer (ML) of Ga-adatom govern the surface morphology of the GaN layers. The bulk surfaces of (1 × 1) and (2 × 1) introduces incoherent nuclei, resulting in a delay of GaN coalescence, exhibits rough growth front and poor surface morphology..
176.	Shinichi Nishizawa, Masahiro Hirata, Numerical simulation of thermal transpiration in Capacitance diaphragm gauge 隔膜真空計における熱遷移効果の数値解析, Journal of the Vacuum Society of Japan, 46, 3, 197-199, 2003.03, The Capacitance diaphragm gauge is one of the most important vacuum gauges in low and middle vacuum ranges. The difference of temperature between the sensor head and the vacuum chamber gives a non-linear sensitivity of the gauge due to thermal transpiration effect. This sensitivity depends not only on pressure but also gas species. It is supposed that under the same condition of gas-surface interaction, the sensitivity should be normalized by mean free path independently of gas species. However, the sensitivity normalized by mean free path also depends on gas species. In this study, by using DSMC method, the influence of gas-surface interaction on thermal transpiration was analyzed. In case of random reflection model, the sensitivity has non-linearity and depends on mean free path. On the other hand, in case of a perfectly elastic reflection model, the sensitivity is constant regardless mean free path. In case of complex reflection that is composed of random and elastic reflections, as increasing the elastic reflection component, the sensitivity decreases from that of random reflection to elastic reflection..
177.	Shinichi Nishizawa, Masahiro Hirata, Numerical simulation of thermal transpiration of capacitance diaphragm gauge 隔膜真空計における熱遷移現象の数値解析, Journal of the Vacuum Society of Japan, 45, 3, 119-122, 2003.03, The Capacitance diaphragm gauge (CDG) is one of the most important vacuum gauges in low and middle vacuum ranges. The difference of temperature between the sensor head and the vacuum chamber gives a non-linear sensitivity of the gauge depending on the pressure due to thermal transpiration effect. Change in the sensitivity of about 4% between molecular flow regime and viscous flow regime is significant for metrological use of the gauge. In this study, by using a DSMC method, pressure distribution in the connecting tube of the gauge was obtained under the pressure range from molecular flow regime to viscous flow regime with taking account of temperature distribution along the connecting tube. It was in good agreement with the pressure dependence of sensitivity obtained by static expansion system experimentally. Furthermore, influence of gas-surface interaction on the thermal transpiration was also discussed..
178.	M. Nasir Khan, Shinichi Nishizawa, Tomohisa Kato, Ryoji Kosugi, Kazuo Arai, Silicon carbide epitaxial layer growths on Acheson seed crystals from silicon melt, Materials Letters, 10.1016/S0167-577X(02)00783-8, 57, 2, 307-314, 2002.12, [URL], Silicon carbide epitaxial layer growth was carried out on both Si- and C-faces of the 6H-SiC Acheson seed crystals by a technique similar to that used for the sublimation growth of bulk single crystals of this material. High-resolution XRD (HRXRD) measurements showed the single crystalline structure for these grown layers. RHEED patterns confirmed that the grown layers are of single crystalline nature having (n×n) surface reconstruction. Raman spectroscopy showed the same polytype for the grown layers as that of the seed crystals. Atomic force and optical microscopy revealed smooth, uniform and mirror like surfaces for the grown layers. Step flow growth mechanism was observed on both Si- and C-faces of the seed crystal. The grown layers show similar characteristic features as that observed for the SiC layers grown by other techniques such as liquid phase epitaxy (LPE) and chemical vapor deposition (CVD). The technique used is a simple, viable and new alternative for growing SiC epitaxial layers..
179.	Shinichi Nishizawa, Masahiro Hirata, DSMC analysis of thermal transpiration of capacitance diaphragm gauge, Vacuum, 10.1016/S0042-207X(02)00212-9, 67, 3-4, 301-306, 2002.09, [URL], The capacitance diaphragm gauge (CDG) is one of the most important vacuum gauges in low and medium vacuum ranges. CDG has a non-linear sensitivity below 100Pa because of the temperature difference between the sensor head and the vacuum chamber, which is called thermal transpiration. This sensitivity depends on gas species and pressure. In this study, by using a direct simulation Monte Carlo (DSMC) method, pressure distribution in the connecting tube of the gauge was obtained under the pressure range from molecular flow regime to viscous flow regime (10^-2-10²Pa) taking account of the temperature distribution along the connecting tube. Furthermore, the pressure dependence of the sensitivity of the CDG was derived from the pressure difference between the hot and cold ends, and found to be in good agreement with the pressure dependence of sensitivity obtained by an empirical equation. The influence of gas-surface interaction on the thermal transpiration was also analyzed..
180.	Naoki Oyanagi, Shinichi Nishizawa, Kazuo Arai, A method of reducing micropipes in thin films by using sublimation growth, Materials Science Forum, 389-393, 1, 107-110, 2002.04, The micropipe termination by using a W or Pt thin film was demonstrated. A SiC single crystal was grown on the modified-Lely seed with W or Pt mask, by the sublimation method. The optical micrograph made it clear that a micropipe contained in seed crystal was terminated at the metal deposited interface. The effect of metal mask thickness on the termination efficiency was also studied..
181.	Tomohisa Kato, Naoki Oyanagi, Yasuo Kitou, Shin-ichi Nishizawa, Kazuo Arai, Dislocation constraint by etch-back process of seed crystal in SiC bulk crystal growth, Materials Science Forum, 389-393, 1, 111-114, 2002.04, Dislocation constraint in the growth of SiC crystal by the modified Lely method was studied. In SiC single crystal growth, the dislocations and defects generally propagate from the seed crystal surface. However, when the etch back on the seed crystal surface in the sublimation process was performed prior to growth, defects and dislocations propagation in the interface between the seed crystal and the grown crystal were reasonably suppressed. The switchover from the etch back to the growth could be performed without changing the heating condition during the initial process. We noticed that the density of the hollow defects called as micropipes in the grown crystal were decreased to 1/10 compared to that of the seed crystal used. We consider the etch back process of the seed crystal is an effective method for constraining the defects in the SiC crystal growth..
182.	Yasuo Kitou, Wook Bahng, Tomohisa Kato, Shinichi Nishizawa, Kazuo Arai, Flux-controlled sublimation growth by an inner guide-tube, Materials Science Forum, 389-393, 1, 83-86, 2002.04, The effect of the geometrical parameters of the inner structure of the crucible on the sublimation growth of bulk SiC was investigated. It was found that the gap between the seed crystal and the guide-tube was the important parameter for the single crystal growth separated from polycrystal. The growth rate ratio of the single/poly crystal increased up to 4. The broadening angle of the single crystal was controlled in the range of 0-30° by changing the taper angle of the guide-tube. The crystal quality in the periphery was improved compared with the crystal grown without the guide-tube. The growth process was discussed considering the flux flow of the sublimation gas..
183.	Naoki Oyanagi, Hirotaka Yamaguchi, Tomohisa Kato, Shinichi Nishizawa, Kazuo Arai, Growth and evaluation of high quality SiC crystal by sublimation method, Materials Science Forum, 389-393, 1, 87-90, 2002.04, High quality 6H-SiC single crystal was grown using the modified Lely method under pressure-controlled low-growth-rate conditions. The grown crystal contained no micropipes and its etch pit density was 4 × 10³ cm^-2. The presence of a Pendellösung fringe as revealed by section topography showed that the grown crystal was composed of a single domain. The relation between etch pits and defects is also discussed..
184.	M. Okamoto, R. Kosugi, Y. Tanaka, D. Takeuchi, S. Nakashima, Shinichi Nishizawa, K. Fukuda, H. Okushi, K. Arai, Homoepitaxial growth of 4H-SiC thin film below 1000°C by microwave plasma chemical vapor deposition, Materials Science Forum, 389-393, 1, 299-302, 2002.04, Microwave plasma chemical vapor deposition was performed aiming at low temperature homoepitaxial growth of 4H-SiC thin films. The growth rate of the deposited film depended strongly on the SiH₄ flow rate, and a smooth surface could not obtained at high SiH₄ flow rate. The surface morphology was also affected by the C/Si ratio. A high C/Si ratio was required to obtain smooth SiC films. Single crystalline 4H-SiC film growth has been achieved at a temperature as low as 970°C by growing under very high C/Si ratio (C/Si = 175) with a very low SiH₄ flow rate (0.004sccm)..
185.	Shinichi Nishizawa, Tomohisa Kato, Yasuo Kitou, Naoki Oyanagi, Kazuo Arai, Numerical simulation of heat and mass transfer in SiC sublimation growth, Materials Science Forum, 389-393, 1, 43-46, 2002.04, The numerical simulation of SiC sublimation growth was carried out. On the results of flux control growth with innerguide tube, the tube controls the thermal field inside a growth cavity, and makes it possible to grow single crystal without obstacle polycrystal. It was also cleared that the grown crystal shape strongly depends on the temperature distribution inside a growth cavity. On the results of in-process etching, it was pointed out that defects occurrence can be suppressed by taking care of temperature distribution on the initial growing surface. These results show that by controlling the thermal field inside a growth cavity, it is possible to control the macro and micro crystal quality such as grown crystal shape and defects, respectively..
186.	Fusao Hirose, Yasuo Kitou, Naoki Oyanagi, Tomohisa Kato, Shin Ichi Nishizawa, Kazuo Arai, Characterization of inclusions in SiC bulk crystals grown by modified lely method, Materials Science Forum, 10.4028/www.scientific.net/msf.389-393.75, 389-393, 1, 75-78, 2002.01, [URL], We have investigated two types of inclusions. They were a dendrite and a transparent inclusion, which have been seldom reported. The dendrite consisted of carbon, titanium and vanadium except for silicon. It should be carbide of titanium and vanadium. The titanium and vanadium might be incorporated from the source. By using a high purity source, it is possible to prevent generation of the dendrite. The transparent inclusion was observed in the SiC bulk crystal even in the growth with the chemical treated SiC source powder. A remarkable feature of the transparent inclusion was to have a small empty core. It was considered that the core might be a trace of Si droplet caused by C/Si ratio fluctuation of sublimated gas. Therefore, the C/Si ratio during the growth should be stabilized to prevent generation of the transparent inclusions..
187.	Tomohisa Kato, Shinichi Nishizawa, Kazuo Arai, Dislocation constraint by etch back process of seed crystal in the SiC sublimation growth, Journal of Crystal Growth, 10.1016/S0022-0248(01)01578-0, 233, 1-2, 219-225, 2001.11, [URL], Dislocation constraint in the growth of SiC crystal by the modified Lely method was studied. In SiC single crystal growth, the dislocations and defects generally propagate from the seed crystal surface. However, when the etch back on the seed crystal surface in the sublimation process was performed prior to growth, defects and dislocation propagation in the interface between the seed crystal and the grown crystal were suppressed reasonably. The switchover from the etch back to the growth could be performed without changing heating condition during the initial process. We noticed that the density of the hollow defects called as micropipes in the grown crystal were decreased to 1/10 compared to that of the seed crystal used. We consider the etch back process of the seed crystal as an effective method for constraining the defects in the SiC crystal growth..
188.	Hirotaka Yamaguchi, Shinichi Nishizawa, Tomohisa Kato, Naoki Oyanagi, Sadafumi Yoshida, Kazuo Arai, In-situ X-ray topography on crystal growth of silicon carbide, Yosetsu Gakkai Shi/Journal of the Japan Welding Society, 70, 6, 23-27, 2001.09.
189.	西澤伸一, 平田正紘, 隔膜真空計における熱遷移現象の数値解析, 真空, 44, 3, 328-328, 2001.03.
190.	NISHIZAWA S., New crucible design for SiC single crystal growth by sublimation, Mat. Res. Soc. Symp., 640, H151-156, 2001.01.
191.	T. Kato, N. Oyanagi, H. Yamaguchi, Shinichi Nishizawa, K. Arai, Defect analysis of SiC sublimation growth by the in-situ X-ray topography, Materials Science Forum, 353-356, 295-298, 2001.01, Silicon carbide (SiC) single crystal growth was studied by the in-situ observation using x-ray topographic technique. Occurrence and dynamics of defects, dislocations were observed in a real time display and captured as topographic images during sublimation growth (modified Lely method) of SiC crystals. From the analysis of these topographic images, high-density of dislocations and typical large defects, such as micropipes, domain boundaries and macrodefects were investigated. On the basis of our in-situ observation and analysis, we argue that dislocation and nucleation control on the seed crystal during initial growth are of prime importance for producing high quality SiC crystals..
192.	Tomohisa Kato, Naoki Oyanagi, Hirotaka Yamaguchi, Shinichi Nishizawa, M. Nasir Khan, Yasuo Kitou, Kazuo Arai, In-situ observation of silicon carbide sublimation growth by X-ray topography, Journal of Crystal Growth, 10.1016/S0022-0248(00)00958-1, 222, 3, 579-585, 2001.01, [URL], The crystal growth of silicon carbide (SiC) was studied by in-situ observation using X-ray topographic technique. The growth was performed by a sublimation method (the modified Lely method). The generation and evolution of defects and dislocations were observed as topographs in a real-time display. Defects and dislocations analyzed by the in-situ technique were compared with the postprocess observations using optical microscopy and X-ray topography. Dislocations in the initial growth layer and typical large defects, such as micropipes, macrodefects and domain boundaries, were investigated. We showed the possibility that large defects are induced by the accumulation of dislocations in the initial growth layer. Moreover, we observed that inhomogeneous growth starting in parts on the seed surface during the initial growth results in new defects in the growing crystal. We discuss the importance of dislocation and nucleation control on the SiC seed crystal during the initial growth, on the basis of facts and findings obtained by the in-situ as well as postprocess observations..
193.	M. Nasir Khan, Shinichi Nishizawa, Wook Bahng, Kazuo Arai, Liquid-phase epitaxy on 6H-SiC Acheson seed crystals in closed vessel, Journal of Crystal Growth, 10.1016/S0022-0248(00)00733-8, 220, 1-2, 75-81, 2000.11, [URL], SiC epitaxial growth was carried out on 6H-SiC Acheson seed crystals in liquid phase using a closed carbon crucible. The growth was carried out in the temperature range of 1500-1700 °C. The geometrical configurations of seed crystals inside the crucible were specific, such that epitaxial layer growth occurred simultaneously on both faces of the same seed crystal under the same growth conditions. Growth rates as high as 20-30 μm/h have been achieved. The growth rate and surface morphologies observed after the growth indicated that the temperature gradient on the seed crystal faces plays a dominant role for the growth mechanism of the epitaxial layers. The convection within the solvent caused by the temperature gradient enhances the mass transport to the growing layer faces enhancing the growth rate and also results in a better surface morphology of the epitaxial grown layers..
194.	T. Henkel, Y. Tanaka, N. Kobayashi, Shinichi Nishizawa, S. Hishita, Beryllium implantation doping of silicon carbide, Materials Science Forum, 338, 2000.05, Structural properties of beryllium implanted silicon carbide have been investigated by secondary ion mass spectrometry, Rutherford backscattering/channeling, and Raman spectroscopy. Strong redistribution of beryllium has been found after a post-implantation anneal step at temperatures between 1300 °C and 1700 °C. The use of a pre-anneal process at 1000 °C before the high-temperature treatment as well as graphite as a surface encapsulant do not efficiently suppress redistribution of Be in the SiC lattice. The crystalline state of the implanted and annealed material is well recovered after annealing at temperatures above 1400 °C..
195.	Wook Bahng, Yasuo Kitou, Shinichi Nishizawa, Hirotaka Yamaguchi, Muhammad Nasir Khan, Naoki Oyanagi, Kazuo Arai, Shigehiro Nishino, Enlargement of SiC single crystal Enhancement of lateral growth using tapered graphite lid, Materials Science Forum, 338, 2000.05, We investigated the rapid enlargement of SiC single crystal during physical vapor transport growth by enhancing the lateral growth. The degrees of enlargement of the single crystals grown on the newly developed graphite lid were larger than those of crystals grown on the conventional one. Using a cone-shaped platform, the polycrystals grown around the single crystal could assist the lateral growth of single crystal. There was no significant difference between the central region and the enlarged region as far as the micropipe density was considered. The dependence of the broadening angle (β) of the single crystal on the taper angle (θ) of the cone-shaped platform was also investigated and an optimum angle at a given growth condition was found..
196.	Yasuo Kitou, Wook Bahng, Shinichi Nishizawa, Shigehiro Nishino, Kazuo Arai, Pressure effect in sublimation growth of bulk SiC, Materials Science Forum, 338, 2000.05, The effect of growth pressure on the impurity incorporation as well as on the crystal quality was investigated in sublimation growth of a bulk SiC single crystal. The growth pressure was varied within the range of 1-100 Torr and it was found that many voids or precipitates were generated in the grown crystals and the Aluminum (Al) impurity incorporation increased during the Si-face growth when the growth pressure decreased. The pressure effect on the Al impurity incorporation with the change of step structure was discussed..
197.	Shinichi Nishizawa, Yasuo Kitou, Wook Bahng, Naoki Oyanagi, Muhammad Nasir Khan, Kazuo Arai, Shape of SiC bulk single crystal grown by sublimation, Materials Science Forum, 338, 2000.05, Numerical simulation of sublimation SiC bulk single crystal growth was performed. Electromagnetic and temperature fields in a growth furnace were analyzed numerically. The relation between grown crystal shape and temperature distribution in a growth cavity was discussed. It is pointed out that the crystal shape has a close relationship with temperature distribution. By modifying the crucible design and temperature distribution in a growth cavity, it is possible to enhance the enlargement of grown crystal, and also possible to keep grown surface flat..
198.	Naoki Oyanagi, Shinichi Nishizawa, Tomohisa Kato, Hirotaka Yamaguchi, Kazuo Arai, SiC single crystal growth rate measurement by in-situ observation using the transmission X-ray technique, Materials Science Forum, 338, 2000.05, The growth rate of SiC bulk single crystal by sublimation was measured in real time by using the transmission X-ray technique. The growth rate obtained by transmission X-ray intensity corresponds to the growth rate measured by nitrogen marker. The growth rate increases as the growth temperature increases and as pressure decreases. While taking into account the pressure balance between the surrounding pressure and vapor pressures of seed and source, the growth rate can be calculated by mass flux from source to seed..
199.	T. Henkel, G. Ferro, Shinichi Nishizawa, H. Pressler, Y. Tanaka, H. Tanoue, N. Kobayashi, Structural characterization of silicon carbide etched by using a combination of ion implantation and wet chemical etching, Materials Science Forum, 338, 2000.05, Silicon carbide has been etched using a combination of high-dose ion implantation and wet chemical etching. Structural properties with respect to the remaining damage after etching have been studied using atomic force microscopy, Rutherford backscattering/channeling, and Raman spectroscopy. No significant deterioration of the crystal quality has been found after the etching process. Moreover, the as-etched surface is characterized by a lower roughness compared to virgin material. The results demonstrate that this etching method can be used for the fabrication of contacts on silicon carbide surfaces..
200.	Muhammad Nasir Khan, Shinichi Nishizawa, Wook Bahng, Kazuo Arai, Temperature gradient effect on SiC epitaxy in liquid phase, Materials Science Forum, 338, 2000.05, Epitaxial growth of 6H-SiC was carried out on 6H-SiC Acheson seed crystals in the silicon melt using closed carbon crucible. The growth was carried out in the temperature range 1500-1700 °C. The geometry was specific one, such that epitaxial layer growth occurred simultaneously on both faces of seed crystal under similar growth conditions. We have measured the growth rate and studied the surface morphology of these grown layers. The temperature gradient within the melt seems to play a dominant role in the growth mechanism in liquid phase and also results in a better surface morphology of the grown layers..
201.	村上寛, 西沢伸一, 町田和雄, 薄膜基板温度観察装置の試作, 真空, 43, 3, 430-430, 2000.03.
202.	BAHNG W., Rapid enlargement of SiC single crystal using a cone-shaped platform, J. Crystal Growth, 10.1016/S0022-0248(99)00754-X, 209, 4, 767-772, 2000.02, [URL].
203.	H. Yamaguchi, Shinichi Nishizawa, T. Kato, N. Oyanagi, W. Bahng, S. Yoshida, K. Arai, Y. Machitani, T. Kikuchi, In situ x-ray topography of silicon carbide during crystal growth by sublimation method, Review of Scientific Instruments, 10.1063/1.1150698, 71, 7, 2829-2832, 2000.01, [URL], We have developed an instrument for real-time observation of silicon carbide (SiC) crystal during the sublimation growth process by x-ray topography. It is constructed by combining an x-ray goniometer and a crystal-growth chamber. The vertical goniometer consists of three circles, an α circle for the x-ray source, a β circle for the detector, and a φ circle for the azimuthal rotation of the sample. The growing crystal boule is set at the center of the goniometer glued on a crucible lid. Transmission topographs are taken using an asymmetric (1011) reflection with the scattering angle 2 θ_B - β - α from the (0001)-oriented boule. A rotating-anode 18 kW generator with a molybdenum target is employed as the x-ray source. Topographs are observed by a direct imaging system using a charge-coupled device camera. Incident and scattered x-ray beams pass through beryllium windows mounted on the bottom and top flanges of the crystal-growth chamber, respectively. The crucibles are also designed for in situ measurements so that the x-ray beam path is separated from the source materials. The in situ topographs demonstrated the movement of micropipes and other defects during the crystal growth..
204.	Tomohisa Kato, Naoki Oyanagi, Hirotaka Yamaguchi, Yukio Takano, Shinichi Nishizawa, Kazuo Arai, In-situ observation of SiC bulk single crystal growth by X-ray topography, Materials Science Forum, 338, 2000.01, We report here for the first time on the in-situ observations for SiC bulk single crystal growth by x-ray topographic technique. Occurrence and dynamic observation of the defects such as micropipes and domain boundaries during SiC crystal growth by the modified Lely method was investigated in a real time display. The in-situ observation was considered to contribute for optimizing the growth conditions and to interpret the mechanism of defects and dislocations formation..
205.	H. Yamaguchi, N. Oyanagi, T. Kato, Y. Takano, Shinichi Nishizawa, W. Bahng, S. Yoshida, K. Arai, X-ray topographic study of SiC crystal at high temperature, Materials Science Forum, 338, 2000.01, We have developed an instrument for in-situ X-ray topography during crystal growth of silicon carbide (SiC). A vertical X-ray goniometer is combined with a furnace for sublimation growth. A high-power X-ray source and a TV imaging system using a CCD camera make possible to display the behaviors of defects in SiC crystal inside crucible. For a demonstration of the developed instrument, we show the topographs of a SiC crystal at high temperature. The topographs show distinct deformations developing with increasing temperature..
206.	西澤伸一, 山口博隆, 加藤智久, X線トポグラフィーによるSiC単結晶成長その場観察装置の開発, 電子技術総合研究所彙報, 63, 8, 305-310, 1999.09.
207.	山口博隆, 西澤伸一, 荒井和雄, SiC単結晶成長のX線トポグラフィーその場観察装置の開発, 電総研ニュース, 595, 2-5, 1999.08.
208.	H. Yamaguchi, Shinichi Nishizawa, W. Bahng, K. Fukuda, S. Yoshida, K. Arai, Y. Takano, Reflection and transmission X-ray topographic study of a SiC crystal and epitaxial wafer, Materials Science and Engineering B: Solid-State Materials for Advanced Technology, 61-62, 221-224, 1999.07, Defects in commercially available silicon carbide (SiC) wafers have been investigated by X-ray topography and optical microscopy. Dots appearing in transmission topographs are identified as a screw dislocation running through the [0001] direction by a comparative observation of the reflection topographs from the front and rear sides. In the peripheral region, these dots appear with high density and accompany large strain fields at the edge, which are related with the dislocations in the basal plane emanating from the dots and connecting them and large holes with diameters of about 10-20 μm opening at the epilayer surface. These large strain fields are considered to originate from the large Burgers vector associating with the screw dislocations..
209.	Taketoshi Hibiya, Shin Nakamura, Kusuhiro Mukai, Zheng Gang Niu, Nobuyuki Imaishi, Shinichi Nishizawa, Shin Ichi Yoda, Masato Koyama, Interfacial phenomena of molten silicon Marangoni flow and surface tension, Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences, 10.1098/rsta.1998.0195, 356, 1739, 899-909, 1998.04, [URL], Temperature oscillation due to the oscillatory Marangoni flow was measured for a molten half-zone silicon column (10 mm high and 10 mm in diameter with a temperature difference of 150 K between the upper and lower solid-liquid interfaces) under microgravity by using fine thermocouples. The flow is in a hypercritical condition; that is, the Marangoni number is estimated to be over 10 000. The structure of the Marangoni instability is two-fold symmetry for the small aspect ratio (height/radius) Γ of 1 and one-fold symmetry for the melt with Γ of 2. The surface tension of molten silicon was measured by a sessile drop method in carefully controlled ambient atmospheres with various oxygen partial pressures from 4 × 10^-22 to 6 × 10^-19 MPa. These measurements showed that the surface tension and its temperature coefficient showed a marked dependence on oxygen partial pressure. Accordingly the effect of oxygen partial pressure on the Marangoni flow should be made clear. Moreover, Marangoni flow at the flat surface, which corresponds to the flow for the Czochralski growth system, should also be studied..
210.	Shin Nakamura, Taketoshi Hibiya, Koichi Kakimoto, Nobuyuki Imaishi, Shinichi Nishizawa, Akira Hirata, Kusuhiro Mukai, Shin Ichi Yoda, Tomoji S. Morita, Temperature fluctuations of the Marangoni flow in a liquid bridge of molten silicon under microgravity on board the TR-IA-4 rocket, Journal of Crystal Growth, 10.1016/S0022-0248(97)00440-5, 186, 1-2, 85-94, 1998.03, [URL], Temperature fluctuation measurements in a liquid bridge of molten silicon, which shows the Marangoni flow in highly super-critical condition, are performed in a half-zone configuration under microgravity on board a TR-IA-4 rocket and on the ground. In the microgravity experiment, two types of temperature oscillation are observed during the melting process of silicon and in the cylindrical half-zone melt. The former oscillation, which has a frequency of about 0.1 Hz during the melting process, has an antiphase correlation of temperature oscillation measured in thermocouples separated by 90° azimuthal angles. The latter oscillation in the cylindrical liquid bridge has no remarkable frequency; however, it tends to have the antiphase correlation in between thermocouples with 180° azimuthal angles. In the ground experiment, temperature fluctuations have a characteristic frequency of 0.2 Hz and there is an antiphase correlation of temperatures in thermocouples with 180° azimuthal angles by using the slender melt zone..
211.	西澤伸一, 宇宙空間での材料作製のためのシミュレーション, シミュレーション, 16, 2, 118-121, 1997.06, In space, it could be possible to make high quality, large and new functional materials. For the material processing such as melt growth of materilas for electrical devices and oxides, it is very important to understand and control the convective phenomena in melt. In this point of view, Marangoni convection in a liquid bridge which simulates the half floating zone was observed under microgravity conditions during parabolic filght. The experimental resutls was compared with that of numerical simulations. The developing processes of flow filed and temperature field were made clear. Furthermore, it coud be possible to estimate the pehnomena which might be happened as long time passed by numerical simulations. It means that numerical simulation is very usufel for developing the materila processing in space..
212.	西澤伸一, 3rd China-Japan Workshop on Microgravity Science, JASMA : Journal of the Japan Society of Microgravity Application, 14, 1, 95-96, 1997.02.
213.	Y. L. Yao, J. Z. Shu, J. C. Xie, F. Liu, W. R. Hu, A. Hirata, Shinichi Nishizawa, M. Sakurai, Transition of oscillatory floating half zone convection from Earth's gravity to microgravity, International Journal of Heat and Mass Transfer, 10.1016/S0017-9310(96)00309-2, 40, 11, 2517-2524, 1997.01, [URL], Oscillatory features of floating half zone convection were experimentally studied by using the drop shaft facility of Japan Microgravity Center which supported microgravity period of 10 s. Coordinated measurements including free surface deformation and oscillation, temperature and flow pattern in both 1-g and micro-g environment were obtained. The oscillatory frequency and amplitude in micro-g condition were lower and larger than the ones in 1-g condition, respectively. The results gave, at first time, the oscillatory features such as free surface wave in micro-g, coordinated measurements of more than two physical quantities in the micro-g, and transition of thermocapillary oscillatory convection from 1-g to micro-g..
214.	Wen Rui Hu, Akira Hirata, Shinichi Nishizawa, Diffusion dominated process for the crystal growth of a binary alloy, Journal of Crystal Growth, 10.1016/S0022-0248(96)00386-7, 169, 2, 380-392, 1996.11, [URL], The pure diffusion process has been often used to study the crystal growth of a binary alloy in the microgravity environment. In the present paper, a geometric parameter, the ratio of the maximum deviation distance of curved solidification and melting interfaces from the plane to the radius of the crystal rod, was adopted as a small parameter, and the analytical solution was obtained based on the perturbation theory. The radial segregation of a diffusion dominated process was obtained for cases of arbitrary Peclet number in a region of finite extension with both a curved solidification interface and a curved melting interface. Two types of boundary conditions at the melting interface were analyzed. Some special cases such as infinite extension in the longitudinal direction and special range of Peclet number were reduced from the general solution and discussed in detail..
215.	西澤伸一, 石山修, 澤岡昭, 2次元矩形容器内の温度差・濃度差マランゴニ対流現象, JASMA : Journal of the Japan Society of Microgravity Application, 13, 4, 304-304, 1996.10.
216.	Akira Hirata, Shinichi Nishizawa, Motoharu Noguchi, Masato Sakurai, Shouichi Yasuhiro, Nobuyuki Imaishi, Marangoni convection in a liquid bridge under microgravity conditions during parabolic flight, Journal of Chemical Engineering of Japan, 10.1252/jcej.27.65, 27, 1, 65-71, 1994.01, [URL], Marangoni convection in a silicone oil liquid bridge under microgravity conditions during parabolic flight was observed. The developing process of axis-symmetric laminar Marangoni convection was studied experimentally and numerically. To reach a steady state of the temperature field, much more time was needed than to reach a steady state of the velocity field. The effects of initial temperature conditions inside a liquid bridge, heat transfer across the free surface, and temperature dependence of viscosity on both velocity and temperature field were studied numerically..
217.	Akira Hirata, Shinichi Nishizawa, Masato Sakurai, Nobuyuki Imaishi, Interfacial Contamination Caused by Water on Marangoni Convection in a Silicone Oil Liquid Bridge, Journal of Chemical Engineering of Japan, 10.1252/jcej.26.754, 26, 6, 754-756, 1993.12, [URL].
218.	NISHIZAWA Shin-ichi, HIRATA Akira, MOMENTUM, WITH HEAT AND MASS TRANSFER THROUGH GAS-LIQUID INTERFACE WITH ACCELERATED INTERFACIAL VELOCITY, Journal of chemical engineering of Japan, 10.1252/jcej.26.649, 26, 6, 649-655, 1993.03, [URL], Effects of interfacial velocity on interfacial momentum, heat and mass transfer through a gas-liquid interface were quantitatively investigated. The rates of momentum, heat and mass transfer depend not only on the magnitude of the interfacial velocity but also on the change of acceleration in interfacial velocity. In addition, by considering the interfacial tension gradient to be the cause of interfacial acceleration, the effect of the interfacial tension gradient on interfacial velocity, interfacial momentum, heat and mass transfer were also quantitatively investigated. Both the interfacial velocity and the rates of momentum, heat and mass transfer depend not only on the magnitude of the interfacial tension gradient but also on the change of interfacial tension..
219.	A. Hirata, Shinichi Nishizawa, Y. Okano, Effect of interfacial tension gradient on momentum and mass transfer through a moving interface of single drops, Unknown Host Publication Title, 1992.01, The effect of interfacial tension gradient on interphase momentum and mass transfer through a moving interface of single drops was studied theoretically. Approximate equations for interfacial velocity, drag coefficient and Sherwood number were proposed with taking account of the interfacial tension gradient. The results of this theoretical study showed good agreement with previous experimental results. (A).
220.	Akira Hirata, Yasunori Okano, Shinichi Nishizawa, Numerical study of transport phenomena through fluid-liquid interfaces, Bulletin of Centre for Informatics (Waseda University), 8, 9-22, 1988.09, The effect of interfacial velocity and interfacial tension gradient on momentum, heat and mass transfer through fluid-liquid interfaces was studied numerically. The effect of interfacial tension gradient on the interfacial velocity was clarified. The results obtained in this study can explain quantitatively the previous experimental results on the interfacial acceleration due to the interfacial tension gradient. Interfacial contamination and interfacial turbulent phenomena were respectively related to the enhancement and suppression of the mobility of interface. Effects of physical properties, bulk flow speed and Prandtl number on starting points of interfacial turbulence were also discussed..

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