Kyushu University [Tanimoto Teruo (Associate Professor) Faculty of Information Science and Electrical Engineering, Department of Advanced Information Technology]

Tanimoto Teruo

Last modified date：2022.06.28

Associate Professor / Department of Advanced Information Technology
Faculty of Information Science and Electrical Engineering

2 Academic Activities

Graduate School

Undergraduate School

工学部

理学部

Other Organization

System LSI Research Center

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Homepage

Academic Degree

Ph.D.

Field of Specialization

Computer architecture

ORCID(Open Researcher and Contributor ID)

0000-0002-9068-0972

Outline Activities

TBD

Research

Research Interests

Research for a new processor design method
keyword : Critical path analysis,High level synthesis,FPGA,ASIC
2018.04～2021.03.
Hardware-Software co-design for secure computer systems
keyword : Security,Hardware-Software co-design
2018.04～2021.03.
Quantum Computer Architecture
keyword : Quantum Computer,System Architecture
2018.10～2021.03.

Academic Activities

Papers

Show All Papers >>

1.	Teruo Tanimoto, Takatsugu Ono, and Koji Inoue, Critical Path based Microarchitectural Bottleneck Analysis for Out-of-Order Execution, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E102-A, No.6, pp.-. Jun. 2019. (in press), 2019.06.

Presentations

Show All Presentations >>

1.	Ilkwon Byun, Junpyo Kim, Dongmoon Min, Ikki Nagaoka, Kosuke Fukumitsu, Iori Ishikawa, Teruo Tanimoto, Masamitsu Tanaka, Koji Inoue, and Jangwoo Kim, XQsim: Modeling Cross-Technology Control Processors for 10+K Qubit Quantum Computers, ACM/IEEE International Symposium on Computer Architecture, 2022.06.
2.	Koki Ishida, Il-Kwon Byun, Ikki Nagaoka, Kosuke Fukumitsu, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Jangwoo Kim, and Koji Inoue, SuperNPU: Architecting an Extremely Fast Neural Processing Unit Using Superconducting Logic Devices, The 53rd IEEE/ACM International Symposium on Microarchitecture (MICRO-53), 2020.10.
3.	Koki Ishida, Masamitsu Tanaka, Ikki Nagaoka, Takatsugu Ono, Satoshi Kawakami, Teruo Tanimoto, Akira Fujimaki, and Koji Inoue, 32 GHz 6.5 mW Gate-Level-Pipelined 4-bit Processor using Superconductor Single-Flux-Quantum Logic, 2020 Symposia on VLSI Technology and Circuits, 2020.06.

Membership in Academic Society

Educational

Educational Activities

TBD

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