Kyushu University Academic Staff Educational and Research Activities Database
List of Papers
Tanimoto Teruo Last modified date:2023.06.28

Associate Professor / Department of Advanced Information Technology / Faculty of Information Science and Electrical Engineering

1. Kuan Yi Ng, Aalaa M. A. Babai, Teruo Tanimoto, Satoshi Kawakami, and Koji Inoue, Empirical Power-Performance Analysis of Layer-wise CNN Inference on Single Board Computers, Journal of Information Processing, 2023.08.
2. Ikki Nagaoka, Ryota Kashima, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Taro Yamashita, Koji Inoue, and Akira Fujimaki, 50-GFLOPS Floating-Point Adder and Multiplier Using Gate-Level-Pipelined Single-Flux-Quantum Logic with Frequency-Increased Clock Distribution, IEEE Transactions on Applied Superconductivity, 33, 4, Art no. 1302711, 2023.06.
3. Koki Ishida, Il-Kwon Byun, Ikki Nagaoka, Kosuke Fukumitsu, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Jangwoo Kim, and Koji Inoue, Superconductor Computing for Neural Networks, IEEE Micro, vol.41, no.3, pp.19–26, 2021.05, The superconductor single-flux-quantum (SFQ) logic family has been recognized as a promising solution for the post-Moore era, thanks to the ultrafast and low-power switching characteristics of superconductor devices. Researchers have made tremendous efforts in various aspects, especially in device and circuit design. However, there has been little progress in designing a convincing SFQ-based architectural unit due to a lack of understanding about its potentials and limitations at the architectural level. This article provides the design principles for SFQ-based architectural units with an extremely high-performance neural processing unit (NPU). To achieve our goal, we developed and validated a simulation framework to identify critical architectural bottlenecks in designing a performance-effective SFQ-based NPU. We propose SuperNPU, which outperforms a conventional state-of-the-art NPU by 23 times in terms of computing performance and 1.23 times in power efficiency even with the cooling cost of the 4K environment..
4. Teruo Tanimoto, Takatsugu Ono, and Koji Inoue, Critical Path based Microarchitectural Bottleneck Analysis for Out-of-Order Execution, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E102-A, No.6, pp.-. Jun. 2019. (in press), 2019.06.