九州大学-研究者情報 [川上哲志 (准教授) システム情報科学研究院情報エレクトロニクス部門]

川上哲志（かわかみさとし）

データ更新日：2024.04.03

准教授　／　システム情報科学研究院情報エレクトロニクス部門

原著論文

1.	Satoshi Kawakam, Research on optical computing system architecture for simple recurrent neural networks, Impact, 2024.01.
2.	中村徹舟 , 宮村信 , 井上弘士 , 川上哲志 , 阪本利司 , 多田宗弘 , 谷本輝夫, 極低温不揮発FPGAを対象とした誤り耐性量子コンピュータ向け表面符号復号器のRTL設計, IPSJ Transaction ACS, 2024.08.
3.	Satoshi Kawakam, Yusuke Ohtsubo, Koji Inoue and Masamitsu Tanaka, Late Breaking Results: Single Flux Quantum based Brownian Circuits for Ultra-Low-Power Computing, In Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024.03.
4.	Keisuke Takano, Takeaki Yajima and Satoshi Kawakami, Design of The Ultra-Low-Power Driven VMM Configurations for uW Scale IoT Devices, In Proceedings of the IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 2023.12.
5.	Tesshu Nakamura, Makoto Miyamura, Koji Inoue, Satoshi Kawakami, Toshitsugu Sakamoto, Munehiro Tada and Teruo Tanimoto, Dynamically Reconfigurable Decoder Architecture for Adaptive Error Correction Using Cryogenic Non-Volatile FPGAs, Proceedings of the Workshop: I too can Quantum (I2Q), 2023.06.
6.	Masamitsu Tanaka, Ikki Nagaoka, Satoshi Kawakami, Teruo Tanimoto, Takatugu Ono, Koji Inoue, and Akira Fujimaki, Gate-level-pipeline SFQ circuits for high-throughput floating-point arithmetic, Proceedings of the European Conference on Applied Superconductivity (EUCAS), 2023.09.
7.	Kuan Yi Ng, Aalaa M.A. Babai, Teruo Tanimoto, Satoshi Kawakami and Koji Inoue, Empirical Power-Performance Analysis of Layer-wise CNN Inference on Single Board Computers, IPSJ Transaction ACS, 2023.08.
8.	Ikki Nagaoka, Ryota Kashima, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Taro Yamashita, Koji Inoue, and Akira Fujimaki, 50-GFLOPS Floating-Point Adder and Multiplier Using Gate-Level-Pipelined Single-Flux-Quantum Logic with Frequency-Increased Clock Distribution, IEEE Transactions on Applied Superconductivity, 2023.04.
9.	Eito Sato, Koji Inoue, Satoshi Kawakami, Design and Analysis of a Nano-photonic Processing Unit for Low-Latency Recurrent Neural Network Applications, The IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022.12.
10.	Takumi Inaba, Takatsugu Ono, Koji Inoue, Satoshi Kawakami, A Hybrid Opto-Electrical Floating-point Multiplier, The IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022.12.
11.	Satoshi Matsushita, Teruo Tanimoto, Satoshi Kawakami, Takatsugu Ono, Koji Inoue, An Edge Autonomous Lamp Control with Camera Feedback, The IEEE World Forum on Internet of Things, 2022.10.
12.	Kuan Yi Ng, Aalaa M.A. Babai, Satoshi Kawakami, Teruo Tanimoto, Koji Inoue, Layer-wise power/performance analysis for single-board CNN inference, The cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming, 2022.06.
13.	Kuan Yi Ng, Aalaa M.A. Babai, Teruo Tanimoto, Satoshi Kawakami and Koji Inoue, Empirical Power-Performance Analysis of Layer-wise CNN Inference on Single Board Computers, IPSJ Transaction ACS , 2022.06.
14.	Iori Ishikawa, Koki Ishida, Masamitsu Tanaka, Ikki Nagaoka, Satoshi Kawakami, Teruo Tanimoto, Akira Fujimaki, Koji Inoue, Design of Variable Bit-Width Arithmetic Unit Using Single Flux Quantum Device, IEEE International Symposium on Circuits & Systems, 2022.05.
15.	Koki Ishida, Ilkwon Byun, Ikki Nagaoka, Kousuke Fukumitsu, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Jangwoo Kim, and Koji Inoue, Superconductor Computing for Neural Networks, IEEE Micro, 2021.06.
16.	Koki Ishida, Ilkwon Byun, Ikki Nagaoka, Kousuke Fukumitsu, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Jangwoo Kim, and Koji Inoue, Architecting an Extremely Fast Neural Processing Unit Using Superconducting Logic Devices, IEEE/ACM International Symposium on Microarchtecture, 2020.10.
17.	Koki Ishida, Masamitsu Tanaka, Ikki Nagaoka, Takatsugu Ono, Satoshi Kawakami, Teruo Tanimoto, Akira Fujimaki and Koji Inoue, 32 GHz 6.5 mW Gate-Level-Pipelined 4-bit Processor using Superconductor Single-Flux-Quantum Logic, IEEE 2020 Symposia on VLSI Technology and Circuits, 2020.06.
18.	Teruo Tanimoto, Shuhei Matsuo, Satoshi Kawakami, Yutaka Tabuchi, Masuo Hirokawa and Koji Inoue, Practical Error Modeling Toward Realistic NISQ Simulation, the Quantum Computing Workshop (QCW) in conjunction with the IEEE Computer Society Annual Symposium on VLSI, 2020.06.
19.	Teruo Tanimoto, Shuhei Matsuo, Satoshi Kawakami, Yutaka Tabuchi, Masuo Hirokawa and Koji Inoue, How many trials do we need for reliable NISQ computing?, the Quantum Computing Workshop (QCW) in conjunction with the IEEE Computer Society Annual Symposium on VLSI, 2020.06.
20.	Keitaro Oka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Inoue Koji, Enhancing a manycore-oriented compressed cache for GPGPU, Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, 22-31, 2020.01, GPUs can achieve high performance by exploiting massive-thread parallelism. However, some factors limit performance on GPUs, one of which is the negative effects of L1 cache misses. In some applications, GPUs are likely to suffer from L1 cache conflicts because a large number of cores share a small L1 cache capacity. A cache architecture that is based on data compression is a strong candidate for solving this problem as it can reduce the number of cache misses. Unlike previous studies, our data compression scheme attempts to exploit the value locality existing within not only intra cache lines but also inter cache lines. We enhance the structure of a last-level compression cache proposed for general purpose manycore processors to optimize against shared L1 caches on GPUs. The experimental results reveal that our proposal outperforms the other compression cache for GPUs by 11 points on average..
21.	Ken Ichi Kitayama, Masaya Notomi, Makoto Naruse, Koji Inoue, Satoshi Kawakami, Atsushi Uchida, Novel frontier of photonics for data processing-Photonic accelerator, APL Photonics, 10.1063/1.5108912, 4, 9, 2019.09, [URL], In the emerging Internet of things cyber-physical system-embedded society, big data analytics needs huge computing capability with better energy efficiency. Coming to the end of Moore's law of the electronic integrated circuit and facing the throughput limitation in parallel processing governed by Amdahl's law, there is a strong motivation behind exploring a novel frontier of data processing in post-Moore era. Optical fiber transmissions have been making a remarkable advance over the last three decades. A record aggregated transmission capacity of the wavelength division multiplexing system per a single-mode fiber has reached 115 Tbit/s over 240 km. It is time to turn our attention to data processing by photons from the data transport by photons. A photonic accelerator (PAXEL) is a special class of processor placed at the front end of a digital computer, which is optimized to perform a specific function but does so faster with less power consumption than an electronic general-purpose processor. It can process images or time-serial data either in an analog or digital fashion on a real-time basis. Having had maturing manufacturing technology of optoelectronic devices and a diverse array of computing architectures at hand, prototyping PAXEL becomes feasible by leveraging on, e.g., cutting-edge miniature and power-efficient nanostructured silicon photonic devices. In this article, first the bottleneck and the paradigm shift of digital computing are reviewed. Next, we review an array of PAXEL architectures and applications, including artificial neural networks, reservoir computing, pass-gate logic, decision making, and compressed sensing. We assess the potential advantages and challenges for each of these PAXEL approaches to highlight the scope for future work toward practical implementation..
22.	川上哲志, 小野貴継, 井上弘士, 納富雅也, ナノフォトニック・ニューラルネットワークアクセラレータ向け統合評価環境, 電子情報通信学会論文誌, J102-A, No.6, 2019.06.
23.	Satoshi Kawakami, Takatsugu Ono, Toshiyuki Ohtsuka, Inoue Koji, Parallel precomputation with input value prediction for model predictive control systems, IEICE Transactions on Information and Systems, 10.1587/transinf.2018PAP0003, E101D, 12, 2864-2877, 2018.12, [URL], We propose a parallel precomputation method for real-time model predictive control. The key idea is to use predicted input values produced by model predictive control to solve an optimal control problem in advance. It is well known that control systems are not suitable for multi- or many-core processors because feedback-loop control systems are inherently based on sequential operations. However, since the proposed method does not rely on conventional thread-/data-level parallelism, it can be easily applied to such control systems without changing the algorithm in applications. A practical evaluation using three real-world model predictive control system simulation programs demonstrates drastic performance improvement without degrading control quality offered by the proposed method..
24.	Satoshi Kawakami, Akihito Iwanaga, Inoue Koji, Many-core acceleration for model predictive control systems, 1st International Workshop on Many-Core Embedded Systems, MES 2013, in Conjunction with the 40th Annual IEEE/ACM International Symposium on Computer Architecture, ISCA 2013, 10.1145/2489068.2489071, 17-24, 2013.07, [URL], This paper proposes a novel many-core execution strategy for real-time model predictive controls. The key idea is to exploit predicted input values, which are produced by the model predictive control itself, to speculatively solve an op- timal control problem. It is well known that control appli- cations are not suitable for multi- or many-core processors, because feedback-loop systems inherently stand on sequen- tial operations. Since the proposed scheme does not rely on conventional thread-/data-level parallelism, it can be easily applied to such control systems. An analytical evaluation using a real application demonstrates the potential of per- formance improvement achieved by the proposed speculative executions..

九大関連コンテンツ

pure2017年10月2日から、「九州大学研究者情報」を補完するデータベースとして、Elsevier社の「Pure」による研究業績の公開を開始しました。

QIR　九州大学学術情報リポジトリシステム情報科学研究院

システム情報科学研究院


	※ 研究者情報全体を検索する場合は右端の「すべて」を選択して下さい。