| 齋藤 渉（さいとう わたる） | データ更新日：2024.03.15 |
教授 ／
応用力学研究所
新エネルギー力学部門
| 1. | Taro Takamori; Keiji Wada; Wataru Saito; Shin-ichi Nishizawa, Paralleled SiC MOSFETs Circuit Breaker With a SiC MPS Diode for Avalanche Voltage Clamping, IEEE Open Journal of Power Electronics, 10.1109/OJPEL.2024.3365830, 5, 392-401, 2024.02, [URL]. |
| 2. | Wataru Saito, A Future Outlook of Power Devices From the Viewpoint of Power Electronics Trends, IEEE Transactions on Electron Devices, 10.1109/TED.2023.3332611, 71, 3, 1356-1364, 2024.03, [URL]. |
| 3. | Kazunori Hasegawa, Kanta Hara, Nobuyuki Shishido, Satoshi Nakano, Wataru Saito, Tamotsu Ninomiya, Power-cycling degradation monitoring of an IGBT module with VCE(sat) measurement in continuous operation of a chopper circuit, Power Electronic Devices and Components, 10.1016/j.pedc.2024.100061, 7, 100061, 2024.04, [URL]. |
| 4. | 藤本 侑里, 西澤 伸一, 齋藤 渉, IGBT ターンオフスイッチングにおけるサージ電圧解析, 電気学会論文誌C（電子・情報・システム部門誌）, 10.1541/ieejeiss.144.198, 144, 3, 198-203, 2024.03. |
| 5. | Xiang Zhou, Munetoshi Fukui, Kiyoshi Takeuchi, Takuya Saraya, Wataru Saito and Toshiro Hiramoto, Robust reverse bias safe operating area and improved electrical performance in 3300 V non-proportionally scaled insulated gate bipolar transistors, Japanese Journal of Applied Physics, 10.35848/1347-4065/ad106d, 63, 2, 02SP57, 2024.02, [URL]. |
| 6. | Yuri Fujimoto, Shin-ichi Nishizawa and Wataru Saito, Turn-off switching voltage surge analysis with dependence on IGBT cell design, Japanese Journal of Applied Physics, 10.35848/1347-4065/ad106d, 63, 2, 02SP36, 2024.02. |
| 7. | Wataru Saito, Shin-ichi Nishizawa, Overvoltage Failure Process of Cascode GaN Field Effect Transistors, Physica Status Solidi a applications and materials science, 10.1002/pssa.202300791, 221, 2300791, 2024.01, [URL]. |
| 8. | Zaiqi Lou, Thatree Mamee, Katsuhiro Hata, Makoto Takamiya, Shin-ichi Nishizawa, Wataru Saito, Mechanism of gate voltage spike under digital gate control at IGBT switching operations, Power Electronic Devices and Components , 10.1016/j.pedc.2023.100054, 7, 2024.04, [URL]. |
| 9. | Koichi Nishi; Kazuya Konishi; Toshiya Tadakuma; Akihiko Furukawa; Wataru Saito, Device Design Direction of CSTBT for Low Loss and EMI Noise, IEEE Transactions on Electron Devices, 10.1109/TED.2023.3326794, 70, 12, 6144-6150, 2023.12. |
| 10. | Thatree Mamee, Zaiqi Lou, Katsuhiro Hata, Makoto Takamiya, Shin-ichi Nishizawa, Wataru Saito, Bond wire lift-off detection by gate voltage waveform in IGBT turn-off process enhanced by digital gate control, Power Electronic Devices and Components, 10.1016/j.pedc.2023.100052, 6, 2023.10, [URL]. |
| 11. | Zaiqi Lou, Thatree Mamee, Katsuhiro Hata, Makoto Takamiya, Shin-ichi Nishizawa, Wataru Saito, The design considerations of stray inductance for power modules with parallel-connected IGBT chips for a digital gate driver control, Power Electronic Devices and Components , 10.1016/j.pedc.2023.100047, 6, 2023.10, [URL]. |
| 12. | Taro Takamori, Keiji Wada, Wataru Saito, Shin-ichi Nishizawa, Reliability investigation of repeated unclamped inductive switching in a diode-clamped SiC circuit breaker, Microelectronics Reliability, 10.1016/j.microrel.2023.115119, 150, 115119, 2023.10. |
| 13. | Taro Takamori, Keiji Wada, Norman Boettcher, Tobias Erlbacher, Wataru Saito, Shin-ichi Nishizawa, Adjustable Current Limiting Function With a Monolithically Integrated SiC Circuit Breaker Device, IEEE Transactions on Industry Applications, 10.1109/TIA.2023.3288856, 59, 5, 6427-6435, 2023.09. |
| 14. | Thatree Mamee, Zaiqi Lou, Katsuhiro Hata, Makoto Takamiya, Shin-ichi Nishizawa, Wataru Saito, Enhancement of turn-off gate voltage waveform change by digital gate control for bond wire lift-off detection in IGBT module, Microelectronics Reliability, 10.1016/j.microrel.2023.115067, 147, 11, 115067, 2023.08. |
| 15. | Tatsuta Tsukamoto, Shin-ichi Nishizawa, Wataru Saito, A simple sensor device for power cycle degradation sensing, Microelectronics Reliability, 10.1016/j.microrel.2023.115068, 147, 11, 115068, 2023.08. |
| 16. | Joseph Peter Kozak; Ruizhe Zhang; Matthew Porter; Qihao Song; Jingcun Liu; Bixuan Wang; Rudy Wang; Wataru Saito; Yuhao Zhang, Stability, Reliability, and Robustness of GaN Power Devices: A Review, IEEE Transactions on Power Electronics, 10.1109/TPEL.2023.3266365, 38, 7, 8442-8471, 2023.07. |
| 17. | Wataru Saito, Shin-Ichi Nishizawa, Failure Process of GaN-HEMTs by Repetitive Overvoltage Stress, The 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 10.1109/ISPSD57135.2023.10147411, 84-87, 2023.05. |
| 18. | Taro Takamori; Keiji Wada; Wataru Saito; Shin-Ichi Nishizawa, Solid-State Circuit Breaker with Avalanche Robustness using Series-Connection of SiC Diodes, 2023 11th International Conference on Power Electronics and ECCE Asia (ICPE 2023 - ECCE Asia), 10.23919/ICPE2023-ECCEAsia54778.2023.10213947, 2023.05. |
| 19. | Kohei Horii; Hiroki Yano; Katsuhiro Hata; Ruizhi Wang; Kazuto Mikami; Kenji Hatori; Koji Tanaka; Wataru Saito; Makoto Takamiya, Large-Current Output Digital Gate Driver for 6500 V, 1000 A IGBT Module to Reduce Switching Loss and Collector Current Overshoot, IEEE Transactions on Power Electronics, 10.1109/TPEL.2023.3259521, 38, 7, 8075-8088, 2023.07. |
| 20. | Jiuyang Yuan, Yoshiji Miyamura, Satoshi Nakano, Wataru Saito, and Shin-ichi Nishizawa, The Study of Dislocation Propagation in Si Wafer during IGBT High Thermal Budget Process, Abstract of 7th IEEE Electron Devices Technology and Manufacturing (EDTM) Conference 2023, 452-454, 2023.03. |
| 21. | Toshiaki Inuma; Katsuhiro Hata; Toru Sai; Wataru Saito; Makoto Takamiya, Two Stop-and-Go Gate Driving to Reduce Switching Loss and Switching Noise in Automotive IGBT Modules, Proceedings of IEEE 7th Southern Power Electronics Conference (SPEC), 10.1109/SPEC55080.2022.10058383, 2022.12. |
| 22. | Wataru Saito, Automatic total performance design of low-voltage power MOSFETs using zoomed response surface method, Japanese Journal of Applied Physics, 10.35848/1347-4065/acac3d, 62, SC, SC0803-1-SC0803-6, 2023.01. |
| 23. | Joseph P. Kozak; Qihao Song; Ruizhe Zhang; Yunwei Ma; Jingcun Liu; Qiang Li; Wataru Saito; Yuhao Zhang, Degradation and Recovery of GaN HEMTs in Overvoltage Hard Switching Near Breakdown Voltage, IEEE Transactions on Power Electronics, 10.1109/TPEL.2022.3198838, 38, 1, 435-446, 2023.01. |
| 24. | Zaiqi Lou, Thatree Mamee, Katsuhiro Hata, Makoto Takamiya, Shin-Ichi Nishizawa, Wataru Saito, IGBT Power Module Design for Suppressing Gate Voltage Spike at Digital Gate Control, IEEE Access, 10.1109/ACCESS.2023.3237266, 11, 6632-6640, 2023.01. |
| 25. | Zaiqi Lou, Wataru Saito, Shin-ichi Nishizawa, Application of N parallel-connected SiC MOSFETs to solid-state circuit breakers based on UIS tests, Microelectronics Reliability, 10.1016/j.microrel.2022.114737, 138, 114737, 2022.11. |
| 26. | Taro Takamori; Keiji Wada; Norman Boettcher; Tobias Erlbacher; Wataru Saito; Shin-Ichi Nishizawa, Adjustable Current Limit Feature with a Self-Sensing and Self-Triggering Monolithically Integrated SiC Circuit Breaker Device, Proceedings of 2022 IEEE Energy Conversion Congress and Exposition (ECCE), 10.1109/ECCE50734.2022.9948054, 2022.10. |
| 27. | Wataru Saito; Zaiqi Lou; Shin-Ichi NIshizawa, Unclamped Inductive Switching Robustness of SiC Devices With Parallel-Connected Varistor, IEEE Transactions on Electron Devices, 10.1109/TED.2022.3200637, 69, 10, 5671-5677, 2022.10. |
| 28. | Wataru Saito; Zaiqi Lou; Shin-ichi Nishizawa, Cutoff Current Capability of SiC-MOSFETs with Parallel Connected Varistor under UIS Condition, Proceedings of 2022 IEEE Workshop on Wide Bandgap Power Devices and Applications in Europe (WiPDA Europe), 10.1109/WiPDAEurope55971.2022.9936060, 2022.09. |
| 29. | Norman Boettcher; Taro Takamori; Keiji Wada; Wataru Saito; Shin-ichi Nishizawa; Tobias Erlbacher, Short Circuit Performance and Current Limiting Mode of a Monolithically Integrated SiC Circuit Breaker for DC Applications up to 800 V, Proceedings of 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe), 2022.09. |
| 30. | Wataru Saito, and Shin-ichi Nishizawa, Zoomed Response Surface Method for Automatic Design in Parameters Optimization of Low-Voltage Power MOSFET, IEEE Journal of the Electron Devices Society, 10.1109/JEDS.2022.3187151, 10, 512-515, 2022.06. |
| 31. | Kohei Horii, Katsuhiro Hata, Ruizhi Wang, Wataru Saito, and Makoto Takamiya, Large Current Output Digital Gate Driver Using Half-Bridge Digital-to-Analog Converter IC and Two Power MOSFETs, Proceedings of 34th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 293-296, 2022.05. |
| 32. | Norman Boettcher, Taro Takamori, Keiji Wada, Wataru Saito, Shin-ichi Nishizawa and Tobias Erlbacher, Fabrication Aspects and Switching Performance of a Self-Sensing 800 V SiC Circuit Breaker Device, Proceedings of 34th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 261-264, 2022.05. |
| 33. | Wataru Saito, and Shin-ichi Nishizawa, Switching Noise-Loss Trade-Off Improvement of SJ-IGBTs, Proceedings of 34th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 53-56, 2022.05. |
| 34. | Wataru Saito and Shin-ichi Nishizawa, Scaling Design Effects on Surface Buffer IGBT Characteristics, IEEE, Journal of Electron Device Society, 10.1109/JEDS.2021.3129162, 10, 23-28, 2022.02. |
| 35. | Peng Luo, Sankara Narayanan Ekkanath Madathil, Wataru Saito and Shin-ichi Nishizawa, Investigation of turn-on performance in 1.2 kV MOS-bipolar devices, Japanese Journal of Applied Physics, 10.35848/1347-4065/ac40aa, 61, SC0801-1-SC0801-8, 2022.02. |
| 36. | Zaiqi Lou, Keiji Wada, Wataru Saito, Shin-ichi Nishizawa, Investigations on acceptable breakdown voltage variation of parallel-connected SiC MOSFETs applied to solid-state circuit breakers , Microelectronics Reliability, https://doi.org/10.1016/j.microrel.2021.114270, 126, 11, 114270, 2021.11. |
| 37. | Mitsuhiko Sagara, Keiji Wada, Shin-ichi Nishizawa, Wataru Saito, Avalanche current balancing using parallel connection of SiC-MOSFET/SiC-JFETs with cascode connection, Microelectronics Reliability, https://doi.org/10.1016/j.microrel.2021.114237, 126, 11, 114237, 2021.11. |
| 38. | Wataru Saito, Shin-Ichi Nishizawa, Simulation Study on Dual Gate Control of Surface Buffer Insulated Gate Bipolar Transistor for High Switching Controllability, IEEE Electron Device Letters, 10.1109/LED.2021.3075657, 42, 6, 907-910, 2021.06. |
| 39. | Wataru Saito, Shin-ichi Nishizawa, Power Loss Reduction of Low-Voltage Power MOSFET by Combination of Assist Gate Structure and Gate Control Technology, Proceedings of 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD), 10.23919/ISPSD50666.2021.9452240, 271-274, 2021.06. |
| 40. | Taichi Ogawa, Wataru Saito, Shin-Ichi Nishizawa, Slit Field Plate Power MOSFET for Improvement of Figure-Of-Merits, IEEE Journal of the Electron Devices Society, 10.1109/JEDS.2021.3079396, 9, 552-556, 2021.05. |
| 41. | Joseph P. Kozak, Ruizhe Zhang, Qihao Song, Jingcun Liu, Wataru Saito, and Yuhao Zhang, True Breakdown Voltage and Overvoltage Margin of GaN Power HEMTs in Hard Switching, IEEE Electron Device Letters, 10.1109/LED.2021.3063360, 42, 4, 505-508, 2021.04. |
| 42. | Zaiqi Lou, Wataru Saito, and Shin-ichi Nishizawa, Investigation of acceptable breakdown voltage variation for parallel-connected SiC MOSFETs during unclamped inductive switching test, Japanese Journal of Applied Physics, 10.35848/1347-4065/abebc1, 60, SBBD18-1-SBBD18-7, 2021.03. |
| 43. | Taichi Ogawa , Wataru Saito and Shin-ichi Nishizawa, A design direction of low-voltage field-plate power MOSFETs for figure-of-merit (FOM) limit, Japanese Journal of Applied Physics, 10.35848/1347-4065/abe801, 60, SBBD16-1-SBBD16-5, 2021.03. |
| 44. | Peng Luo; Sankara Narayanan Ekkanath Madathil; Shin-Ichi Nishizawa; Wataru Saito, Turn-OFF dV/dt Controllability in 1.2-kV MOS-Bipolar Devices, IEEE Transactions on Power Electronics, 10.1109/TPEL.2020.3014560, 36, 3, 3304-3311, 2021.03. |
| 45. | T. Saraya, K. Itou, T. Takakura, M. Fukui, S. Suzuki, K. Takeuchi, M. Tsukuda, K. Satoh, T. Matsudai, K. Kakushima, T. Hoshii, K. Tsutsui, H. Iwai, A. Ogura, W. Saito, S. Nishizawa, I. Omura, H. Ohashi, and T. Hiramoto, 3.3 kV Back-Gate-Controlled IGBT (BC-IGBT) Using Manufacturable Double-Side Process Technology, International Electron Devices Meeting (IEDM) 2020, 2020.12. |
| 46. | Wataru Saito; Shin-ichi Nishizawa, Improvement Design for Turn-On Switching Characteristics in Surface Buffer Insulated Gate Bipolar Transistor, IEEE Electron Device Letters, 10.1109/led.2020.3034898, 41, 12, 1814-1816, 2020.12. |
| 47. | Taro Takamori, Keiji Wada, Wataru Saitob, Shin-ichi Nishizawab, Gate drive circuit for current balancing of parallel-connected SiC-JFETs under avalanche mode, Microelectronics Reliability, 10.1016/j.microrel.2020.113, 114, 113776, 2020.11. |
| 48. | Ryohei Sato; Koichi Kakimoto; Wataru Saito; Shin-ichi Nishizawa, Dislocation Propagation in Si 300 mm Wafer during High Thermal Budget Process and Its Optimization, 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), 10.1109/ISPSD46842.2020.9170035, 494-497, 2020.09. |
| 49. | Peng Luo; Sankara Narayanan Ekkanath Madathil; Shin-ichi Nishizawa; Wataru Saito, Dynamic Avalanche Free Super Junction-TCIGBT for High Power Density Operation, 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), 10.1109/ISPSD46842.2020.9170129, 470-473, 2020.09. |
| 50. | Wataru Saito; Shin-ichi Nishizawa, High Switching Controllability Trench Gate Design in Si-IGBTs, 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), 10.1109/ISPSD46842.2020.9170118, 447-450, 2020.09. |
| 51. | Peng Luo; Sankara Narayanan Ekkanath Madathil; Shin-Ichi Nishizawa; Wataru Saito, Evaluation of Dynamic Avalanche Performance in 1.2-kV MOS-Bipolar Devices, IEEE Transactions on Electron Devices, 10.1109/TED.2020.3007594, 67, 9, 3691-3697, 2020.09. |
| 52. | Wataru Saito, Shin-Ichi Nishizawa , Alternated Trench-Gate IGBT for Low Loss and Suppressing Negative Gate Capacitance, IEEE Transactions on Electron Devices, 10.1109/TED.2020.3002510, 67, 8, 3285-3290, 2020.08. |
| 53. | Wataru Saito, Shin-Ichi Nishizawa, Surface Buffer IGBT for High Total Performance, IEEE Transactions on Electron Devices, 10.1109/TED.2020.2999874, 67, 8, 3263-3269, 2020.08. |
| 54. | Taichi Ogawa, Wataru Saito, and Shin-Ichi Nishizawa, On-Resistance Limit Estimation of 100 V-class Field-Plate Trench Power MOSFETs Optimized Oxide Thickness, IEEE Electron Device Letters, 10.1109/LED.2020.3000239, 41, 7, 1063-1065, 2020.07. |
| 55. | Wataru Saito, Shin-ichi Nishizawa, Assist Gate MOSFETs for Improvement of On-Resistance and Turn-Off Loss Trade-Off, IEEE Electron Device Letters, 10.1109/LED.2020.2991927, 41, 7, 1060-1062, 2020.07, Assist Gate (AG) MOSFET is proposed for low power loss operation of low-voltage power MOSFETs by a new structure with the optimum gate control. The second channel and accumulation layer reduce the channel and drift resistances. In addition, the gate control of AG-MOSFET decreases turn-off loss. 40 and 100 V-class AG-MOSFET characteristics were analyzed using TCAD simulation. The AG-MOSFET improves on-resistance and turn-off loss trade-off. The simulation results show 34% lower on-resistance with 16% lower turn-off loss for 40 V-class device and 21% lower on-resistance with 10% lower turn-off loss for 100 V-class device.. |
| 56. | Kiyoshi Takeuchi, Munetoshi Fukui, Takuya Saraya, Kazuo Itou, Toshihiko Takakura, Shinichi Suzuki, Yohichiroh Numasawa, Naoyuki Shigyo, Kuniyuki Kakushima, Takuya Hoshii, Kazuyoshi Furukawa, Masahiro Watanabe, Hitoshi Wakabayashi, Kazuo Tsutsui, Hiroshi Iwai, Atsushi Ogura, Wataru Saito, Shin-Ichi Nishizawa, Masanori Tsukuda, Ichiro Omura, Hiromichi Ohashi, and Toshiro Hiramoto, Bipolar Transistor Test Structures for Extracting Minority Carrier Lifetime in IGBTs, IEEE Transactions on Semiconductor Manufacturing, 10.1109/TSM.2020.2972369, 33, 2, 159-165, 2020.05, Vertical PNP bipolar transistor test structures were fabricated and measured, attempting to electrically obtain information on carrier lifetime in the voltage-supporting base region of Insulated Gate Bipolar Transistors (IGBTs). Owing to the structural similarity, the test structures and functional IGBTs can be integrated on the same wafers, making it possible to directly correlate lifetime data and IGBT characteristics. To solve a problem of leaky backside PN junction, common base current gain of the test devices was measured without applying a reverse bias between the collector and base terminals, which suppressed the leakage to an acceptable level. A simple analytical formula to convert the current gain to hole lifetime in the N-type base region was proposed and used, that takes into account the existence of a commonly used N-buffer layer adjacent to the backside P-collector layer. The validity of the formula was confirmed using TCAD simulations. This method was applied to IGBT wafers with two different wafer thicknesses (i.e., base lengths): 120 μm and 360 μm. Consistent lifetime values extracted in spite of the largely different thicknesses supports the validity of the proposed lifetime estimation method.. |
| 57. | Peng Luo, Sankara Narayanan Ekkanath Madathil, Shin-ichi Nishizawa, Wataru Saito, High dV/dt Controllability of 1.2kV Si-TCIGBT for High Flexibility Design with Ultra-low Loss Operation, 2020 IEEE Applied Power Electronics Conference and Exposition (APEC), 10.1109/APEC39645.2020.9124293, 686-689, 2020.03. |
| 58. | Peng Luo, Sankara Narayanan Ekkanath Madathil, Shin-ichi Nishizawa, and Wataru Saito, Dynamic Avalanche Free Design in 1.2kV Si-IGBTs for Ultra High Current Density Operation, International Electron Devices Meeting (IEDM) 2019, 10.1109/IEDM19573.2019.8993596, 266-269, 2019.12. |
| 59. | Yasuhiro Okada ; Takeshi Mizoguchi ; Yuta Tanimoto ; Hideyuki Kikuchihara ; Toshiyuki Naka ; Wataru Saito ; Mitiko Miura-Mattausch ; Hans J?ergen Mattausch, HiSIM_GaN: Compact Model for GaN-HEMT With Accurate Dynamic Current-Collapse Reproduction, IEEE Transactions on Electron Devices, 66, 1, 106-115, 2019.01. |
| 60. | Takeshi Mizoguchi, Toshiyuki Naka, Yuta Tanimoto, Yasuhiro Okada, Wataru Saito, Mitiko Miura-Mattausch, Hans J?rgen Mattausch, Modeling of field-plate effect on gallium-nitride-based high electron mobility transistors for high-power applications, IEICE Transactions on Electronics, E100.C, 3, 321-328, 2017.03. |
| 61. | Wataru Saito and Toshiyuki Naka, Relation between UIS withstanding capability and I-V characteristics in high-voltage GaN-HEMTs, Elsevier Microelectronics Reliability, 76-77, 309-313, 2017.11. |
| 62. | W. Saito and T. Naka, UIS test of high-voltage GaN-HEMTs with p-type gate structure, Elsevier Microelectronics Reliability, 64, 552-555, 2016.11. |
| 63. | Yusuke Takei, Kazuo Tsutsui, Wataru Saito, Kuniyuki Kakushima, Hitoshi Wakabayashi, and Hiroshi Iwai, Dependence of ohmic contact properties on AlGaN layer thickness for AlGaN/GaN high-electron-mobility transistors, Japanese J. of Applied Physics, 55, 40306, 2016.02. |
| 64. | Takeshi Mizoguchi, Toshiyuki Naka, Yuta Tanimoto, Yasuhiro Okada, Wataru Saito, Mitiko Miura-Mattausch, and Hans J?rgen Mattausch, Analysis of GaN high electron mobility transistor switching characteristics for high-power applications with HiSIM-GaN compact model, Japanese J. of Applied Physics, 55, 04EG03, 2016.02. |
| 65. | Takashi Setoya, , Tsuneo Ogura, Wataru Saito, Tomoko Matsudai, Koichi Endo, Destruction failure analysis and international reliability test standard for power devices, Elsevier Microelectronics Reliability, 55, 1932-1937, 2015.11. |
| 66. | L. Zhang, M. Koike, M. Ono, S. Itai, K. Matsuzawa, S. Ono, W. Saito, M. Yamaguchi, Y. Hayase, K. Hara, Comprehensive 2D-carrier profiling of low-doping region by high-sensitivity scanning spreading resistance microscopy (SSRM) for power device applications, Elsevier Microelectronics Reliability, 55, 1159-1163, 2015.11. |
| 67. | W. Saito, T. Suwa, T. Uchihara, T. Naka, T. Kobayashi, Breakdown behaviour of high-voltage GaN-HEMTs, Elsevier Microelectronics Reliability, 55, 1682-1686, 2015.11. |
| 68. | Yusuke Takei, Masayuki Kamiya, Kazuo Tsutsui, Wataru Saito, Kuniyuki Kakushima, Hitoshi Wakabayashi, Yoshinori Kataoka and Hiroshi Iwai, Reduction of contact resistance on AlGaN/GaN HEMT structures by introducing uneven AlGaN layersm, Physica Status Solidi A, 212, 5, 1104-1109, 2015.08. |
| 69. | Yusuke Takei, Mari Okamoto, Wataru Saito, Kazuo Tsutsui, Kuniyuki Kakushima, Hitoshi Wakabayashi, Yoshinori Kataoka and Hiroshi Iwai, Ohmic Contact Properties Depending on AlGaN Layer Thickness for AlGaN/GaN High Electron Mobility Transistor Structures, Electro Chemical Society Transactions, 61, 4, 265-270, 2014.10. |
| 70. | Wataru Saito, Power device trends for high-power density operation of power electronics system, Japanese J. of Applied Physics, 53, 04EP02, 2014.02. |
| 71. | Wataru Saito, GaN-HEMTs for high-voltage switching applications, Electro Chemical Society Transactions, 41, 8, 43-49, 2011.10. |
| 72. | Wataru Saito, Yorito Kakiuchi, Tomohiro Nitta, Yasunobu Saito, Takao Noda, Hidetoshi Fujimoto, Akira Yoshioka, Tetsuya Ohno, and Masakazu Yamaguchi, Field-Plate Structure Dependence of Current Collapse Phenomena in High-Voltage GaN-HEMTs, IEEE Electron Device Letters, 31, 7, 659-661, 2010.07. |
| 73. | Wataru Saito, Takao Noda, Masahiko Kuraguchi, Yoshiharu Takada, Kunio Tsuda, Yasunobu Saito, Ichiro Omura and Masakazu Yamaguchi, Effect of buffer layer structure on drain leakage current and current collapse phenomena in high-voltage GaN-HEMTs, IEEE Trans. Electron Devices, 56, 7, 1371-1376, 2009.07. |
| 74. | Wataru Saito, Tomohiro Nitta, Yorito Kakiuchi, Yasunobu Saito, Kunio Tsuda, Ichiro Omura and Masakazu Yamaguchi, A 120-W Boost Converter Operation Using a High-Voltage GaN-HEMT, IEEE Electron Device Letters, 29, 1, 8-10, 2008.01. |
| 75. | Wataru Saito, Tomohiro Nitta, Yorito Kakiuchi, Yasunobu Saito, Kunio Tsuda, Ichiro Omura and Masakazu Yamaguchi, Suppression of Dynamic On-Resistance Increase and Gate Charge Measurements in High-Voltage GaN-HEMTs With optimized Field-Plate Structure, IEEE Trans. Electron Devices, 54, 8, 1825-1830, 2007.08. |
| 76. | Wataru Saito, Tomohiro Nitta, Yorito Kakiuchi, Yasunobu Saito, Kunio Tsuda, Ichiro Omura and Masakazu Yamaguchi, ON-Resistance Modulation of High Voltage GaN HEMT on Sapphire Substrate Under High Applied Voltage, IEEE Electron Device Letters, 28, 8, 676-678, 2007.08. |
| 77. | Masahiko Kuraguchi, Yoshiharu Takada, Takashi Suzuki, Mayumi Hirose, Kunio Tsuda, Wataru Saito, Yasunobu Saito and Ichiro Omura, Normally-off GaN-MISFET with well-controlled threshold voltage, Physical State Solid (a), 204, 6, 2010-2013, 2007.06. |
| 78. | Wataru Saito, Tomokazu Domon, Ichiro Omura, Masahiko Kuraguchi, Yoshiharu Takada, Kunio Tsuda and Masakazu Yamaguchi, Demonstration of 13.56-MHz Class-E Amplifier Using a High- Voltage GaN Power-HEMT, IEEE Electron Device Letters, 27, 5, 326-328, 2006.05. |
| 79. | Wataru Saito, Yoshiharu Takada, Masahiko Kuraguchi, Kunio Tsuda and Ichiro Omura, Recessed-Gate Structure Approach Toward Normally Off High-Voltage AlGaN/GaN HEMT for Power Electronics Applications, IEEE Trans. Electron Devices, 53, 2, 356-362, 2006.02. |
| 80. | Wataru Saito, Ichiro Omura, Satoshi Aida, Shigeo Koduki, Masaru Izumisawa, Hironori Yoshioka and Tsuneo Ogura, High Breakdown Voltage (>1000V) Semi-Superjunction MOSFETs Using 600-V Class Superjunction MOSFET Process, IEEE Trans. Electron Devices, 52, 10, 2317-2322, 2005.10. |
| 81. | Masahiko Kuraguchi, Yoshiharu Takada, Wataru Saito, Ichiro Omura and Kunio Tsuda, High breakdown voltage AlGaN/GaN MIS-HFET with low leakage current, Physical State Solid (c), 2, 7, 2647-2650, 2005.07. |
| 82. | Wataru Saito, Masahiko Kuraguchi, Yoshiharu Takada, Kunio Tsuda, Ichiro Omura and Tsuneo Ogura, Influence of Surface Defect Charge at AlGaN-GaN-HEMT Upon Schottky Gate Leakage Current and Breakdown Voltage, IEEE Trans. Electron Devices, 52, 2, 159-164, 2005.02. |
| 83. | Wataru Saito, Masahiko Kuraguchi, Yoshiharu Takada, Kunio Tsuda, Ichiro Omura and Tsuneo Ogura, Design Optimization of High Breakdown Voltage AlGaN-GaN Power HEMT on an Insulating Substrate for RonA-VB Tradeoff Characteristics, IEEE Trans. Electron Devices, 52, 1, 106-111, 2005.01. |
| 84. | Wataru Saito, Masahiko Kuraguchi, Yoshiharu Takada, Kunio Tsuda, Ichiro Omura and Tsuneo Ogura, High Breakdown Voltage Undoped AlGaN-GaN Power-HEMT on Sapphire Substrate and Its Demonstration for DC-DC Converter Application, IEEE Trans. Electron Devices, 51, 11, 1913-1917, 2004.11. |
| 85. | Wataru Saito, Ichiro Omura, Ken'ichi Tokano, Tsuneo Ogura and Hiromichi Ohashi, A Novel Low On-Resistance Schottky-Barrier Diode with p-Buried Floating Layer Structure, IEEE Trans. Electron Devices, 51, 5, 797-802, 2004.05. |
| 86. | Wataru Saito, Ichiro Omura, Tsuneo Ogura and Hiromichi Ohashi, Theoretical limit estimation of lateral wide band-gap semiconductor power-switching device, Solid-State Electronics, 48, 4, 1555-1562, 2004.04. |
| 87. | Wataru Saito, Yoshiharu Takada, Masahiko Kuraguchi, Kunio Tsuda, Ichiro Omura and Tsuneo Ogura, Design and Demonstration of High Breakdown Voltage GaN High Electron Mobility Transistor (HEMT) Using Field Plate Structure for Power Electronics Applications, Japanese Journal of Applied Physics, 43, 4, 2239-2242, 2004.04. |
| 88. | Wataru Saito, Yoshiharu Takada, Masahiko Kuraguchi, Kunio Tsuda, Ichiro Omura, Tsuneo Ogura and Hiromichi Ohashi, High Breakdown Voltage AlGaN-GaN Power-HEMT Design and High Current Density Switching Behavior, IEEE Trans. Electron Devices, 50, 12, 2528-2531, 2003.12. |
| 89. | Wataru Saito, Ichiro Omura, Satoshi Aida, Shigeo Koduki, Masaru Izumisawa and Tsuneo Ogura, Semisuperjunction MOSFETs: New Design Concept for Lower On-Resistance and Softer Reverse-Recovery Body Diode, IEEE Trans. Electron Devices, 50, 8, 1801-1806, 2003.08. |
| 90. | Yoshiharu Takada, Wataru Saito, Masahiko Kuraguchi, Ichiro Omura and Kunio Tsuda, High Voltage GaN-based power HEMTs with field plate technique: Breakdown voltage and switching characteristics, Physical State Solid (c), 0, 7, 2347-2350, 2003.07. |
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