| 1. |
Yasunari Suzuki, Takanori Sugiyama, Tomochika Arai, Wang Liao, Koji Inoue, and Teruo Tanimoto, Q3DE: A fault-tolerant quantum computer architecture for multi-bit burst errors by cosmic rays, Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture (MICRO-55), 1110-1125, 2022.10. |
| 2. |
Ilkwon Byun, Junpyo Kim, Dongmoon Min, Ikki Nagaoka, Kosuke Fukumitsu, Iori Ishikawa, Teruo Tanimoto, Masamitsu Tanaka, Koji Inoue, and Jangwoo Kim, XQsim: Modeling Cross-Technology Control Processors for 10+K Qubit Quantum Computers, Proceedings of ACM/IEEE International Symposium on Computer Architecture (ISCA ‘22), 366-382, 2022.06. |
| 3. |
Koki Ishida, Il-Kwon Byun, Ikki Nagaoka, Kosuke Fukumitsu, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Jangwoo Kim, and Koji Inoue, Superconductor Computing for Neural Networks, IEEE Micro, vol.41, no.3, pp.19–26, 2021.05, The superconductor single-flux-quantum (SFQ) logic family has been recognized as a promising solution for the post-Moore era, thanks to the ultrafast and low-power switching characteristics of superconductor devices. Researchers have made tremendous efforts in various aspects, especially in device and circuit design. However, there has been little progress in designing a convincing SFQ-based architectural unit due to a lack of understanding about its potentials and limitations at the architectural level. This article provides the design principles for SFQ-based architectural units with an extremely high-performance neural processing unit (NPU). To achieve our goal, we developed and validated a simulation framework to identify critical architectural bottlenecks in designing a performance-effective SFQ-based NPU. We propose SuperNPU, which outperforms a conventional state-of-the-art NPU by 23 times in terms of computing performance and 1.23 times in power efficiency even with the cooling cost of the 4K environment.. |
| 4. |
Koki Ishida, Il-Kwon Byun, Ikki Nagaoka, Kosuke Fukumitsu, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Jangwoo Kim, Koji Inoue, SuperNPU: Architecting an Extremely Fast Neural Processing Unit Using Superconducting Logic Devices, Proceedings of the 53rd IEEE/ACM International Symposium on Microarchitecture, 10.1109/MICRO50266.2020.00018, 58-72, 2020.10. |
| 5. |
Koki Ishida, Masamitsu Tanaka, Ikki Nagaoka, Takatsugu Ono, Satoshi Kawakami, Teruo Tanimoto, Akira Fujimaki, Koji Inoue, 32 GHz 6.5 mW Gate-Level-Pipelined 4-Bit Processor using Superconductor Single-Flux-Quantum Logic, Proceedings of the IEEE Symposium on VLSI Circuits, 10.1109/vlsicircuits18222.2020.9162826, 1-2, 2020.06. |
| 6. |
Hiroshi Sasaki, Teruo Tanimoto, Koji Inoue, and Hiroshi Nakamura, Scalability-based Manycore Partitioning, Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques (PACT ‘12), 107-116, 2012.09. |
