情報処理学会創立40周年記念論文賞

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1145/2807591.2807638

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/SC.2008.5220091

出版者・発行元：Journal of Real-Time Image Processing  

The growing demand for high-quality video requires complex coding techniques that cost resource consumption and increase encoding time which represents a challenge for real-time processing on Embedded Systems. Kvazaar and x265 encoders are two efficient implementations of the High-Efficient Video Coding (HEVC) standard. In this paper, the performance of All Intra Kvazaar and x265 encoders on the Nvidia Jetson platform was evaluated using two coding configurations; highspeed preset and high-quality preset. In our work, we used two scenarios, first, the two encoders were run on the CPU, and based on the average encoding time Kvazaar proved to be 65.44% and 69.4% faster than x265 with 1.88% and 0.6% BD-rate improvement over x265 at high-speed and high-quality preset, respectively. In the second scenario, the two encoders were run on the GPU of the Nvidia Jetson, and the results show the average encoding time under each preset is reduced by half of the CPU-based scenario. In addition, Kvazaar is 54.5% and 56.70% faster with 1.93% and 0.45% BD-rate improvement over x265 at high-speed and high-quality preset, respectively. Regarding the scalability, the two encoders on the CPU are linearly scaled up to four threads and speed remains constant afterward. On the GPU, the two encoders are scaled linearly with the number of threads. The obtained results confirmed that, Kvazaar is more efficient and that it can be used on Embedded Systems for real-time video applications due to its high speed and performance over the x265 HEVC encoder.

DOI： 10.1007/s11554-024-01429-5

Scopus

出版者・発行元：Journal of Real-Time Image Processing  

In the context of emergency response applications, real-time situational awareness is vital. Unmanned aerial vehicles (UAVs) with imagers have emerged as crucial tools for providing timely information in such scenarios. Convolutional neural networks (CNN) are effective in image processing. However, the deployment of CNN models in UAVs faces significant challenges. The CNN models involve large number of parameters and energy-costly floating-point computations beyond the memory and power available on-board the UAVs. To address these challenges, we propose a co-design optimization approach for deploying the EmergencyNet CNN model on resource-constrained UAVs. Our strategy includes channel-wise pruning to reduce the size and optimize the network architecture. Additionally, we apply additive powers-of-two (APoT) quantization to further compress the model and enhance computational efficiency. Using channel-wise network pruning we derive TinyEmergencyNet that is only 155KB in memory size and 50% smaller than EmergencyNet. This proposed approach is evaluated on Aerial Image Disaster Event Recognition (AIDER) dataset. We have achieved an F1-score of 93.6% with 4-bit APoT quantization that closely approaches the full precision (32-bit) accuracy of 94%. Furthermore, hardware-friendly bit-shifting operations as a result of APoT quantization present an added advantage in hardware accelerator implementations. This work pioneers the joint application of channel-wise pruning and non-uniform APoT quantization on EmergencyNet, presenting a suitable solution tailored for UAV-based emergency response applications.

DOI： 10.1007/s11554-024-01430-y

Scopus

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）   出版者・発行元：Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)  

Charity crowdfunding is a technique for raising funds that involves collecting modest contributions from a vast number of individuals or groups via established crowdfunding platforms or other digital avenues. The objective is to provide support for charitable organizations, social welfare initiatives, or personal requirements. The widespread adoption of the Internet and the rapid advancement of digital technology have facilitated the global dissemination and promotion of charity crowdfunding. However, crowdfunding platforms have recently experienced a decline in credibility due to various factors such as fraudulent donations, inadequate fund management, and other forms of disorder. The blockchain’s decentralization and anti-tampering features exhibit a high degree of compatibility with the requirements of a crowdfunding platform. Most current state-of-the-art techniques do not ensure the non-linkability of user identities in the face of sybil attacks, nor do they offer a streamlined auditing mechanism for crowdsourcing modest donations that simultaneously preserves transactional privacy. This paper presents a novel crowdfunding system called CFChain based on blockchain technology. Initially, the distributed identity and BLS signature are employed to establish a user authentication mechanism, enabling CFChain to withstand sybil attacks while preserving the non-linkability of user identities. Subsequently, a crowdfunding mechanism is constructed utilizing zero-knowledge proofs to facilitate streamlined auditing procedures while safeguarding donations’ confidentiality. Additionally, a security analysis of CFChain is presented. The system prototype is subsequently implemented on the Hyperledger Fabric. Empirical evidence indicates that the efficiency of CFChain is viable.

DOI： 10.1007/978-981-97-0862-8_10

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記述言語：その他   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE Computer Architecture Letters  

The bandwidth limit between cryogenic and room-temperature environments is a critical bottleneck in superconducting noisy intermediate-scale quantum computers. This paper presents the first trial of algorithm-aware system-level optimization to solve this issue by targeting the quantum approximate optimization algorithm. Our counter-based cryogenic architecture using single-flux quantum logic shows exponential bandwidth reduction and decreases heat inflow and peripheral power consumption of inter-temperature cables, which contributes to the scalability of superconducting quantum computers.

DOI： 10.1109/lca.2023.3322700

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出版者・発行元：Proceedings -Design, Automation and Test in Europe, DATE  

This paper proposes a random walk circuit imple-mentation with single flux quantum devices, essential for Brownian circuits, to reduce processing energy consumption dramatically. SPICE-based simulation demonstrating its functional operation and random walks can be achieved via the Shapiro- Wilk test. Furthermore, we developed a Monte Carlo simulator for Brownian circuits, enabling functionality verification and computation step distribution analysis. Latency/energy evaluation using a half-adder as a case study revealed that proposed circuits could reduce energy consumption by 1/1260 and offer an opportunity for low-power computing systems.

Scopus

出版者・発行元：Peer-to-Peer Networking and Applications  

Crowdfunding refers to the online collection of certain capital from a vast number of individuals or groups that each contribute a relatively small amount. Recently, the credibility of crowdfunding platforms has been undermined by fraudulent projects, inadequate fund management, and other forms of disorder. The decentralization and anti-tampering features of blockchain provide the possibility to solve the above problems, and many studies have proposed blockchain-based crowdfunding schemes. However, the existing state-of-the-art methods do not provide user authentication, transaction auditing, and identity management in a privacy-preserving way. Accordingly, this paper presents a novel blockchain-based crowdfunding system called CrowdChain. Initially, the distributed identity and BLS signature are employed to establish a user authentication mechanism, enabling CrowdChain to withstand Sybil attacks while preserving the non-linkability of user identities. Secondly, the physically unclonable function (PUF) is used to generate keys associated with digital identities that are not stored in external devices to resist physical attacks. Subsequently, a crowdfunding mechanism is constructed utilizing zero-knowledge proofs to facilitate streamlined auditing procedures while safeguarding the confidentiality of transactions. Additionally, the formal security analysis proves the security of the CrowdChain scheme. The system prototype is implemented on the Hyperledger Fabric. Empirical evidence indicates the viable efficiency of CrowdChain.

DOI： 10.1007/s12083-024-01785-w

Scopus

記述言語：その他   掲載種別：研究論文（学術雑誌）   出版者・発行元：Journal of Information Processing  

This paper analyzes the impact of input sparsity and DFS/DVFS configurations for single-board computers on the execution time, power, and energy of each VGG16 layer as the first step towards efficient CNN inference on single-board computers. For this purpose, we first develop a power and execution time measurement environment and perform experiments using Raspberry Pi 4 and NVIDIA Jetson Nano. Our results show that clock frequency strongly correlates with execution time and power. Inversely, input sparsity has a weak correlation with execution time and power. Then, we show that a coarse-grained DVFS model can explain over 96% of the variations in the power of each VGG16 layer even when sets of clock frequency and voltage on the single-board computer are unavailable.

DOI： 10.2197/ipsjjip.31.478

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記述言語：その他   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE Transactions on Applied Superconductivity  

We demonstrate the functioning of a high-throughput, gate-level-pipelined floating-point adder and multiplier over 50 GHz. The gate-level-pipelined floating-point adder and multiplier requires dedicated circuit blocks to wait until other circuit blocks complete calculations because of the dependence between their sign, exponent, and significand parts. We revealed that the resultant delay difference of the waiting circuit blocks hinders high-frequency operation if the predesigned circuit blocks with the fixed clock distribution are connected in a simple manner. We showed that clock distribution needs to synchronize with every pipeline stage regardless of the circuit blocks to minimize the delay difference between the circuit blocks for circuits containing the waiting circuit blocks (e.g., the floating-point adder and multiplier). We designed a 5-bit floating-point adder and multiplier to demonstrate the effectiveness of the clock distribution experimentally. The test chips were fabricated using AIST 10-kA/cm$\boldsymbol{^{2}}$ Advanced Process 2. We verified the high-speed operation at over 50 GHz in the floating-point adder and multiplier. The maximum clock frequency and throughput of the floating-point adder were 56 GHz and 56 GFLOPS, respectively. The corresponding values for the floating-point multiplier were 63 GHz and 63 GFLOPS, respectively.

DOI： 10.1109/tasc.2023.3250614

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記述言語：その他   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE Transactions on Applied Superconductivity  

In this article, we demonstrated a high-throughput gate-level-pipelined 8-bit multiply-accumulate (MAC) unit with a long feedback loop using low-voltage rapid single-flux quantum (LV-RSFQ) logic. The long feedback loop in the MAC unit is an obstacle for high-throughput operation because the logic gates must wait for the delayed inputs from the feedback loop. The LV-RSFQ logic makes high-frequency operation even more difficult by larger and more variable feedback delay. We design the feedback loop by using counter-flow clocking and adding many D flip-flops to divide the long feedback loop into shorter paths. The target clock frequency of the MAC unit with a feedback loop was set to 30 GHz by the experimental results of the MAC unit without a feedback loop. We model the clock frequency and its circuit overhead in a feedback loop to design the feedback loop in the MAC unit achieving 30 GHz with a minimum overhead. The test chips are fabricated using the national institute of advanced industrial science and technology (AIST) 10-kA/cm 2 Advanced Process 2. We have successfully obtained high-throughput 30-GHz operations in the LV-RSFQ MAC unit with a long feedback loop by using the model-based design. The maximum operating frequency of the MAC unit reaches 40 GHz.

DOI： 10.1109/tasc.2023.3239329

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記述言語：英語   出版者・発行元：IEEE  

Moore’s Law, doubling the number of transistors in a chip every two years, has so far contributed to the evolution of computer systems. Unfortunately, we cannot expect sustainable transistor shrinking anymore, marking the beginning of the so-called post-Moore era. Therefore, it has become essential to explore emerging devices, and superconductor single-flux-quantum (SFQ) logic that operates in a 4.2- kelvin environment is a promising candidate. Josephson junctions (JJs) are used as switching elements in SFQ logic to compose a superconductor ring (SFQ ring) that can store (or trap) and transfer a single magnetic flux quantum. It fundamentally operates with the voltage pulse-driven nature that makes it possible to achieve extremely low-latency and low-energy JJ switching. This talk shares the history of our SFQ Research, e.g., revisiting microarchitecture and demonstrating over 30 GHz microprocessors, AI accelerator designs, and recently targeting quantum computers. Then, the role of computer architecture for such emerging device computing is discussed.

CiNii Research

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）   出版者・発行元：Proceedings - 2022 IEEE 15th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2022  

The performance improvement by CMOS circuit technology is reaching its limits. Many researchers have been studying computing technologies that use emerging devices to challenge such critical issues. Nanophotonic technology is a promising candidate due to its ultra-low latency, high bandwidth, and low power natures. The advanced research activity of nanophotonic computing is to design hardware accelerators for AI inference applications. However, few considerations about nanophotonic accelerators for AI training applications have been conducted. The main reason is that state-of-the-art nanophotonic AI accelerators involve integer operations, whereas floating-point (FP) sum-of-products dominate the training process. However, to the best of the authors' knowledge, there are no optical circuits that target floating-point arithmetic units. This study proposes a novel Opto-Electrical Floating-point Multiplier (OEFM) toward ultra-low-latency, a power-efficient nanophotonic accelerator for AI training applications. We design a microarchitecture of OEFM, including a novel optical integer multiplier and other electrical components. Based on our evaluation framework, we analyze the calculation accuracy of the proposed multiplier and OEFM. Experimental results show that OEFM achieves a 56 % reduction in latency and a 41 % reduction in energy consumption compared with a conventional electrical circuit.

DOI： 10.1109/mcsoc57363.2022.00057

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記述言語：その他   掲載種別：研究論文（その他学術会議資料等）   出版者・発行元：Proceedings - 2022 IEEE 15th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2022  

Since the Internet of Things (IoT) has become more widely used in various industrial situations, Artificial Intelligence (AI) programs, particularly Convolutional Neural Network (CNN) applications, are projected to be implemented on edge devices to meet high-accuracy and huge industry computing needs. Offloading computing-intensive workloads to the cloud is a promising solution for compact energy-constrained edge devices, but it tends to incur significant costs in total execution latency. For flexible and fine-grained offloading, this paper aims to design and implement an edge-cloud cooperative CNN inference framework on an IoT platform by targeting TensorFlow Lite. We have confirmed the implementation's feasibility and accuracy through the verification of implementing LeNet, AlexNet, and VGGNet. Intending to perform high-performance edge-cloud AI executions on the presented IoT platform, we evaluate the performance overhead (total execution latency) of the provided implementation and identify the current bottlenecks of the target platform for enhancing it.

DOI： 10.1109/mcsoc57363.2022.00060

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記述言語：その他   掲載種別：研究論文（その他学術会議資料等）   出版者・発行元：Proceedings - 2022 IEEE 15th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2022  

Recurrent neural networks (RNNs) have achieved high performance in inference processing that handles time-series data. Among them, hardware acceleration for fast processing RNNs is helpful for tasks where real-time performance is es-sential, such as speech recognition and stock market prediction. The nano-photonic neural network accelerator is an approach that takes advantage of the high speed, high parallelism, and low power consumption of light to achieve high performance in neural network processing. However, existing methods are inefficient for RNNs due to significant overhead caused by the absence of recursive paths and the immaturity of the model to be designed. Therefore, architectural considerations that take advantage of RNN characteristics are essential for low latency. This paper proposes a fast and low-power processing unit for RNNs that introduces activation functions and recursion processing using optical devices. We clarified the impact of noise on the proposed circuit's calculation accuracy and inference accuracy. As a result, the calculation accuracy deteriorated significantly in proportion to the increase in the number of recursions, but the effect on inference accuracy was negligible. We also compared the performance of the proposed circuit to an all-electric design and a hybrid design that processes the vector-matrix product optically and the recursion electrically. As a result, the performance of the proposed circuit improves latency by 467x, reduces power consumption by 93.0% compared with the all-electrical design, improves latency by 7.3x, and reduces power consumption by 58.6% compared with the hybrid design.

DOI： 10.1109/mcsoc57363.2022.00058

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記述言語：その他   掲載種別：研究論文（その他学術会議資料等）   出版者・発行元：2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings  

A superconductor single-flux-quantum (SFQ) logic 8-bit microprocessor is demonstrated up to 57.2 GHz with a measured power consumption of 11.2 mW. The microprocessor has an ultradeep, gate-level pipelining containing many feedback paths and communications between components. The arrival clock timings at all the logic gates are ultra-precisely tuned using two different clocking schemes, called 'concurrent-flow' and 'counter-flow,' to achieve extremely high clock frequency operation over 50 GHz. Low-temperature circumstances enable us to conduct super delay-intensive layout design by controlling delays of all waveguide interconnects in the order of sub-picosecond precision.

DOI： 10.1109/a-sscc56115.2022.9980802

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記述言語：その他   掲載種別：研究論文（その他学術会議資料等）   出版者・発行元：2022 IEEE 8th World Forum on Internet of Things, WF-IoT 2022  

Recently IoT edge devices have become more diverse and lower cost. In addition, small low-power single-board computers' computing performance has significantly increased. These conditions make it possible to process locally without communicating to the cloud. Since the advantages of in-edge processing are security and privacy, we applied in-edge IoT to smart homes with rich private information to be secured. In in-edge processing, conventional cloud-managed abnormality monitoring and system maintenance cannot be involved. We developed a lamp control system with in-edge processing. It detects failures using camera image processing and recovers from the failure. The abnormalities of the image processing are detected by monitoring cyclic outdoor brightness change observed on windows captured with the same camera. We have developed a prototype system with Python with OpenCV and FastAPI, etc., over PHP-based lamp timer control while keeping source code size small and considering validation easiness. The camera detectors work at 10 FPS on Python with as small as 1607 total source code lines (three times of code lines against the original lamp control timer).

DOI： 10.1109/wf-iot54382.2022.10152281

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出版者・発行元：IEEE  

This paper presents the design of an ultra-high-speed, low-power arithmetic unit that supports variable bit-width operations with single flux quantum (SFQ) technology. Because of the high-speed nature of superconductor devices, we can achieve extremely high power-performance efficiency that cannot be achieved by state-of-the-art CMOS devices. To implement the complex function to support the variable bit-width feature, we introduce a novel circuit architecture to maintain the high-speed operation over 50GHz. Our prototype chip design successfully demonstrated 53.5GHz 1.59mW operations.

DOI： 10.1109/iscas48785.2022.9937317

Scopus

CiNii Research

記述言語：日本語   出版者・発行元：公益社団法人 低温工学・超電導学会 (旧 社団法人 低温工学協会)  

DOI： 10.2221/jcsj.57.382

CiNii Research

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/ACCESS.2021.3125697

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/tasc.2021.3071996

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/ACCESS.2020.3014163

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ISVLSI49217.2020.00059

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ISVLSI49217.2020.00060

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

A Single-Flux-Quantum (SFQ) 4-bit throughput-oriented processor has successfully been demonstrated at up to 32 GHz with the measured power consumption of 6.5 mW. This is the first implementation of the gate-level-pipelined processor, and it achieves 2.5 Tera-Operations Per Watt (TOPS/W) by circuit and architectural optimizations.

DOI： 10.1109/VLSICircuits18222.2020.9162826

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/VLSICircuits18222.2020.9162826

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

GPUs can achieve high performance by exploiting massive-thread parallelism. However, some factors limit performance on GPUs, one of which is the negative effects of L1 cache misses. In some applications, GPUs are likely to suffer from L1 cache conflicts because a large number of cores share a small L1 cache capacity. A cache architecture that is based on data compression is a strong candidate for solving this problem as it can reduce the number of cache misses. Unlike previous studies, our data compression scheme attempts to exploit the value locality existing within not only intra cache lines but also inter cache lines. We enhance the structure of a last-level compression cache proposed for general purpose manycore processors to optimize against shared L1 caches on GPUs. The experimental results reveal that our proposal outperforms the other compression cache for GPUs by 11 points on average.

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1145/3368474.3368491

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1145/3368474.3368496

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

High-performance soft processors in field-programmable gate arrays (FPGAs) have become increasingly important as recent large FPGA systems have relied on soft processors to run many complex workloads, like a network software stack. An out-of-order (OoO) superscalar approach is a good candidate to improve performance in such cases, as evidenced from OoO hard processor studies. Recent studies have revealed, however, that conventional OoO processor components do not fit well in an FPGA, and it is thus important to carefully design such components for FPGA characteristics. Hence, we propose the RSD processor: a new, open-source OoO RISC-V soft processor optimized for an FPGA. The RSD supports many aggressive OoO execution features, like speculative scheduling, OoO memory instruction execution and disambiguation, a memory dependence predictor, and a non-blocking cache. While the RSD supports such aggressive features, it also leverages FPGA characteristics. Therefore, it consumes fewer FPGA resources than are consumed by existing OoO soft processors, which do not support such aggressive features well. We first introduce the end result of the RSD microarchitecture design and then describe several novel optimization techniques. The RSD achieves up to 2.5-times higher Dhrystone MIPS while using 60% fewer registers and 64% fewer lookup tables (LUTs) as compared to state-of-the-art, open-source OoO processors.

DOI： 10.1109/ICFPT47387.2019.00016

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/HiPC.2019.00044

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ICFPT47387.2019.00016

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Interconnection networks grow larger as supercomputers include more nodes and require higher bandwidth for performance. This scaling significantly increases the fraction of power consumed by the network, by increasing the number of network components (links and switches). Typically, network links consume power continuously once they are turned on. However, recent proposals for energy efficient interconnects have introduced low-power operation modes for periods when network links are idle. Low-power operation can increase messaging time when switching a link from low-power to active operation. We extend the TraceR-CODES network simulator for power modeling to evaluate the impact of energy efficient networking on power and performance. Our evaluation presents the first study on both single-job and multi-job execution to realistically simulate power consumption and performance under congestion for a large-scale HPC network. Results on several workloads consisting of HPC proxy applications show that single-job and multi-job execution favor different modes of low power operation to have significant power savings at the cost of minimal performance degradation.

DOI： 10.1109/HiPC.2019.00044

記述言語：英語  

DOI： 10.1063/1.5108912

記述言語：英語  

DOI： 10.1063/1.5108912

記述言語：英語  

In the emerging Internet of things cyber-physical system-embedded society, big data analytics needs huge computing capability with better energy efficiency. Coming to the end of Moore's law of the electronic integrated circuit and facing the throughput limitation in parallel processing governed by Amdahl's law, there is a strong motivation behind exploring a novel frontier of data processing in post-Moore era. Optical fiber transmissions have been making a remarkable advance over the last three decades. A record aggregated transmission capacity of the wavelength division multiplexing system per a single-mode fiber has reached 115 Tbit/s over 240 km. It is time to turn our attention to data processing by photons from the data transport by photons. A photonic accelerator (PAXEL) is a special class of processor placed at the front end of a digital computer, which is optimized to perform a specific function but does so faster with less power consumption than an electronic general-purpose processor. It can process images or time-serial data either in an analog or digital fashion on a real-time basis. Having had maturing manufacturing technology of optoelectronic devices and a diverse array of computing architectures at hand, prototyping PAXEL becomes feasible by leveraging on, e.g., cutting-edge miniature and power-efficient nanostructured silicon photonic devices. In this article, first the bottleneck and the paradigm shift of digital computing are reviewed. Next, we review an array of PAXEL architectures and applications, including artificial neural networks, reservoir computing, pass-gate logic, decision making, and compressed sensing. We assess the potential advantages and challenges for each of these PAXEL approaches to highlight the scope for future work toward practical implementation.

DOI： 10.1063/1.5108912

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/ACCESS.2019.2936796

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

We report the successful operation of an energy-efficient 8-bit arithmetic logic unit (ALU) based on bit-parallel, gate-Ievel-pipelining, and low-voltage rapid single-flux-quantum (LV-RSFQ) approaches. We implemented the ALU using a 10-kA/cm² Nb process. The bias voltage was optimized to obtain high energy efficiency. Although lowed bias voltage leads to difficulty in timing design, we solved the problem by precise timing control. The operating frequency reached 30 GHz. Thanks to these high-throughput and low-energy technologies, we realized highly energy-efficient operation over 100 tera-operations per second per watt (TOPS/W).

DOI： 10.1109/ISEC46533.2019.8990905

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1587/transfun.E102.A.758

記述言語：日本語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Discrimination between earthquakes and explosion is one of the main challenges in the field of seismology. In some cases, the explosions recorded as an earthquake or vice verse, which can contaminate the seismic catalog. Rapid discrimination is required to support the real-time seismic application. The discrimination algorithm is based on a wavelet filter bank to extract the discriminative features, and support vector machine (SVM) as a classifier. Therefore; we propose to optimize the hardware implementation of the discrimination algorithm on Field Programmable Gate Array (FPGA). First, we implement the wavelet filter bank using optimized lifting scheme. Then, we utilize the linear classifier to implement the SVM classifier. Finally, we optimize the hardware resources of the discrimination algorithm to be utilized on low-cost FPGA called TE0711 board (Xilinx Artix7). The implemented design is utilized 1.2% and 39.8% of the FPGA's Look Up Table (LUT) and register resources, respectively.

DOI： 10.1109/JEC-ECC.2018.8679531

記述言語：英語  

DOI： 10.1109/JEC-ECC.2018.8679541

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

This paper reports the performance and endurance impacts of a slow-write approach for a multi-level cell (MLC) of phase change memory (PCM). An MLC improves the density of PCM, but the endurance is a critical issue. To extend the lifetime of the cell, a slow-write approach is one of the techniques that is used. However, the slow-write approach increases the program execution time because it takes a long time. In this paper, we discuss three types of slow-write approach for MLC and evaluate the endurance and performance quantitatively to understand the effectiveness of our approach. Our evaluation results show that one of the approaches enhances the endurance of MLC PCM 1.57 times with a 1.41 % performance degradation on average compared with the conventional write operation.

DOI： 10.1109/JEC-ECC.2018.8679540

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

A multiplier based on superconductor single-flux-quantum (SFQ) logic is demonstrated up to 48GHz with the measured power consumption of 5.6 mW. The multiplier performs 8 × 8 - bit signed multiplication every clock cycle. The design is based on a bit-parallel, gate-level-pipelined structure that exploits ultimately high-throughput performance of SFQ logic. The test chip fabricated using a 1.0- μ {m}, 9-layer process consists of 20,251 Nb/AlOx/Nb Josephson junctions (JJs). The correctness of operation is verified by on-chip high-speed testing.

DOI： 10.1109/ISSCC.2019.8662351

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ISSCC.2019.8662351

記述言語：その他   掲載種別：研究論文（学術雑誌）  

© 2019 Information Processing Society of Japan. A spoofing attack is a critical issue in wireless communication in which a malicious transmitter outside a system attempts to be genuine. As a countermeasure against this, we propose a device-authentication method based on position identification using radio-propagation characteristics (RPCs). Not depending on information processing such as encryption technology, this method can be applied to sensing devices etc. which commonly have many resource restrictions. We call the space from which attacks achieve success as the “attack space.” In order to confine the attack space inside of the target system to prevent spoofing attacks from the outside, formulation of the relationship between combinations of transceivers and the attack space is necessary. In this research, we consider two RPCs, the received signal strength ratio (RSSR) and the time difference of arrival (TDoA), and construct the attack-space model which uses these RPCs simultaneously. We take a tire pressure monitoring system (TPMS) as a case study of this method and execute a security evaluation based on radio-wave-propagation simulation. The simulation results assuming multiple noise environments all indicate that it is possible to eliminate the attack possibility from a distant location.

DOI： 10.2197/ipsjjip.27.322

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Presently the power consumption of supercomputer system becomes a critical issue to develop the exascale supercomputer system. On the other hand, the power consumption character of applications is not so considered by the applications developers because their main interest is how fast to run their applications. In this study, we examine and evaluate the power consumption behavior of our Magnetohydrodynamic simulation code which solves the planetary magnetosphere under the constrained power of CPU and DRAM on the x86 computer system. As the results, we found there are some regions in the simulation code which decrease the calculation performance or do not affect the performance under the power capping. This indicates the capability of power optimization without performance degradation using the dynamic power capping in running the application. In addition, we obtained the specific power consumption combinations between CPU and DRAM which greatly affect the calculation performance.

DOI： 10.1109/HPCC/SmartCity/DSS.2018.00113

記述言語：英語   掲載種別：研究論文（学術雑誌）  

SUMMARY Correctly understanding microarchitectural bottlenecks is important to optimize performance and energy of OoO (Out-of-Order) processors. Although CPI (Cycles Per Instruction) stack has been utilized for this purpose, it stacks architectural events heuristically by counting how many times the events occur, and the order of stacking affects the result, which may be misleading. It is because CPI stack does not consider the execution path of dynamic instructions. Critical path analysis (CPA) is a well-known method to identify the critical execution path of dynamic instruction execution on OoO processors. The critical path consists of the sequence of events that determines the execution time of a program on a certain processor. We develop a novel representation of CPCI stack (Cycles Per Critical Instruction stack), which is CPI stack based on CPA. The main challenge in constructing CPCI stack is how to analyze a large number of paths because CPA often results in numerous critical paths. In this paper, we show that there are more than ten to the tenth power critical paths in the execution of only one thousand instructions in 35 benchmarks out of 48 from SPEC CPU2006. Then, we propose a statistical method to analyze all the critical paths and show a case study using the benchmarks.

DOI： 10.1587/transfun.E102.A.758

記述言語：英語   掲載種別：研究論文（学術雑誌）  

A spoofing attack is a critical issue in wireless communication in which a malicious transmitter outside a system attempts to be genuine. As a countermeasure against this, we propose a device-authentication method based on position identification using radio-propagation characteristics (RPCs). Not depending on information processing such as encryption technology, this method can be applied to sensing devices etc. which commonly have many resource restrictions. We call the space from which attacks achieve success as the “attack space.” In order to confine the attack space inside of the target system to prevent spoofing attacks from the outside, formulation of the relationship between combinations of transceivers and the attack space is necessary. In this research, we consider two RPCs, the received signal strength ratio (RSSR) and the time difference of arrival (TDoA), and construct the attack-space model which uses these RPCs simultaneously. We take a tire pressure monitoring system (TPMS) as a case study of this method and execute a security evaluation based on radio-wave-propagation simulation. The simulation results assuming multiple noise environments all indicate that it is possible to eliminate the attack possibility from a distant location.

DOI： 10.2197/ipsjjip.27.322

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Situation-Based Dynamic Frame-Rate Control for On-Line Object Tracking,

DOI： 10.1109/jec-ecc.2018.8679545

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/jec-ecc.2018.8679540

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1587/transinf.2018PAP0003

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1587/transfun.e101.a.2297

記述言語：英語   掲載種別：研究論文（学術雑誌）  

On-line object tracking (OLOT) has been a core technology in computer vision, and its importance has been increasing rapidly. Because this technology is utilized for battery-operated products, energy consumption must be minimized. This paper describes a method of adaptive frame-rate optimization to satisfy that requirement. An energy trade-off occurs between image capturing and object tracking. Therefore, the method optimizes the frame-rate based on always changed object speed for minimizing the total energy while taking into account the trade-off. Simulation results show a maximum energy reduction of 50.0%, and an average reduction of 35.9% without serious tracking accuracy degradation.

DOI： 10.1587/transfun.E101.A.2297

記述言語：英語  

Power consumption is a first class design constraint for developing future exascale computing systems. To achieve exascale system performance with realistic power provisioning of 20-30MW, we need to improve power-performance efficiency significantly compared to today's supercomputer systems. In order to maximize effective performance within a power constraint, investigating how to optimize power resource allocation to each hardware component or each job submitted to the system is necessary. We have been conducting research and development on a software framework for code optimization and system power management for the power-constraint adaptive systems. We briefly introduce the research efforts for maximizing application performance under a given power constraint, power-aware resource manager, and power-performance simulation and analysis framework for future supercomputer systems.

DOI： 10.1007/978-981-13-1924-2_13

記述言語：英語   掲載種別：研究論文（学術雑誌）  

We propose a parallel precomputation method for real-time model predictive control. The key idea is to use predicted input values produced by model predictive control to solve an optimal control problem in advance. It is well known that control systems are not suitable for multi- or many-core processors because feedback-loop control systems are inherently based on sequential operations. However, since the proposed method does not rely on conventional thread-/data-level parallelism, it can be easily applied to such control systems without changing the algorithm in applications. A practical evaluation using three real-world model predictive control system simulation programs demonstrates drastic performance improvement without degrading control quality offered by the proposed method.

DOI： 10.1587/transinf.2018PAP0003

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

The accurate detection of P-wave arrival time is imperative for determining the hypocenter location of an earthquake. However, precise detection of onset time becomes more difficult when the signal-to-noise ratio (SNR) of the seismic data is low, such as during microearthquakes. In this letter, a stacked denoising autoencoder (SDAE) is proposed to smooth the background noise. The SDAE acts as a denoising filter for the seismic data. In the proposed algorithm, the SDAE is utilized to reduce background noise such that the onset time becomes more clear and sharp. Afterward, a hard decision with one threshold is used to detect the onset time of the event. The proposed algorithm is evaluated on both synthetic and field seismic data. As a result, the proposed algorithm outperforms the short-time average/long-time average and the Akaike information criterion algorithms. The proposed algorithm accurately picks the onset time of 94.1% for 407 field seismic waveforms with a standard deviation error of 0.10 s. In addition, the results indicate that the proposed algorithm can pick arrival times accurately for weak SNR seismic data with SNR higher than -14 dB.

DOI： 10.1109/LGRS.2018.2861218

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：日本語  

Optical WDM parallel adder based on optical pass gate logic (2) ~ Experimental study using thermo-optic switch ~

DOI： 10.11470/jsapmeeting.2018.2.0_934

記述言語：日本語  

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1587/transinf.2017edp7296

記述言語：英語   掲載種別：研究論文（学術雑誌）  

The power consumption of server platforms has been increasing as the amount of hardware resources equipped on them is increased. Especially, the capacity of DRAM continues to grow, and it is not rare that DRAM consumes higher power than processors on modern servers. Therefore, a reduction in the DRAM energy consumption is a critical challenge to reduce the system-level energy consumption. Although it is well known that improving row buffer locality (RBL) and bank-level parallelism (BLP) is effective to reduce the DRAM energy consumption, our preliminary evaluation on a real server demonstrates that RBL is generally low across 15 multithreaded benchmarks. In this paper, we investigate the memory access patterns of these benchmarks using a simulator and observe that cache line-grained channel interleaving schemes, which are widely applied to modern servers including multiple memory channels, hurt the RBL each of the benchmarks potentially possesses. In order to address this problem, we focus on a row-grained channel interleaving scheme and compare it with three cache line-grained schemes. Our evaluation shows that it reduces the DRAM energy consumption by 16.7%, 12.3%, and 5.5%on average (up to 34.7%, 28.2%, and 12.0%) compared to the other schemes, respectively.

DOI： 10.1587/transinf.2017EDP7296

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Monitoring illegal explosions is mandatory for the safety of human life, environment, and protect the important buildings such as High-dam in Egypt. This kind of monitoring can be accomplished by detecting and identifying the explosions. If an illegal explosion happens such as quarry blast, an alarm should be reported to the government to take immediate action. However, the main problem is that many measured signals from received explosions are similar to earthquakes in their shape and both cannot differentiate from each other. Also, incorrect classification possibly will distort the real seismicity nature of the region. This problem motivates us to search for unique discriminating features to distinguish between earthquakes and explosions with precise accuracy. Therefore, in this paper, we propose to extract the discriminative features based on Autoencoder from the first few seconds after the P-wave arrival time of the event. The discriminative features are found to be in the first 60 samples after the arrival time of P-wave. Thus the first stage of the proposed algorithm is extracting the discriminative features via the Autoencoder. Then, softmax classifies the event based on these extracted features. The proposed algorithm achieves a classification accuracy of 98.55% when applied to 900 earthquakes and quarry blasts waveforms recorded by Egyptian National Seismic Network (ENSN).

DOI： 10.1109/ICIS.2018.8466464

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Hardware overprovisioned systems have recently been proposed as a viable alternative for a power-efficient design of next-generation supercomputers. A key challenge for such systems is to determine the degree of overprovisioning, which refers to the number of extra nodes that need to be installed under a given power constraint. In this paper, we first show that the degree of overprovisioning depends on dynamic parameters, such as the job mix as well as the global power constraint, and that static decisions can result in limited system throughput. We then study an exhaustive combination of adaptive resource management strategies that span three job scheduling algorithms, four power capping techniques, and three node boot-up mechanisms to understand the trade-off space involved. We then draw conclusions about how these strategies can adaptively control the degree of overprovisioning and analyze their impact on job throughput and power utilization.

DOI： 10.1109/IPDPS.2018.00062

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/LGRS.2018.2861218

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/LCA.2018.2866243

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/LCA.2018.2866243

記述言語：英語  

A novel light speed computing technology has been developed by NTT, Kyoto University, and Kyushu University that employs nanophotonic technology in critical paths and thus overcomes the problem of operational latency that is the chief limiting factor in conventional electronic circuits. The ultimate objective of this work is to develop an ultrahigh-speed optoelectronic arithmetic processor. This article provides an overview of our recent work and describes the successful implementation of this novel optical computing technology.

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1145/3178452

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/HPCC/SmartCity/DSS.2018.00113

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ICIS.2018.8466464

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/IPDPS.2018.00062

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1587/transele.E101.C.359

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1587/transele.E101.C.359

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Correctly understanding microarchitectural bottlenecks is important to optimize performance and energy of OoO (Out-of-Order) processors. Although CPI (Cycles Per Instruction) stack has been utilized for this purpose, it stacks architectural events heuristically by counting how many times the events occur, and the order of stacking affects the result, which may be misleading. It is because CPI stack does not consider the execution path of dynamic instructions. Critical path analysis (CPA) is a well-known method to identify the critical execution path of dynamic instruction execution on OoO processors. The critical path consists of the sequence of events that determines the execution time of a program on a certain processor. We develop a novel representation of CPCI stack (Cycles Per Critical Instruction stack), which is CPI stack based on CPA. The main challenge in constructing CPCI stack is how to analyze a large number of paths because CPA often results in numerous critical paths. In this paper, we show that there are more than ten to the tenth power critical paths in the execution of only one thousand instructions in 35 benchmarks out of 48 from SPEC CPU2006. Then, we propose a statistical method to analyze all the critical paths and show a case study using the benchmarks.

DOI： 10.1109/CANDAR.2017.60

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

A spoofing attack is a critical issue in wireless communication in embedded systems in which a malicious transmitter outside a system attempts to be genuine. As a countermeasure against this, we propose a device-authentication method based on position identification using radio-propagation characteristics (RPCs). Since RPCs are natural phenomena, this method does not depend on information processing such as encryption technology. We call the space from which attacks achieve success "attack space". By formulating the relationship between combinations of transceivers and the attack space, this method can be used in embedded systems. In this research, we consider two RPCs, the received signal strength ratio (RSSR) and the time difference of arrival (TDoA), and construct the attack-space model which use these RPCs simultaneously for preventing wireless spoofing-attacks. We explain the results of a validity evaluation for the proposed model based on radio-wave-propagation simulation assuming free space and a noisy environment.

DOI： 10.1109/DASC-PICom-DataCom-CyberSciTec.2017.94

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

© 2017 IEEE. A spoofing attack is a critical issue in wireless communication in embedded systems in which a malicious transmitter outside a system attempts to be genuine. As a countermeasure against this, we propose a device-authentication method based on position identification using radio-propagation characteristics (RPCs). Since RPCs are natural phenomena, this method does not depend on information processing such as encryption technology. We call the space from which attacks achieve success "attack space". By formulating the relationship between combinations of transceivers and the attack space, this method can be used in embedded systems. In this research, we consider two RPCs, the received signal strength ratio (RSSR) and the time difference of arrival (TDoA), and construct the attack-space model which use these RPCs simultaneously for preventing wireless spoofing-attacks. We explain the results of a validity evaluation for the proposed model based on radio-wave-propagation simulation assuming free space and a noisy environment.

DOI： 10.1109/DASC-PICom-DataCom-CyberSciTec.2017.94

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

We propose an optical parallel adder based on a binary decision diagram that can calculate simply by propagating light through electrically controlled optical pass gates. The CARRY and CARRY operations are multiplexed in one circuit by a wavelength division multiplexing scheme to reduce the number of optical elements, and only a single gate constitutes the critical path for one digit calculation. The processing time reaches picoseconds per digit when we use a 100-μm-long optical path gates, which is ten times faster than a CMOS circuit.

DOI： 10.1117/12.2296842

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Moore's law for CMOS computers is still continuing, but its near-future saturation is now being discussed. One of the serious saturations is about its latency. The computation delay for a CMOS transistor is already saturated above 10 ps, which will be problematic when ultralow-latency response is required for broad-band data streams, even with parallelization or pipe-line processing. We regard that optical circuits may serve as ultralow-latency computation circuits if they are small enough and tightly combined with electronic circuits. The former requires nanophotonic devices/circuits and the former requires OE/EO conversion with ultrasmall capacitance.

記述言語：英語  

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.2197/ipsjjip.25.983

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/candar.2017.60

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Limited power budgets will be one of the biggest challenges for deploying future exascale supercomputers. One of the promising ways to deal with this challenge is hardware overprovisioning, that is, installingmore hardware resources than can be fully powered under a given power limit coupled with software mechanisms to steer the limited power to where it is needed most. Prior research has demonstrated the viability of this approach, but could only rely on small-scale simulations of the software stack. While such research is useful to understand the boundaries of performance benefits that can be achieved, it does not cover any deployment or operational concerns of using overprovisioning on production systems. This paper is the first to present an extensible power-aware resource management framework for production-sized overprovisioned systems based on the widely established SLURM resource manager. Our framework provides flexible plugin interfaces and APIs for power management that can be easily extended to implement site-specific strategies and for comparison of different power management techniques. We demonstrate our framework on a 965-node HA8000 production system at Kyushu University. Our results indicate that it is indeed possible to safely overprovision hardware in production. We also find that the power consumption of idle nodes, which depends on the degree of overprovisioning, can become a bottleneck. Using real-world data, we then draw conclusions about the impact of the total number of nodes provided in an overprovisioned environment.

DOI： 10.1109/IPDPS.2017.107

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/IPDPS.2017.107

記述言語：日本語  

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/LCA.2017.2684813

記述言語：英語  

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Graph analysis applications have been widely used in real services such as road-traffic analysis and social network services. Breadth-first search (BFS) is one of the most representative algorithms for such applications; therefore, many researchers have tuned it to maximize performance. On the other hand, owing to the strict power constraints of modern HPC systems, it is necessary to improve power efficiency (i.e., performance per watt) when executing BFS. In this work, we focus on the power efficiency of DRAM and investigate the memory access pattern of a state-of-the-art BFS implementation using a cycle-accurate processor simulator. The results reveal that the conventional address mapping schemes of modern memory controllers do not efficiently exploit row buffers in DRAM. Thus, we propose a new scheme called per-row channel interleaving and improve the DRAM power efficiency by 30.3% compared to a conventional scheme for a certain simulator setting. Moreover, we demonstrate that this proposed scheme is effective for various configurations of memory controllers.

DOI： 10.1109/HPGDMP.2016.010

記述言語：英語  

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Integrated optical circuits with nanophotonic devices have attracted significant attention due to its low power dissipation and light-speed operation. With light interference and resonance phenomena, the nanophotonic device works as a voltage-controlled optical pass-gate like a pass-Transistor. This paper first introduces a concept of the optical pass-gate logic, and then proposes a parallel adder circuit based on the optical passgate logic. Experimental results obtained with an optoelectronic circuit simulator show advantages of our optical parallel adder circuit over a traditional CMOS-based parallel adder circuit.

DOI： 10.1109/ISOCC.2016.7799721

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/bigdata.2016.7840624

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Single-flux-quantum (SFQ) logic is promising technology to realize an incredible microprocessor which operates over 100 GHz due to its ultra-fast-speed and ultra-lowpower natures. Although previous work has demonstrated prototype of an SFQ microprocessor, the SFQ based L1 cache memory has not well optimized: A large access latency and strictly limited scalability. This paper proposes a novel SFQ cache architecture to support fast accesses. The sub-Arrayed structure applied to the cache produces better scalability in terms of capacity. Evaluation results show that the proposed cache achieves 1.8X fast access speed.

DOI： 10.1109/ISOCC.2016.7799755

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/hpgdmp.2016.010

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

This paper analyzes accuracy of performance models generated by machine learning-based empirical modeling methodology. Although the accuracy strongly depends on the quality of learning procedure, it is not clear what kind of learning algorithms and training data set (or feature) should be used. This paper inclusively explores the learning space of processor performance modeling as a case study. We focus on static architectural parameters as training data set such as cache size and clock frequency. Experimental results show that a tree-based non-linear regression modeling is superior to a stepwise linear regression modeling. Another observation is that clock frequency is the most important feature to improve prediction accuracy.

DOI： 10.1109/JEC-ECC.2016.7518973

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ISOCC.2016.7799721

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Slowdown and inevitable end in exponential scaling of processor performance, the end of the so-called"Moore's Law" is predicted to occur around 2025-2030 timeframe. Because CMOS semiconductor voltage is also approaching its limits, this means that logic transistor power will become constant, and as a result, the system FLOPS will cease to improve, resulting in serious consequences for IT in general, especially supercomputing. Existing attempts to overcome the end of Moore's law are rather limited in their future outlook or applicability. We claim that data-oriented parameters, such as bandwidth and capacity, or BYTES, are the new parameters that will allow continued performance gains for periods even after computing performance or FLOPS ceases to improve, due to continued advances in storage device technologies and optics, and manufacturing technologies including 3-D packaging. Such transition from FLOPS to BYTES will lead to disruptive changes in the overall systems from applications, algorithms, software to architecture, as to what parameter to optimize for, in order to achieve continued performance growth over time. We are launching a new set of research efforts to investigate and devise new technologies to enable such disruptive changes from FLOPS to BYTES in the Post-Moore era, focusing on HPC, where there is extreme sensitivity to performance, and expect the results to disseminate to the rest of IT.

DOI： 10.1145/2903150.2906830

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1145/2903150.2906830

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/jec-ecc.2016.7518973

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

As the power consumption of HPC systems will be a primary constraint for exascale computing, a main objective in HPC communities is recently becoming to maximize power efficiency (i.e., performance per watt) rather than performance. Although programmers have spent a considerable effort to improve performance by tuning HPC programs at a code level, tunings for improving power efficiency is now required. In this work, we select two representative HPC programs (Graph500 and SDPARA) and evaluate how traditional code-level performance tunings applied to these programs affect power efficiency. We also investigate the impacts of the tunings on power efficiency at various operating frequencies of CPUs and/or GPUs. The results show that the tunings significantly improve power efficiency, and different types of tunings exhibit different trends in power efficiency by varying CPU frequency. Finally, the scalability and power efficiency of state-of-the-art Graph500 implementations are explored on both a single-node platform and a 960-node supercomputer. With their high scalability, they achieve 27.43 MTEPS/Watt with 129.76 GTEPS on the single-node system and 4.39 MTEPS/Watt with 1,085.24 GTEPS on the supercomputer.

DOI： 10.1109/BigData.2016.7840624

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

A key challenge in next-generation supercomputing is to effectively schedule limited power resources. Modern processors suffer from increasingly large power variations due to the chip manufacturing process. These variations lead to power inhomogeneity in current systems and manifest into performance inhomogeneity in power constrained environments, drastically limiting supercomputing performance. We present a first-of-its-kind study on manufacturing variability on four production HPC systems spanning four microarchitectures, analyze its impact on HPC applications, and propose a novel variation-aware power budgeting scheme to maximize effective application performance. Our low-cost and scalable budgeting algorithm strives to achieve performance homogeneity under a power constraint by deriving application-specific, module-level power allocations. Experimental results using a 1,920 socket system show up to 5.4X speedup, with an average speedup of 1.8X across all benchmarks when compared to a variation-unaware power allocation scheme.

DOI： 10.1145/2807591.2807638

記述言語：英語  

DOI： 10.1109/MCSoC.2015.5

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Today's computer systems often employ high-throughput accelerators (such as Intel Xeon Phi coprocessors and NVIDIA Tesla GPUs) to improve the performance of some applications or portions of applications. While such accelerators are useful for suitable applications, it remains challenging to predict which workloads will run well on these platforms and to predict the resulting performance trends for varying input.

DOI： 10.1109/ISPASS.2015.7095797

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ISPASS.2015.7095797

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

This paper proposes a new hardware barrier mechanism which offers the flexibility to select which cores should join the synchronization, allowing for executing multiple multi-threaded applications by dividing a many-core processor into several groups. Experimental results based on an RTL simulation show that our hardware barrier achieves a 66-fold reduction in latency over typical software based implementations, with a hardware overhead of the processor of only 1.8%. Additionally, we demonstrate that the proposed mechanism is sufficiently flexible to cover a variety of core groups with minimal hardware overhead.

DOI： 10.1109/ASPDAC.2015.7058982

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ASPDAC.2015.7058982

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Power capping is an essential function for efficient power budgeting and cost management on modern server systems. Contemporary server processors operate under power caps by using dynamic voltage and frequency scaling (DVFS). However, these processors are often deployed in non-uniform memory access (NUMA) architectures, where thread allocation between cores may significantly affect performance and power consumption. This paper proposes a method which maximizes performance under power caps on NUMA systems by dynamically optimizing two knobs: DVFS and thread allocation. The method selects the optimal combination of the two knobs with models based on artificial neural network (ANN) that captures the nonlinear effect of thread allocation on performance. We implement the proposed method as a runtime system and evaluate it with twelve multithreaded benchmarks on a real AMD Opteron based NUMA system. The evaluation results show that our method outperforms a naive technique optimizing only DVFS by up to 67.1%, under a power cap.

DOI： 10.1109/ICCD.2014.6974701

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ICCD.2014.6974701

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/CCGrid.2014.47

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/IPDPS.2014.23

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Recently to achieve the Exa-flops next generation computer system, the power consumption becomes the important issue. On the other hand, the power consumption character of application program is not so considered now. In this study we examine the power character of our Magneto hydrodynamic (MHD) simulation code for the global magnetosphere to evaluate the power consumption behavior of the simulation code under the CPU power capping on the parallel computer system. As a result, it is confirmed that there are different power consumption parts in the MHD simulation code, which the execution performance decreases or does not change under the CPU power capping. This indicates the capability of performance optimization with the power capping.

DOI： 10.1109/CCGrid.2014.47

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Graphics processing units (GPUs) provide an order-of-magnitude improvement on peak performance and performance-per-watt as compared to traditional multicore CPUs. However, GPU-accelerated systems currently lack a generalized method of power and performance prediction, which prevents system designers from an ultimate goal of dynamic power and performance optimization. This is due to the fact that their power and performance characteristics are not well captured across architectures, and as a result, existing power and performance modeling approaches are only available for a limited range of particular GPUs. In this paper, we present power and performance characterization and modeling of GPU-accelerated systems across multiple generations of architectures. Characterization and modeling both play a vital role in optimization and prediction of GPU-accelerated systems. We quantify the impact of voltage and frequency scaling on each architecture with a particularly intriguing result that a cutting-edge Kepler-based GPU achieves energy saving of 75% by lowering GPU clocks in the best scenario, while Fermi- and Tesla-based GPUs achieve no greater than 40% and 13%, respectively. Considering these characteristics, we provide statistical power and performance modeling of GPU-accelerated systems simplified enough to be applicable for multiple generations of architectures. One of our findings is that even simplified statistical models are able to predict power and performance of cutting-edge GPUs within errors of 20% to 30% for any set of voltage and frequency pair.

DOI： 10.1109/IPDPS.2014.23

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/CASES.2013.6662514

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Optimizing the performance in multiprogrammed environments, especially for workloads composed of multi-threaded programs is a desired feature of runtime management system in future manycore processors. At the same time, power capping capability is required in order to improve the reliability of microprocessor chips while reducing the costs of power supply and thermal budgeting. This paper presents a sophisticated runtime coordinated power-performance management system called C-3PO, which optimizes the performance of manycore processors under a power constraint by controlling two software knobs: thread packing, and dynamic voltage and frequency scaling (DVFS). The proposed solution distributes the power budget to each program by controlling the workload threads to be executed with appropriate number of cores and operating frequency. The power budget is distributed carefully in different forms (number of allocated cores or operating frequency) depending on the power-performance characteristics of the workload so that each program can effectively convert the power into performance. The proposed system is based on a heuristic algorithm which relies on runtime prediction of power and performance via hardware performance monitoring units. Empirical results on a 64-core platform show that C-3PO well outperforms traditional counterparts across various PARSEC workload mixes.

DOI： 10.1109/PACT.2013.6618803

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/PACT.2013.6618803

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1587/transinf.E96.D.2268

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1587/transinf.E96.D.1645

記述言語：英語  

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1145/2489068.2489071

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Nowadays, the trend of developing micro-processor with tens of cores brings a promising prospect for embedded systems. Realizing a high performance and low power many-core processor is becoming a primary technical challenge. We are currently developing a many-core processor architecture for embedded systems as a part of a NEDO's project. This paper introduces the many-core architecture called SMYLEref along whit the concept of Virtual Accelerator on Many-core, in which many cores on a chip are utilized as a hardware platform for realizing multiple virtual accelerators. We are developing its prototype system with off-the-shelf FPGA evaluation boards. In this paper, we introduce the architecture of SMYLEref and the detail of the prototype system. In addition, several initial experiments with the prototype system are also presented.

DOI： 10.1109/ASPDAC.2013.6509656

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

This paper introduces a manycore research project called SMYLE (Scalable ManYcore for Low Energy computing). The aims of this project are: 1) proposing a manycore SoC architecture and developing a suitable programming and execution environment, 2) designing a domain specific manycore system for emerging video mining applications, and 3) releasing developed software tools and FPGA emulation environments to accelerate manycore research and development in the community. The project started in December 2010 with full support from the New Energy and Industrial Technology Development Organization (NEDO).

DOI： 10.1109/ASPDAC.2013.6509655

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

This paper proposes a new last level cache architecture called line sharing cache (LSC), which can reduce the number of cache misses without increasing the size of the cache memory. It stores lines which contain the identical value in a single line entry, which enables to store greater amount of lines. Evaluation results show performance improvements of up to 35% across a set of SPEC CPU2000 benchmarks.

DOI： 10.1109/ASPDAC.2013.6509677

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

This paper presents a hybrid compile and run-time memory management technique for a 3D-stacked reconfigurable accelerator including a memory layer composed of multiple memory units whose parallel access allows a very high bandwidth. The technique inserts allocation, free and data transfers into the code for using the memory layer and avoids memory overflows by adding a limited number of additional copies to and from the host memory. When compile-time information is lacking, the technique relies on run-time decisions for controlling these memory operations. Experiments show that, compared to a pessimistic approach, the overhead for avoiding overflows can be cut on average by 27%, 45% and 63% when the size of each memory unit is respectively 1kB, 128kB and 1MB.

DOI： 10.1109/CASES.2013.6662514

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ASPDAC.2013.6509656

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ASPDAC.2013.6509655

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/IISWC.2013.6704675

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ASPDAC.2013.6509677

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/IISWC.2013.6704675

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

This paper proposes a novel many-core execution strategy for real-time model predictive controls. The key idea is to exploit predicted input values, which are produced by the model predictive control itself, to speculatively solve an op- timal control problem. It is well known that control appli- cations are not suitable for multi- or many-core processors, because feedback-loop systems inherently stand on sequen- tial operations. Since the proposed scheme does not rely on conventional thread-/data-level parallelism, it can be easily applied to such control systems. An analytical evaluation using a real application demonstrates the potential of per- formance improvement achieved by the proposed speculative executions.

DOI： 10.1145/2489068.2489071

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/DSD.2012.15

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

We propose a three-dimensional (3D) reconfigurable data-path accelerator which is capable of running partitioned large data flow graphs (DFGs) on the layers of 3D stack, while inter-layer connections are implemented by means of through-silicon vias (TSVs). A tool for mapping data flow graphs has been developed, and a key 3D-specific problem namely routing nets on 3D architecture has been discussed in details as well. Conducted experiments demonstrate smaller footprint area and higher performance for the 3D accelerator comparing with 2D counterpart.

DOI： 10.1109/DSD.2012.15

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1007/s11227-010-0505-0

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Multicore processors have been popular for years, and the industry is gradually shifting towards the era of manycore processors. Single-thread performance of microprocessors is not growing at a historical rate, but the existence of a num- ber of active processes in the computer system and the con- tinuing development of multi-threaded applications benefit from the growing core counts to sustain system throughput. This trend brings us a situation where a number of paral- lel applications simultaneously being executed on a single system. Since multi-threaded applications try to maximize its throughput by utilizing the whole system, each of them usually create equal or larger number of threads compared to underlying logical core counts. This introduces much greater number of threads to be co-scheduled in the entire system. However, each program has different characteristics (or scalability) and contends for shared resources, which are the CPU cores and memory hierarchies, with each other. Therefore, it is clear that OS thread scheduling will play a major role in achieving high system performance under such conditions. We develop a sophisticated scheduler that (1) dynamically predicts the scalability of programs via the use of hardware performance monitoring units, (2) decides the optimal number of cores to be allocated for each program, and (3) allocates the cores to programs while maximizing the system utilization to achieve fair and maximum perfor- mance. The evaluation results on a 48-core AMD Opteron system show improvements over the Linux scheduler for a variety of multiprogramming workloads.

DOI： 10.1145/2370816.2370833

記述言語：日本語  

記述言語：日本語  

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1145/2370816.2370833

記述言語：英語  

本稿では，3次元積層DRAMの利用を前提とし，大幅なチップ面積の増加をともなうことなく高いメモリ性能を達成可能な新しいキャッシュ・アーキテクチャを提案する．3次元積層されたDRAMを大容量キャッシュとして活用することで，オフチップメモリ参照回数の劇的な削減が期待できる．しかしながら，キャッシュの大容量化はアクセス時間の増加を招くため，場合によっては性能が低下する．この問題を解決するため，提案方式では，実行対象プログラムのワーキングセット・サイズに応じて3次元積層DRAMキャッシュを選択的に活用する．ベンチマークプログラムを用いた定量的評価を行った結果，提案方式は動的制御方式により平均メモリアクセス時間を15%削減した．This paper proposes a novel cache architecture for 3D-implemented microprocessors. 3D-IC is one of the most interesting techniques to achieve high-performance, low-power VLSI systems. Stacking multiple dies makes it possible to implement microprocessor cores and large caches (or DRAM) into the same chip. Unfortunately, applying the 3D DRAM cache causes performance degradation for some programs, because increasing cache size makes access time longer. To tackle this issue, the proposed cache supports two operation modes: a fast but small SRAM cache mode and a slow but large DRAM cache mode. An appropriate operation mode is selected at run time based on the behavior of application programs. The evaluation results show that the proposed approach achieves 15% of memory performance improvement.

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ISOCC.2012.6407075

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

This paper proposes static task mapping techniques for embedded many-core SoCs. The proposed techniques take into account both task and data parallelisms of the tasks in order to efficiently utilize the potential parallelism of the many-core architecture. Two approaches are proposed for static mapping: one approach is based on integer linear programming and the other is based on a greedy algorithm. In addition, a static mapping technique considering dynamic task switching is proposed. Experimental results show the effectiveness of the proposed techniques.

DOI： 10.1109/ISOCC.2012.6407075

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

3D stacked multi-core processor is one of the applications of 3D integration technology. It achieves high bandwidth access to last level cache and allows to increase the number of cores while maintaining the package area. Although, 3D multi-core temperature increases with the number of stacked dies because of the escalating power density and thermal resistivity. Therefore, 3D multi-cores require lower clock frequencies for keeping the temperature under a safe constraint, so that performance is not always improved. In this paper, we evaluate the performance of 3D stacked multi-cores running under temperature constraints, and we show that there is a trade-off between clock frequency and parallel capability.

DOI： 10.1109/3DIC.2012.6263025

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1587/transinf.E94.D.2298

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

This paper introduces our research status focusing on 3D-implemented microprocessors. 3D-IC is one of the most interesting techniques to achieve high-performance, low-power VLSI systems. Stacking multiple dies makes it possible to implement microprocessor cores and large caches (or DRAM) into the same chip. Although this kind of integration has a great potential to bring a breakthrough in computer systems, its efficiency strongly depends on the characteristics of target application programs. Unfortunately, applying die stacking implementation causes performance degradation for some programs. To tackle this issue, we introduce a novel cache architecture consisting of a small but fast SRAM and a stacked large DRAM. The cache attempts to adapt to varying behavior of application programs in order to compensate for the negative impact of the die stacking approach.

DOI： 10.1109/MWSCAS.2011.6026484

記述言語：英語  

DOI： 10.1109/ISLPED.2011.5993616

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/CCECE.2011.6030605

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/3DIC.2012.6263025

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/3DIC.2012.6263034

記述言語：英語  

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1016/j.sysarc.2010.07.009

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Thermal management is one of the main concerns in three-dimensional integration due to difficulty of dissipating heat through the stack of the integrated circuit. In a 3D stack involving a data-path accelerator, a base processor and memory components, peak temperature reduction is targeted in this paper. A mapping algorithm has been devised in order to distribute operations of data flow graphs evenly over the processing elements of the target accelerator in two steps involving thermal-aware partitioning of input data flow graphs, and thermal-aware mapping of the partitions onto the processing elements. The efficiency of the proposed technique in reducing peak temperature is demonstrated throughout the experiments.

DOI： 10.1109/3DIC.2012.6263034

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Dedicated tools for placing and routing data flow graphs extracted from computation-intensive applications are basic requirements for developing applications on a large-scale reconfigurable data-path processor (LSRDP) implemented by superconductivity circuits. Using an alternative technology instead of CMOS circuits for implementing such hardware entails considering particular constraints and conditions from the architecture and tools development perspectives. The main contribution of this work is to introduce an operand routing network (ORN) architecture as well as algorithms for routing the nets corresponding to the edges of the data flow graphs. Further, a micro-routing algorithm is proposed for routing and configuring the ORNs internally. These algorithms have been applied on a number of data flow graphs from target applications and the results demonstrate their efficacy.

DOI： 10.1109/CCECE.2011.6030605

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Single-Flux Quantum based large-scale data-path processor (SFQ-LSRDP) is a reconfigurable computing system which is implemented by means of superconductivity circuits. SFQ-LSRDP has a capability of accelerating data flow graphs (DFGs) extracted from scientific applications. Using an alternative technology instead of CMOS circuits for implementing such hardware entails considering particular constraints and conditions from the architecture and tools development perspectives. In this paper, we will introduce hardware specifications of the LSRDP and the tool chain developed for implementing applications. Placing and routing data flow graphs is a fundamental part to develop applications on the SFQ-LSRDP. Algorithms for placing DFG operations and routing nets corresponding to the edges of data flow graphs will be discussed in more details. These algorithms have been applied on a number of data flow graphs and the results demonstrate their efficiency. Further, simulation results demonstrates remarkable performance numbers in the range of hundreds of Gflops for the proposed architecture.

DOI： 10.1109/ASQED.2011.6111751

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/DATE.2010.5456902

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

To overcome issues originating from the CMOS technology, a large-scale reconfigurable data-path (LSRDP) processor based on single-flux quantum circuits is introduced. LSRDP is augmented to a general purpose processor to accelerate the execution of data flow graphs (DFGs) extracted from scientific applications. Procedure of mapping large DFGs onto the LSRDP is discussed and our proposed techniques for reducing area of the accelerator within the design procedure will be introduced as well.

DOI： 10.1109/date.2010.5456902

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1587/transfun.E92.A.3182

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Multitude parameters in the design process of a reconfigurable instruction-set processor (RISP) may lead to a large design space and remarkable complexity. Quantitative design approach uses the data collected from applications to satisfy design constraints and optimize the design goals while considering the applications' characteristics; however it highly depends on designer observations and analyses. Exploring design space can be considered as an effective technique to find a proper balance among various design parameters. Indeed, this approach would be computationally expensive when the performance evaluation of the design points is accomplished based on the synthesis-and-simulation technique. A combined analytical and simulation-based model (CAnSO**) is proposed and validated for performance evaluation of a typical RISP. The proposed model consists of an analytical core that incorporates statistics collected from cycle-accurate simulation to make a reasonable evaluation and provide a valuable insight. CAnSO has clear speed advantages and therefore it can be used for easing a cumbersome design space exploration of a reconfigurable RISP processor and quick performance evaluation of slightly modified architectures.

DOI： 10.1587/transfun.E92.A.3182

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

This paper proposes the concept of performance balancing, and reports its performance impact on a Chip multiprocessor (CMP). Integrating multiple processor cores into a single chip, or CMPs, can achieve higher peak performance by means of exploiting thread level parallelism. However, the off-chip memory bandwidth which does not scale with the number of cores tends to limit the potential of CMPs. To solve this issue, the technique proposed in this paper attempts to make a good balance between computation and memorization. Unlike conventional parallel executions, this approach exploits some cores to improve the memory performance. These cores devote the on-chip memory hardware resources to the remaining cores executing the parallelized threads. In our evaluation, it is observed that our approach can achieve 31% of performance improvement compared to a conventional parallel execution model in the specified program.

DOI： 10.1145/1621960.1621966

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

The memory bandwidth can dramatically be improved by means of stacking the main memory (DRAM) on processor cores and connecting them by wide on-chip buses composed of through silicon vias (TSVs). The 3D stacking makes it possible to reduce the cache miss penalty because large amount of data can be transferred from the main memory to the cache at a time. If a large cache line size is employed, we can expect the effect of prefetching. However, it might worsen the system performance if programs do not have enough spatial localities of memory references. To solve this problem, we introduce software-controllable variable line-size cache scheme. In this paper, we apply it to an L1 data cache with 3D stacked DRAM organization. In our evaluation, it is observed that our approach reduces the L1 data cache and stacked DRAM energy consumption up to 75%, compared to a conventional cache.

DOI： 10.1109/SOCDC.2009.5423920

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

This paper introduces an energy efficient acceleration technique for embedded microprocessors. By means of supporting an ALU-array based coarse-grain reconfigurable functional unit, well customized special instructions are identified and executed for each application program. Since the reconfigurable functional unit can execute several dependent instructions (a sequence of instructions), simultaneously, the performance of the base microprocessor can dramatically be improved. In addition, this kind of direct execution is very energy efficient because it reduces activation counts of hardware components such as instruction cache, branch predictor, register-file accesses, and so on.

DOI： 10.1109/SOCDC.2009.5423898

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/socdc.2009.5423920

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1145/1621960.1621966

記述言語：英語  

記述言語：英語  

We report the progress in the development of an Operand Routing Network (ORN) for an SFQ Reconfigurable Data-Paths processor (SFQ-RDP). The SFQ-RDP is implemented as a two-dimensional array of Floating-Point Units (FPU), outputs of which can be connected to the inputs of one or more FPUs in the next row via ORN. We have considered two architectures of the ORN: one is based on NDRO switches and the other-on crossbar switches. The comparison shows that the crossbar-based ORN has better performance due to the regular pipelined structure. We have designed a crossbar switch with a multicasting function and a l-to-2 ORN prototype for 2.5 kA/cm² process. The circuits have been experimentally tested at the frequencies up to 36 GHz.

DOI： 10.1109/TASC.2009.2018534

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1587/transele.e92.c.433

記述言語：英語   掲載種別：研究論文（学術雑誌）  

This paper proposes a software-controllable variable line-size (SC-VLS) cache architecture for low power embedded systems. High bandwidth between logic and a DRAM is realized by means of advanced integrated technology. System-in-Silicon is one of the architectural frameworks to realize the high bandwidth. An ASIC and a specific SRAM are mounted onto a silicon interposer. Each chip is connected to the silicon interposer by eutectic solder bumps. In the framework, it is important to reduce the DRAM energy consumption. The specific DRAM needs a small cache memory to improve the performance. We exploit the cache to reduce the DRAM energy consumption. During application program executions, an adequate cache line size which produces the lowest cache miss ratio is varied because the amount of spatial locality of memory references changes. If we employ a large cache line size, we can expect the effect of prefetching. However, the DRAM energy consumption is larger than a small line size because of the huge number of banks are accessed. The SC-VLS cache is able to change a line size to an adequate one at runtime with a small area and power overheads. We analyze the adequate line size and insert line size change instructions at the beginning of each function of a target program before executing the program. In our evaluation, it is observed that the SC-VLS cache reduces the DRAM energy consumption up to 88%, compared to a conventional cache with fixed 256 B lines.

DOI： 10.1587/transele.E92.C.433

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ASPDAC.2009.4796540

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. The conventional approaches based on synthesis and simulations are very time consuming and need a considerable design effort. A combined analytical and simulation-based model (CAnSO ) is proposed and validated for performance evaluation of a typical reconfigurable instruction set processor. The proposed model consists of an analytical core that incorporates statistics gathered from cycle-accurate simulation to make a reasonable evaluation and provide a valuable insight. Compared to cycle-accurate simulation results, CAnSO proves almost 2% variation in the speedup measurement.

DOI： 10.1109/ASPDAC.2009.4796540

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1587/transele.E92.C.1231

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Data prefetching is a well known approach to compensating for poor memory performance, and has been employed in commercial processor chips. Although a number of prefetching techniques have so far been proposed, in many cases, they have assumed single-core architectures. In Chip Multiprocessor (or CMP) chips, there are some shared resources such as L2 caches, buses, and so on. Therefore, the effect of prefetching on CMP should be different from traditional single-core processors. In this paper, we analyze the effect of prefetching on CMP performance. This paper first classifies the impact of prefetches issued during program execution. Then, we discuss quantitatively the effect of prefetching to memory performance. The experimental results show that the negative effect of invalidation of prefetched cache blocks is very small. In addition, it is observed that the current prefetch algorithms do not exploit effectively the feature of CMPs, i.e. cache-to-cache on-chip data transfer.

DOI： 10.1109/APCSAC.2008.4625454

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

In the design of embedded systems, especially batterypowered systems, it is important to reduce energy consumption. Cache are now used not only in general-purpose processors but also in embedded processors. As feature sizes shrink, the leakage energy has contributed to a significant portion of total energy consumption. To reduce the leakage energy of cache, the Drowsy cache was proposed, in which the cache lines are periodically moved to the lowleakage mode without loss of its content. However, when a cache line in the low-leakage mode is accessed, one or more clock cycles are required to transition the cache line back to the normal mode before its content can be accessed. As a result, these penalty cycles may significantly degrade the cache performance, especially in embedded processors without out-of-order execution. In this paper, we propose four mode transition policies which aim at high energy reduction with the minimum performance degradation. We also compare our policies with existing policies in the context of embedded processors. Experimental results demonstrate the effectiveness of the proposed policies.

DOI： 10.1109/DELTA.2008.70

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/APCSAC.2008.4625454

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of digital systems continues to grow. Temperature is another factor that exponentially increases the leakage current. In this paper, we show the effect of temperature on the optimal (minimum-energy-consuming) cache configuration for low energy embedded systems. Our results show that for a given application and technology, the optimal cache size moves toward smaller caches at higher temperatures, due to the larger leakage. Our results show that using a Temperature-Aware Configurable Cache (TACC), up to 61% energy can be saved for instruction cache and 77% for data cache compared to a configurable cache that has been configured for only the corner case temperature (100°C). The TACC also enhances the performance by up to 28% and 17% for the instruction and data cache, respectively.

DOI： 10.1109/ISVLSI.2008.24

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

In the design process of a reconfigurable accelerator employing in an embedded system, multitude parameters may result in remarkable complexity and a large design space. Design space exploration as an alternative to the quantitative approach can be employed to find a right balance between the different design parameters. In this paper, a hybrid approach is introduced to analytically explore the design space for a coarse grain accelerator and determine a wise design point exploiting data extracted from applications, quantitatively. It also provides flexibility for taking into account new design constraints as well as new characteristics of applications. Furthermore, this approach is a methodological approach which reduces the design time and results in a point which satisfies the design goals.

DOI： 10.1109/ASPDAC.2008.4484039

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1145/1393921.1393987

記述言語：英語  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Reconfiguration latency has a significant impact on the system performance in reconfigurable systems. A temporal partitioning approach is introduced for partitioning data flow graphs for a reconfigurable system comprising a partial programmable fine-grained hardware. Residing eligibility inspired from the Universal gravitation law is introduced to depict the eligibility of a node to stay in succeeding configurations (partitions) and to prohibit it from being swapped in/out. Partitioning based on residing eligibility causes fewer nodes with different functionalities to be assigned to subsequent partitions. Thus, reconfiguration overhead time and also unused hardware space decreases due to common parts in consecutive configurations.

DOI： 10.1587/elex.5.366

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1587/elex.5.366

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ISVLSI.2008.24

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1093/ietele/e91-c.4.418

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Encapsulating critical computation subgraphs as application-specific instruction set extensions is an effective technique to enhance the performance of embedded processors. However, the addition of custom functional units to the base processor is required to support the execution of these custom instructions. Although automated tools have been developed to reduce the long design time needed to produce a new extensible processor for each application, short time-to-market, significant non-recurring engineering and design costs are issues. To address these concerns, we introduce an adaptive extensible processor in which custom instructions are generated and added after chip-fabrication. To support this feature, custom functional units (CFUs) are replaced by a reconfigurable functional unit (RFU). The proposed RFU is based on a matrix of functional units which is multi-cycle with the capability of conditional execution. A quantitative approach is utilized to propose an efficient architecture for the RFU and fix its constraints. To generate more effective custom instructions, they are extended over basic blocks and hence, multiple exits custom instructions are proposed. Conditional execution has been added to the RFU to support the multi-exit feature of custom instructions. Experimental results show that multi-exit custom instructions enhance the performance by an average of 67% compared to custom instructions limited to one basic block. A maximum speedup of 4.7, compared to a general embedded processor, and an average speedup of 1.85 was achieved on MiBench benchmark suite.

DOI： 10.1093/ietele/e91-c.4.497

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1093/ietele/e91-c.3.350

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/DELTA.2008.70

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ASPDAC.2008.4484039

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1007/s11227-008-0174-4

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1093/ietele/e91-c.4.497

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Application-specific instruction set extension is an effective technique for reducing accesses to components such as on- and off-chip memories, register file and enhancing the energy efficiency. However, the addition of custom functional units to the base processor is required for supporting custom instructions, which due to the increase of manufacturing and design costs in new nanometer-scale technologies and shorter time-to-market, is becoming an issue. To address above issues, in our proposed approach, an optimized reconfigurable functional unit is used instead, and instruction set customization is done after chip-fabrication. Therefore, while maintaining the flexibility of a conventional microprocessor, the low-energy feature of customization is applicable. Experimental results show that the maximum and average energy savings are 67% and 22%, respectively for our proposed architecture framework.

DOI： 10.1145/1393921.1393987

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

To predict application performance on an HPC system is an important technology for designing the computing system and developing applications. However, accurate prediction is a challenge, particularly, in the case of a future coming system with higher performance. In this paper, we present a new method for predicting application performance on HPC systems. This method combines modeling of sequential performance on a single processor and macro-level simulations of applications for parallel performance on the entire system. In the simulation, the execution flow is traced but kernel computations are omitted for reducing the execution time. Validation on a real terascale system showed that the predicted and measured performance agreed within 10% to 20 %. We employed the method in designing a hypothetical petascale system of 32768 SIMD-extended processor cores. For predicting application performance on the petascale system, the macro-level simulation required several hours.

DOI： 10.1109/SC.2008.5220091

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Performance evaluation is a serious challenge in designing optimizing reconfigurable instruction set processors. A combined and simulation-based model (CAnSO?) is proposed and for performance evaluation of a typical reconfigurable set processor. The proposed model consists of an core that incorporates statistics gathered from cycleaccurate to make a reasonable evaluation. CAnSO has speed advantages and compared to cycle-accurate simulation, proves almost 2% variation in the speedup measurement.

DOI： 10.1109/SOCDC.2008.4815603

記述言語：英語  

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1093/ietisy/e90-d.12.1956

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

This talk presents an overview of the Petascale System Interconnect (PSI) project. The PSI project is one of the national projects on "Fundamental Technologies for the Next Generation Supercomputing" of MEXT (Ministry of Education, Culture Sports, Science and Technology), Japan. The goal of the PSI project is to develop technologies enabling petascale supercomputing systems with hundreds of thousands of computing nodes. The PSI project consists of three subprojects to tackle with the three fundamental technologies: subproject 1 is for the small and efficient optical packet switches; subproject 2 is for the low-cost & high-performance MPI communications; and subproject 3 is for the methodologies of evaluating and estimating the performance of petascale systems. With the successful completion of the PSI project, the Japan Next-Generation Supercomputer R&D Center (NSC) will take the technologies to build Japan's next generation supercomputer, which is expected to be over 70 times faster than the current fastest supercomputers.

DOI： 10.1063/1.2827008

記述言語：英語  

We have designed a reconfigurable data-path (RDP) prototype based on the single-flux-quantum (SFQ) circuit. The RDP serves as an accelerator for a high performance computer and is composed of many stages of the array of floating point number processing units (FPUs) connected by reconfigurable operand routing networks (ORNs). The FPU array usually includes shift-registers (SRs) in order that the data is forwarded to the next stage without calculation. The data-path is reconfigured so as to reflect a long repeat instruction appearing in large-scale calculations. We can implement parallel and pipelined processing without memory access in such calculations, reducing the required bandwidth between a memory and a microprocessor. The SFQ high speed network switches and bit-serial/slice FPUs realize reduction in the circuit areas and in the power consumption compared to semiconductor devices when we make up the RDP by using the SFQ circuit. As a first step of the development of the SFQ-RDP, we design a 2 × 2 RDP prototype composed of double arrays of dual arithmetic logic units (ALUs). The prototype also has dual SRs in each array and four ORNs. We use bit-serial ALUs designed to operate at 25GHz. Each ORN behaves like a 4 × 2 crossbar switch. We have demonstrated the reconfiguration in the RDP prototype made up of 15 050 Josephson junctions though only some of the functions of ALUs are available.

DOI： 10.1088/0953-2048/20/11/S06

記述言語：英語  

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1093/ietele/e90-c.10.1972

記述言語：その他   掲載種別：研究論文（学術雑誌）  

記述言語：日本語  

記述言語：日本語  

本稿では、高速かつ正確なメモリアーキテクチャ・シミュレーション法を提案する。一般に、メモリアーキテクチャの評価には、メモリ参照のアドレス・トレースに基づいたシミュレーションを行う。しかしながら、評価対象の増加により、評価時間が長くなる傾向にある。トレースに基づくシミュレーションにおいて、1 回あたりのシミュレーション時間はアドレス・トレースの削減によって短縮できるが、精度が低下するという問題がある。そこで、本手法はメモリアクセスの特徴を活用して高い精度維持しつつトレース・サイズを削減し、シミュレーション時間の短縮を実現する。キャッシュ性能測定に基づく評価実験の結果、本手法はトレース・サイズを平均 98.8％削減し、そのときのキャッシュ・ミス率の予測誤差は平均 0.067 パーセンテージ・ポイントであった。This paper proposes a fast and accurate memory architecture simulation technique. To design memory architecture, the first steps commonly involve using trace-driven simulation. However, expanding the design space makes the evaluation time increase. A fast simulation is achieved by a trace size reduction, but it reduces the simulation accuracy. Our approach can reduce the simulation time while maintaining the accuracy of the simulation results. In order to evaluate validity of proposed technique, we measured the cache miss ratio. In our evaluation, the proposed technique reduces the trace size 98.8％ and cache miss ratio differs from 0.067 percentage point on an average.

DOI： 10.15017/8308

記述言語：日本語  

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1007/978-3-540-72685-2_24

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/DATE.2007.364612

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1145/1228784.1228891

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

To improve the performance of embedded processors, an effective technique is collapsing critical computation subgraphs as application-specific instruction set extensions and executing them on custom functional units. The problems of this approach are immense cost and long time of designing. To address these issues, we propose an adaptive extensible processor in which custom instructions (CIs) are generated and added after chip-fabrication. To support this feature, custom functional units are replaced by a reconfigurable matrix of functional units with the capability of conditional execution. Unlike previous proposed CIs, ours can include multiple exits. Experimental results show that multi-exit CIs enhance the performance by 46% in average compared to CIs limited to one basic block. A maximum speedup of 2.89 compared to a 4-issue in-order RISC processor, and a speedup of 1.66 in average, was achieved on MiBench benchmark suite.

DOI： 10.1109/DATE.2007.364612

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Energy consumption is a major concern in embedded computing systems. Several studies have shown that cache memories account for about 40% or more of the total energy consumed in these systems. In older technology nodes, active power was the primary contributor to total power dissipation of a CMOS design. However, with the scaling of feature sizes, the share of leakage in total power consumption of digital systems continues to grow. Temperature is a factor which exponentially increases the leakage current. In this paper, we show the effects of temperature on the selection of optimal cache size for low energy embedded systems. Our results show that for a given application, the optimal cache size selection is affected by the temperature. Our experiments have been done for 100nm technology. Our study reveals that the cache size selection for different temperatures depends on the rate at which cache miss increases when reducing the cache size. When the miss rate increases sharply the optimal point is the same for all examined temperatures, however when it becomes smoother, the optimal point for different temperatures begin to get farther.

DOI： 10.1145/1228784.1228891

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

OpenFMO framework, an open-source software (OSS) platform for Fragment Molecular Orbital (FMO) method, is extended to multi-physics simulations (MPS). After reviewing the several FMO implementations on distributed computer environments, the subsequent development planning corresponding to MPS is presented. It is discussed which should be selected as a scientific software, lightweight and reconfigurable form or large and self-contained form.

DOI： 10.1063/1.2835969

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Various processor architectures have been proposed until today, and the performance has improved remarkably. Recently, the Chip Multi-processors (CMPs), which has many processor cores onto a chip, are proposed for further performance improvement. The Cell processor is one of such CMP and shows high computational performance. Although this processor is designed for the multimedia, that high performance character can be utilized to molecular orbital calculation. In this study we implemented Fock matrix construction program on the Cell processor, and evaluated computational performance. As a result, there were two kinds of main stalls by the branch prediction and the data alignment, which are controlled by software mechanism for the simplification of the Cell processor hardware. It is possible to improve the performance about 30%, if the branch prediction hit ratio could be improved to 99%. For data alignment stall, a part of stalls, which is originated by data shuffle pipeline, could be decreased by preparing hardware data alignment mechanism.

DOI： 10.1063/1.2836167

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

In an embedded system including a base processor integrated with a tightly coupled accelerator, extracting frequently executed portions of the code (hot portion) and executing their corresponding data flow graph (DFG) on the accelerator brings about more speedup. In this paper, we intend to present our motivations for handling control instructions in DFGs and extending them to Control DFGs (CDFGs). In addition, basic requirements for an accelerator with conditional execution support are proposed. Moreover, some algorithms are presented for temporal partitioning of CDFGs considering the target accelerator architectural specifications. To show the effectiveness of the proposed ideas, we applied mem to the accelerator of an extensible processor called AMBER. Experimental results represent the effectiveness of covering control instructions and using CDFGs versus DFGs.

DOI： 10.1007/978-3-540-72685-2_24

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1093/ietele/e89-c.12.1937

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ICECS.2006.379744

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ICECS.2006.379629

記述言語：英語  

DOI： 10.1093/ietfec/e89-a.12.3377

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1007/11859802_18

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1007/11802167_73

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/FPL.2006.311313

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

This paper presents a reconfigurable functional unit (RFU) for an adaptive dynamic extensible processor. The processor can tune its extended instructions to the target applications, after chip-fabrication. The custom instructions (CIs) are generated deploying the hot basic blocks during the training mode. In the normal mode, CIs are executed on the RFU. A quantitative approach was used for designing the RFU. The RFU is a matrix of functional units with 8 inputs and 6 outputs. Performance is enhanced up to 1.25 using the proposed RFU for 22 applications of Mibench. This processor needs no extra opcodes for CIs, new compiler, source code modification and recompilation.

DOI： 10.1109/FPL.2006.311313

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

To address computer security issues, a hardware-based intrusion detection technique is proposed. This uses the dynamic program execution behavior for authentication. Based on secret key information, an execution behavior is determined. Next, a secure compiler constructs object code which generates the predetermined execution behavior at runtime. During program execution, a secure profiler monitors the execution behavior. If the profiler cannot detect the expected behavior, it sends an alarm signal to the microprocessor for terminating program execution. Since attack code cannot anticipate the execution behavior required, malicious attacks can be detected and prohibited at the start of program execution.

DOI： 10.1109/ICECS.2006.379744

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

This paper proposes an efficient cache line management algorithm for a security-aware cache architecture (SCache). SCache attempts to detect the corruption of return address values at runtime. When a return address store is executed, the cache generates a replica of the return address. This copied data is treated as read only. Subsequently, when the corresponding return address load is performed, the cache verifies the return address value loaded from the memory stack by means of comparing it with the replica data. Unfortunately, since the replica data is also a candidate for cache line replacements, SCache does not work well for application programs that cause higher cache miss rates. To resolve this issue, a lock and unlock data management algorithm is proposed in order to improve the security of SCache. The experimental results show that a proposed SCache model can protect about 99% of return address loads from the threat of buffer overflow attacks, while it worsens the processor performance by only 1%, compared with a non-secure conventional cache.

DOI： 10.1109/ICECS.2006.379629

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Extracting appropriate custom instructions is an important phase for implementing an application on an extensible processor with a reconfigurable functional unit (RFU). Custom instructions (CIs) are usually extracted from critical portions of applications. It may not be possible to meet all of the RFU constraints when CIs are generated. This paper addresses the generation of mappable CIs on an RFU. In this paper, our proposed RFU architecture for an adaptive dynamic extensible processor is described. Then, an integrated framework for temporal partitioning and mapping is presented to partition and map the CIs on RFU. In this framework, two mapping aware temporal partitioning algorithms are used to generate CIs. Temporal partitioning iterates and modifies partitions incrementally to generate CIs. Using this framework brings about more speedup for the extensible processor.

DOI： 10.1007/11802167_73

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Extensible processors allow customization for an application by extending the core instruction set architecture. Extracting appropriate custom instructions is an important phase for implementing an application on an extensible processor with a reconfigurable functional unit. Custom instructions (CIs) usually are extracted from critical portions of applications. This paper presents approaches for CI generation with respect to the RFU constraints to improve speedup of the extensible processor. First, our proposed RFU architecture for an adaptive dynamic extensible processor called AMBER is described. Then, an integrated temporal partitioning and mapping framework is presented to partition and map the CIs on the RFU. In this framework, a mapping aware temporal partitioning algorithm is used to generate CIs which are mappable on the RFU. Temporal partitioning iterates and modifies partitions incrementally to generate CIs. In addition, a mapping algorithm is presented which supports CIs with critical path length more than the RFU depth.

DOI： 10.1007/11859802_18

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1093/ietfec/e88-a.12.3274

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ICITA.2005.7

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1093/ietfec/e88-a.4.862

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1145/1055626.1055638

記述言語：英語  

Cache memories are the most area-and energy-consuming units in today’s microprocessors. As the speed disparity between processor and external memory increases, designers try to put large multilevel caches on a chip to reduce the number of external memory accesses and thus boost the system performance. (See Table 8.1 for a survey of the on-die caches for several recent high-end microprocessors.) On-chip data and instruction caches are implemented using arrays of densely packed static RAM cells. The device count for the caches often exceeds the number of transistors devoted to the processor’s datapath and controller. For example, the Alpha21364 [3] and PA-RISC Maco [5] microprocessors have over 90% of their transistors in RAM, with most of them dedicated for caches; the Itanium2 [1] has 80% in caches, the IBM G5 [7] has 72%, the PowerPC [8] has 71%, and Strong-ARM110 [9] has 70%. Due to the large load capacitance and high access rate, these caches account for significant portion of the overall power dissipation (e.g., 35% in Itanium2 [1]; 43% in Strong-ARM [9]). Therefore optimizing caches for power is increasingly important. Although much work on energy reduction has taken place in the circuit and technology domains [10,11], interest in cache design for power efficiency at the architectural level continues to increase. Architecture is the entry point in cache design hierarchy, and decisions taken at this level can drastically affect the efficiency of design.

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

In order to maintain the high reliability of a computer system, it is necessary to detect the failure leading to a fault. In general, fault can be detected by exploiting time redundancy or spatial redundancy. However, it negatively affects on either hardware cost or processor performance. To solve the cost-performance issue, in this paper, we propose a concept of cost-effective approach to achieve spatial redundancy for dependable processors. In addition, we perform a primly evaluation for the impact of our method on processor performance.

DOI： 10.1109/ICITA.2005.7

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ISSOC.2004.1411147

記述言語：英語  

Cache memories are the most area- and energy-consuming units in today’s microprocessors. As the speed disparity between processor and external memory increases, designers try to put large multilevel caches on a chip to reduce the number of external memory accesses and thus boost the system performance. (See Table 25.1 for a survey of the on-die caches for several recent high-end microprocessors.) On-chip data and instruction caches are implemented using arrays of densely packed static RAM cells. The device count for the caches often exceeds the number of transistors devoted to the processor’s datapath and controller. For example, the Alpha21364 [3] and PA-RISC Maco [5] microprocessors have over 90% of their transistors in RAM, with most of them dedicated for caches; the Itanium2 [1] has 80% in caches, the IBM G5 [7] has 72%, the PowerPC [8] has 71%, and Strong-ARM110 [9] has 70%. Due to the large load capacitance and high access rate, these caches account for significant portion of the overall power dissipation (e.g., 35% in Itanium2 [1]; 43% in Strong-ARM [9]). Therefore optimizing caches for power is increasingly important. Although much work on energy reduction has taken place in the circuit and technology domains [10,11], interest in cache design for power efficiency at the architectural level continues to increase. Architecture is the entry point in cache design hierarchy, and decisions taken at this level can drastically affect the efficiency of design.

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

This paper reports design and evaluation results of a low-energy I-cache architecture, called history-based tag-comparison (HBTC) cache. The HBTC cache attempts to re-use tag-comparison results to detect and eliminate unnecessary memory-array activations. We have performed cycle accurate simulations, and have designed an SRAM core based on a 0.18 μm CMOS technology. As a result, it has been observed that the HBTC approach can achieve 60% of energy reduction, with only 0.3% performance degradation, compared to a conventional cache. Furthermore, we have also evaluated the potential of the HBTC cache by combining with other low-energy techniques.

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

The designing of a low-power TCP/IP hardcore for pervasive computing was discussed. In order to implement the TCP/IP operations in hardware, the TCP and IP functions were partitioned into four modules which were port_ctr, data_ctr, window_ctr, and checksum. It was found that the data_ctr consumed about 22-30% of total power. The power consumption of TCP core and IP core were compared and it was found that the power consumed by the TCP was almost double of that of the IP core.

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1007/978-3-540-39864-6_10

記述言語：その他   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

The paper proposes a new computationally efficient technique for DCT operation. Unlike related research, the technique reduces the number of computations by predicting the effect of quantization on DCT and avoiding calculations of those DCT values which lead to zero elements in the block after quantization. Experimental evaluation on a number of video benchmarks shows that our method is able to reduce the total number of computations by 29% for DCT and by 59% for quantization while maintaining high image quality.

DOI： 10.1109/SIPS.2003.1235663

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

This paper proposes an architecture for low-power directmapped instruction caches, called “history-based tag-comparison (HBTC) cache”. The HBTC cache attempts to detect and omit unnecessary tag checks at run time. Execution footprints are recorded in an extended BTB (Branch Target Buffer), and are used to know the cache residence of target instructions before starting cache access. In our simulation, it is observed that our approach can reduce the total count of tag checks by 90 %, resulting in 15 % of cache-energy reduction, with less than 0.5 % performance degradation.

DOI： 10.1007/3-540-36612-1_2

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/APCCAS.2002.1115097

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/APCCAS.2002.1115094

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1145/566408.566447

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1145/566408.566446

記述言語：英語   掲載種別：研究論文（学術雑誌）  

In this paper, we propose a novel architecture for low-power direct-mapped instruction caches, called "history-based tag-comparison (HBTC) cache." The cache attempts to reuse tag-comparison results for avoiding unnecessary tag checks. Execution footprints are recorded into an extended BTB (Branch Target Buffer). In our evaluation, it is observed that the energy for tag comparison can be reduced by more than 90% in many applications.

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1007/3-540-36612-1_2

記述言語：英語   掲載種別：研究論文（学術雑誌）  

One of uncompromising requirements from portable computing is energy efficiency, because that affects directly the battery life. On the other hand, portable computing will target more demanding applications, for example moving pictures, so that higher performance is still required. Cache memories have been employed as one of the most important components of computer, systems. In this paper, we briefly survey architectural techniques for high performance, low power cache memories.

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ICCD.2002.1106768

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1007/3-540-45716-X_28

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

This paper presents an experimental study of register file utilization in conventional RISC-type data path architecture to determine benefits that we can expect to achieve by eliminating unnecessary register file reads and writes. Our analysis shows that operand bypassing, enhanced for operand-reuse can discard the register file accesses up to 65% as a peak and by 39% on average for tested benchmark programs.

DOI： 10.1007/3-540-45716-x_28

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

The design of portable battery operated multimedia devices requires energy-efficient multiplication circuits. This paper presents a novel approach to reduce power consumption of digital multiplier based on dynamic bypassing of partial products. The bypassing elements incorporated into the multiplier hardware eliminate redundant signal transitions, which appear within the carry-save adders when the partial product is zero. Simulations on the real-life DCT data show that the proposed approach can improve power saving of related methods by 12%, while jointly with them, it reduces the power consumption of a 16x16 digital CMOS multiplier by 31%, with 25% area overhead and less than 4% performance degradation in the worst case. The circuit implementation is outlined.

DOI： 10.1109/APCCAS.2002.1115097

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

This paper proposes a new approach to reducing the power consumption of instruction ROMs for embedded systems. The power consumption of instruction ROMs strongly depends on the switching activity of bit-lines. If a read bit-value indicates '0', the precharged bitline is discharged. In this scenario, a bit-line switching takes place and consumes power. Otherwise, the precharged bit-line level is maintained until the next access, thus no bit-line switching occurs. In our approach, the binary-patterns to be assigned to op-codes are determined based on the frequency of instructions for reducing the bit-line switching activity. Application programs are analyzed in advance, and then binary-patterns including many '1's' are assigned to the most frequently referenced instructions. In our evaluation, it is observed that the proposed approach can reduce bit-line switching by 40%.

DOI： 10.1109/APCCAS.2002.1115094

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1007/3-540-44570-6_13

記述言語：英語  

This paper proposes an on-chip memory-path architecture employing the dynamically variable line-size (D-VLS) cache for high performance and low energy consumption. The D-VLS cache exploits the high on-chip memory bandwidth attainable on merged DRAM/logic LSIs by replacing a whole large cache line in one cycle. At the same time, it attempts to avoid frequent evictions by decreasing the cache-line size when programs have poor spatial locality. Activating only on-chip DRAM subarrays corresponding to a replaced cache-line size produces a significant energy reduction. Ln our simulation, it is observed that our proposed on-chip memory-path architecture, which employs a direct-mapped D-VLS cache, improves the ED (Energy Delay) product by more than 75% over a conventional memory-path model.

記述言語：英語  

This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called "dynamically variable line-size cache (D-VLS cache)." The D-VLS cache ran optimize its line-size according to the characteristic of programs, and attempts to improve the performance by exploiting the high on-chip memory bandwidth on merged DRAM/logic LSIs appropriately. In our evaluation, it is observed that an average memory access time improvement achieved by a direct-mapped D-VLS cache is about 20% compared to a conventional direct-mapped cache with tired 32-byte lines. This performance improvement is better than that of a doubled-size conventional direct-mapped cache*.

記述言語：英語  

This paper proposes a new approach to achieving high performance and low energy consumption for set-associative caches. The cache, called way-predicting set-associative cache, speculatively selects a single way, which is likely to contain the data desired by the processor, from the set designated by a memory address, before it starts a normal cache access. By accessing only the single way predicted, instead of accessing all the ways in a set, energy consumption can be reduced. In order for the way-predicting cache to perform well, accuracy of way prediction is important. This paper shows that the accuracy of an MRU (most recently used)-based way prediction is higher than 90% for most of the benchmark programs. The proposed way-predicting cache improves the ED (energy-delay) product by 60-70% compared to the conventional set-associative cache*.

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

We are constructing a high-performance, special-purpose parallel machine for ab initio Molecular Orbital calculations, called MOE (Molecular Orbital calculation Engine). The sequential execution time is O(N⁴) where N is the number of basis functions, and most of time is spent to the calculations of electron repulsion integrals (ERIs). The calculation of ERIs have a lot of parallelism of O(N⁴), and therefore MOE tries to exploit the parallelism. This paper discuss the MOE architecture and examines important aspects of architecture design, which is required to calculate ERIs according to the "Obara method". We conclude that n-way parallelization is the most cost-effective, hence we designed the MOE prototype system with a host computer and many processing nodes. The processing node includes a 76 bit oating-point MULTIPLY-and-ADD unit and internal memory, etc., and it performs ERI computations efficiently. We estimate that the prototype system with 100 processing nodes calculate the energy of proteins in a few days.

DOI： 10.1109/SC.1999.10000

記述言語：英語  

Merged DRAM/logic LSIs could provide high on-chip memory bandwidth by interconnecting logic portions and DRAM with wider on-chip buses. For merged DRAM/logic LSIs with the memory hierarchy including cache memory, we can exploit such high on-chip memory bandwidth by means of replacing a whole cache line (or cache block) at a time on cache misses. This approach tends to increase the cache-line size if we attempt to improve the attainable memory bandwidth. Larger cache lines, however, might worsen the system performance if programs running on the LSIs do not have enough spatial locality of references and cache misses frequently take place. This paper describes a novel cache architecture suitable for merged DRAM/logic LSIs, called variable line-size cache or VLS cache, for resolving the above-mentioned dilemma. The VLS cache can make good use of the high on-chip memory bandwidth by means of larger cache lines and, at the same time, alleviate the negative effects of larger cache-line size by partitioning each large cache line into multiple sub-lines and allowing every sub-line to work as an independent cache line. The number of sub-lines involved when a cache replacement occurs fan be determined depending on the characteristics of programs. This paper also evaluates the cost/performance improvements attainable by the VLS cache and compares it with those of conventional cache architectures. As a result, it is observed that a VLS cache reduces the average memory-access time by 16.4% while it increases the hardware cost by only 13%, compared to a conventional direct-mapped cache with fixed 32-byte lines.

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/ACCESS.2019.2936796

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/ACCESS.2020.3014163

開催年月日： 2021年6月

記述言語：英語   会議種別：口頭発表（一般）  

開催地：Fukuoka   国名：日本国  

開催年月日： 2021年6月

記述言語：英語   会議種別：口頭発表（一般）  

開催地：Fukuoka   国名：日本国  

開催年月日： 2021年6月

記述言語：英語   会議種別：口頭発表（一般）  

開催地：online   国名：日本国  

開催年月日： 2021年6月

記述言語：英語   会議種別：口頭発表（一般）  

開催地：online   国名：日本国  

開催年月日： 2020年1月

記述言語：英語   会議種別：口頭発表（一般）  

開催地：Fukuoka, Japan   国名：日本国  

開催年月日： 2020年1月

記述言語：英語   会議種別：口頭発表（一般）  

開催地：Fukuoka, Japan   国名：日本国  

開催年月日： 2019年12月

記述言語：英語   会議種別：口頭発表（一般）  

開催地：Hyderabad, India   国名：インド  

開催年月日： 2019年12月

記述言語：英語   会議種別：口頭発表（一般）  

開催地：Tianjin, China   国名：中華人民共和国  

開催年月日： 2019年2月

記述言語：英語  

開催地：San Francisco   国名：アメリカ合衆国  

開催年月日： 2018年12月

記述言語：英語  

国名：エジプト・アラブ共和国  

開催年月日： 2018年12月

記述言語：英語  

国名：日本国  

開催年月日： 2018年10月

記述言語：英語  

国名：日本国  

開催年月日： 2018年6月

記述言語：英語  

国名：日本国  

開催年月日： 2018年5月

記述言語：英語  

国名：日本国  

開催年月日： 2014年10月

記述言語：英語  

国名：大韓民国  

開催年月日： 2014年10月

記述言語：英語  

国名：大韓民国  

researchmap

開催年月日： 2011年10月

記述言語：英語  

開催地：Xi'an   国名：中華人民共和国  

Hardware accelerators integrating to general purpose processors are increasingly employed to achieve lower power consumption and higher processing speed, however, energy consumption of high performance accelerators has become a great issue on large scale parallel computer system. We have investigated the applicability of Single-Flux-Quantum (SFQ) circuits as a part of superconductivity technology in high-performance computing systems. Although it is possible to develop extraordinary low power processor by SFQ devices, conditional branch and loop back controls are difficult to be implemented by current SFQ technology. Therefore, we have proposed Reconfigurable Data- Path (RDP) accelerator which is avoiding those limitations of SFQ technology, while trying to get benefits of these circuits. In this research, we have implemented two-dimensional Heat (2D-Heat) and Finite Difference Time Domain (2D-FDTD) applications for investigating efficiency of using SFQ-RDP accelerator. According to performance evaluation results for above applications, execution times are 50.6 and 79.0 times smaller than those of the general purpose processor, and comparable with ones reported for GPU (Graphics Processing Units).Hardware accelerators integrating to general purpose processors are increasingly employed to achieve lower power consumption and higher processing speed, however, energy consumption of high performance accelerators has become a great issue on large scale parallel computer system. We have investigated the applicability of Single-Flux-Quantum (SFQ) circuits as a part of superconductivity technology in high-performance computing systems. Although it is possible to develop extraordinary low power processor by SFQ devices, conditional branch and loop back controls are difficult to be implemented by current SFQ technology. Therefore, we have proposed Reconfigurable Data-Path (RDP) accelerator which is avoiding those limitations of SFQ technology, while trying to get benefits of these circuits. In this research, we have implemented two-dimensional Heat (2D-Heat) and Finite Difference Time Domain (2D-FDTD) applications for investigating efficiency of using SFQ-RDP accelerator. According to performance evaluation results for above applications, execution times are 50.6 and 79.0 times smaller than those of the general purpose processor, and comparable with ones reported for GPU (Graphics Processing Units).

開催年月日： 2011年1月

記述言語：その他   会議種別：口頭発表（一般）  

開催地：筑波   国名：日本国  

開催年月日： 2011年1月

記述言語：その他   会議種別：口頭発表（一般）  

開催地：筑波   国名：日本国  

開催年月日： 2010年7月

記述言語：その他  

開催地：テネシー   国名：その他  

開催年月日： 2009年1月

記述言語：その他   会議種別：口頭発表（一般）  

開催地：yokohama   国名：日本国  

開催年月日： 2008年8月

記述言語：その他  

国名：日本国  

開催年月日： 2008年8月

記述言語：その他  

国名：フランス共和国  

開催年月日： 2008年8月

記述言語：その他  

国名：インド  

開催年月日： 2008年1月

記述言語：その他  

国名：大韓民国  

開催年月日： 2008年1月

記述言語：その他  

国名：台湾  

開催年月日： 2008年1月

記述言語：その他  

国名：大韓民国  

開催年月日： 2008年1月

記述言語：その他  

開催年月日： 2007年12月

記述言語：その他  

国名：アメリカ合衆国  

開催年月日： 2007年9月

記述言語：その他  

国名：ルーマニア  

開催年月日： 2007年9月

記述言語：その他  

国名：ギリシャ共和国  

開催年月日： 2007年9月

記述言語：その他  

国名：ギリシャ共和国  

開催年月日： 2007年9月

記述言語：その他  

国名：ギリシャ共和国  

開催年月日： 2007年6月

記述言語：その他  

国名：アメリカ合衆国  

開催年月日： 2007年5月

記述言語：その他   会議種別：口頭発表（一般）  

国名：日本国  

開催年月日： 2007年5月

記述言語：その他   会議種別：口頭発表（一般）  

国名：日本国  

開催年月日： 2007年4月

記述言語：その他   会議種別：口頭発表（一般）  

開催地：横浜   国名：日本国  

開催年月日： 2002年8月

記述言語：英語  

開催地：Monterey, CA   国名：アメリカ合衆国  

A new architectural technique to reduce energy dissipation of video memory is propose. Unlike existing approaches, the technique exploits the pixel correlation in video sequences, dynamically adjusting the memory bit-width to the number of bits changed per pixel. Instead of treating the data bits independently, we group the most significant bits together, activating the corresponding group of bit-lines adaptively to data variation. The method is not restricted to the specific bit-patterns nor depends on the storage phase. It works equally well on read and write accesses, as well as during precharging. Simulation results show that using this method we can reduce the total energy consumption of video memory by 20% without affecting the picture quality.

開催年月日： 2002年8月

記述言語：英語  

開催地：Monterey, CA   国名：アメリカ合衆国  

This paper proposes a history-based tag-comparison scheme for reducing energy consumption of direct-mapped instruction caches. The proposed cache efficiently exploits program-execution footprints recorded in the Branch Target Buffer (BTB), and attempts to detect and eliminate unnecessary tag checks at run time. Simulation results show that our approach can eliminate up to 95% of tag checks, saving the cache energy by 17%, while affecting the processor performance by only 0.2%.

開催年月日： 1999年8月

記述言語：英語  

開催地：San Diego, CA, USA   国名：その他  

This paper proposes a new approach using way prediction for achieving high performance and low energy consumption of set-associative caches. By accessing only a single cache way predicted, instead of accessing all the ways in a set, the energy consumption can be reduced. This paper shows that the way-predicting set-associative cache improves the ED (energy-delay) product by 60-70% compared to a conventional set-associative cache.

開催年月日： 1999年1月

記述言語：英語  

開催地：Orlando, FL, USA   国名：その他  

This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called `dynamically variable line-size cache (D-VLS cache)'. The D-VLS cache can optimize its line-size according to the characteristic of programs, and attempts to improve the performance by exploiting the high on-chip memory bandwidth. In our evaluation, it is observed that the performance improvement achieved by a direct-mapped D-VLS cache is about 27%, compared to a conventional direct-mapped cache with fixed 32-byte lines.

記述言語：その他  

開催地：the Convention and Exhibition Center (COEX)   国名：大韓民国  

記述言語：その他   会議種別：口頭発表（一般）  

開催地：Park Plaza Hotel   国名：アメリカ合衆国  

記述言語：その他   会議種別：口頭発表（一般）  

開催地：Tampere   国名：フィンランド共和国  

記述言語：その他   会議種別：口頭発表（一般）  

国名：フランス共和国  

記述言語：その他   会議種別：口頭発表（一般）  

国名：フランス共和国  

記述言語：その他   会議種別：口頭発表（一般）  

国名：フランス共和国  

記述言語：その他  

国名：日本国  

記述言語：その他  

国名：日本国  

記述言語：その他  

国名：日本国  

記述言語：その他   会議種別：口頭発表（一般）  

国名：グレートブリテン・北アイルランド連合王国(英国)  

記述言語：英語   会議種別：シンポジウム・ワークショップ パネル（公募）  

国名：アメリカ合衆国  

記述言語：その他  

国名：日本国  

記述言語：英語   会議種別：シンポジウム・ワークショップ パネル（公募）  

国名：トルコ共和国  

記述言語：その他   会議種別：シンポジウム・ワークショップ パネル（公募）  

国名：アメリカ合衆国  

記述言語：英語   会議種別：シンポジウム・ワークショップ パネル（公募）  

国名：アメリカ合衆国  

記述言語：英語   会議種別：シンポジウム・ワークショップ パネル（公募）  

国名：大韓民国  

記述言語：英語  

国名：日本国  

, , , , Hiroshi Sasaki, and Koji Inoue, "

記述言語：英語  

国名：日本国  

記述言語：英語   会議種別：シンポジウム・ワークショップ パネル（公募）  

国名：日本国  

記述言語：日本語  

国名：日本国  

Speculative Execution for Real-time Model Predictive Control on Manycore Processor

記述言語：英語  

国名：日本国  

記述言語：英語  

国名：日本国  

記述言語：日本語  

国名：日本国  

動画像上の指定した対象物体の位置座標を各フレームで推定するオンライン物体追跡は,自動車の安全技術の一つである障害物追跡や居眠り検知などに広く応用され,重要な技術となっている.最近ではバッテリ駆動を基本とする移動体における応用が拡大しており,追跡精度を向上するだけでなく,低消費エネルギー化も同時に達成することが求められる.そこで本稿では,物体追跡システムの低消費エネルギー化を目的とした動的フレームレート最適化方式を提案する.本方式では,物体追跡システム全体の消費エネルギーに基づいて最適なフレームレートに動的変更することにより,必要以上のフレーム取得や処理に要する消費エネルギーを削減する.消費エネルギーモデルを用いて本方式の実装・評価を行った結果,従来方式と同程度の追跡精度で消費エネルギーを70%以上削減できることが分かった.

記述言語：英語  

国名：オランダ王国  

記述言語：英語  

国名：日本国  

記述言語：英語   会議種別：口頭発表（一般）  

国名：日本国  

記述言語：日本語  

国名：日本国  

Dynamic Frame-rate Optimization for Low Energy Object Tracking

記述言語：日本語  

国名：日本国  

Dynamic Frame-rate Optimization for Low Energy Object Tracking

記述言語：日本語  

国名：日本国  

記述言語：日本語  

国名：日本国  

A Parallel Adder Circuit based on Optical Pass-gate Logic and Its Evaluation with Optoelectronic Circuit Simulator

記述言語：日本語  

国名：日本国  

Formulating Attack Condition on Received Signal Strength Indicator based Device Authentication

記述言語：英語   会議種別：口頭発表（一般）  

国名：大韓民国  

記述言語：日本語  

国名：日本国  

Shift-Register-Based Single-Flux-Quantum Cache Memory Architecture

記述言語：英語   会議種別：口頭発表（一般）  

国名：アメリカ合衆国  

記述言語：英語   会議種別：口頭発表（一般）  

国名：アメリカ合衆国  

記述言語：英語   会議種別：口頭発表（一般）  

国名：アメリカ合衆国  

記述言語：英語   会議種別：口頭発表（一般）  

国名：イタリア共和国  

記述言語：日本語  

国名：日本国  

Design of Component Circuits for Rapid Single-Flux-Quantum Gate-Level-Pipelined Microprocessors

記述言語：英語   会議種別：口頭発表（一般）  

国名：日本国  

記述言語：英語   会議種別：口頭発表（一般）  

国名：アメリカ合衆国  

J-GLOBAL

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J-GLOBAL

researchmap

記述言語：日本語  

記述言語：日本語  

記述言語：日本語  

画像認識技術が様々な分野で使われ，画像認識アプリケーションを高性能・低消費エネルギーで実行するプロセッサが要求されている．画像認識アプリケーションの実行時間の多くを占めるのはフィルタ処理である．そのため， GRAPE-DR のように演算器をアレイ上に並べるアーキテクチャが適している．しかしながら，処理ごとにフィルタの大きさが異なるため，従来のようにメモリとのデータ入出力を行う演算器が最上段と最下段に固定されている場合，一度に動作させることの可能な演算器が少なくなってしまう．そこで，本稿では，メモリとのデータ入出力に柔軟性を持たせた DSP (Data Stream Processing) Tile 型アクセラレータ・アーキテクチャを提案する．提案するアクセラレータは， DSPTile という小規模なフィルタ処理を実行可能な Tile を大量に集積しており，各 DSPTile がメモリと通信を行える．さらに，各 DSPTile は他の DSPTile へ演算結果を渡せるように接続されている．これらを利用して，小規模なフィルタ処理を複数並列に実行したり，大規模なフィルタ処理を実行したりすることが可能である．本稿では，面積オーバーヘッドを考慮しながら，詳細なアーキテクチャの決定を行う．Image recognition processing includes a number of filter operations which dominate the total execu tion time. Exploiting ALU array to accelerate the filter operations is one of the most promising approaches to achieve such energy-efficient executions. However, it is difficult for conventional ALU array accelerator to achieve high-performance and low-energy for multi-scale filter operations. To tackle this issule this paper proposes DSP (Data Stream Processing) tile accelerator for multi scale filter operations. Tile accelerator has many DSP tiles which can execute a small size of filter efficiently. Each DSP tile is connected with three-dimensionally implemented scratch-pad memories via TSVs.

記述言語：日本語  

本稿ではシングルコアプロセッサで実行されるマルチタスクにおいて，キャッシュウェイの割り当てとコード配置を同時に最適化する手法の提案を行う．同時には一つの割り当てられたキャッシュウェイのみを活性化し，残りのキャッシュウェイは活性化しないことでセットアソシアティブキャッシュへのアクセスエネルギーを削減可能である．また，主記憶上のプログラムコードの配置位置を変えることでキャッシュミス数を削減する．キャッシュミス数を削減することで主記憶へのアクセスエネルギーを削減可能であると同時に，全実行時間の短縮が可能である．商用プロセッサを用いた実験によって本手法を適用したプロセッサシステムの評価を行い，手法適用前の場合と比較して最大で 17％ の消費エネルギーの削減を確認した．The paper proposes a technique which simultaneously finds the optimal cache way allocation and code placement for given multiple tasks running on a single core processor. It reduces the energy consumption in a set-associative cache by activating only a single cache way at a time and deactivating the remaining cache ways. The technique also reduces the number of cache misses by changing the code placement in a main memory, which results in a reduction of the energy consumption in the main memory as well as the reduction of total execution time. Experiments using a commercial embedded processor demonstrate that the technique reduces the total energy consumption in the target processor system by 17% at the best case compared to the energy of the system which does not apply our technique.

記述言語：日本語  

本稿ではシングルコアプロセッサで実行されるマルチタスクにおいて,キャッシュウェイの割り当てとコード配置を同時に最適化する手法の提案を行う.同時には一つの割り当てられたキャッシュウェイのみを活性化し,残りのキャッシュウェイは活性化しないことでセットアソシアティブキャッシュへのアクセスエネルギーを削減可能である.また,主記憶上のプログラムコードの配置位置を変えることでキャッシュミス数を削減する.キャッシュミス数を削減することで主記憶へのアクセスエネルギーを削減可能であると同時に,全実行時間の短縮が可能である.商用プロセッサを用いた実験によって本手法を適用したプロセッサシステムの評価を行い,手法適用前の場合と比較して最大で17%の消費エネルギーの削減を確認した.

記述言語：日本語  

Improving execution code generation for on-chip memory lending on multicores

記述言語：日本語  

本稿では，3次元積層DRAMの利用を前提とし，大幅なチップ面積の増加を伴うことなく高いメモリ性能を達成可能な新しいキャッシュ・アーキテクチャを提案する．3次元実装されたDRAMを大容量キャッシュとして活用することで，オフチップメモリ参照回数の劇的な削減が期待できる．しかしながら，その反面，キャッシュの大容量化はアクセス時間の増加を招くため，場合によっては性能が低下する．この問題を解決するため，提案方式では，実行対象プログラムのワーキングセット・サイズに応じて3次元積層DRAMキャッシュを選択的に活用する．ベンチマーク・プログラムを用いた定量的評価を行った結果，提案方式の静的制御方式で平均35%，動的制御方式で平均43%の性能向上を達成した．In this paper, we propose a new architecture that can achieve high memory performance without large footprint overhead for DRAM-stacked processors. 3D stacked DRAM caches can dramatically reduce off chip memory accesses. However, this approach degrades performance in some cases because increasing cache size makes access time longer to solve this problems. Our approach selectively leverages the stacked DRAM cache based on the valiation of working set sizes. The results of our quantitative evaluation showed that the proposed approach achieves 35% of memory performance gain in static control method and 43% in dynamic control method.

記述言語：日本語  

現在我々は，チップマルチプロセッサの高性能化を目的とした演算/メモリ性能バランシング技術を提案している．本技術では，チップ内に搭載された複数コアを必要に応じて「演算用」もしくは「メモリ性能向上用」として使い分ける．本方式では，如何にして適切なコア配分を実現するかが極めて重要となる．そこで本稿では，性能モデリングに基づくコア分配法を提案する．また，本方式を Cell/BE、プロセッサに実装し，その有効性を評価する．ベンチマークプログラムを用いた定量的評価を行った結果，単純な並列処理に比べて最大で 14.5％の性能向上を達成できた．We have proposed the concept of Performance Balancing to improve the CMP performance. This approach attempts to exploit the on-chip cores not only for executing the parallelized threads, but also for improving the memory performance. In this technique, it is very important to decide an appropriate number of cores dedicated to memory performance improvements. In this paper, we propose an algorithm to solve this problem and implement it on a Cell/B.E. processor. In our evaluation, it is observed that our approach can achieve 14％ performance improvement in the best case compared to a conventional CMP model.

記述言語：日本語  

複数コアを1チップに搭載するチップマルチプロセッサ(CMP)が注目されている.CMPでは,チップ内並列処理により高い演算性能を達成することができる.共有型キャッシュを搭載するCMPの場合,各コアは最大でキャッシュの全容量を利用可能となる.しかしながら,その反面,複数アプリケーションを同時に実行した場合には,複数コアによるキャッシュアクセスが発生するため競合性ミスが増加する.その結果,あるコアにおけるプログラム実行性能が,他コアで実行されるプログラム特性よって大きな影響を受ける.したがって,CMP性能を最大限引き出すためには,共有型キャッシュの最適化が極めて重要となる.そこで本稿では,キャッシュ共有型CMPを対象とし,複数アプリケーションの同時実行によるメモリ負荷変動を定量的に解析した.解析の結果,あるプログラム実行において,他コアとの競合性ミスに起因するメモリ負荷の増加が「大きく発生する区間」と「さほど発生しない区間」が存在することが分かった.

記述言語：日本語  

複数コアを１チップに搭載するチップマルチプロセッサ(CMP)が注目されている．CMP では，チップ内並列処理により高い演算性能を達成することができる．共有型キャッシュを搭載する CMP の場合，各コアは最大でキャッシュの全容量を利用可能となる．しかしながら，その反面，複数アプリケーションを同時に実行した場合には，複数コアによるキャッシュアクセスが発生するため競合性ミスが増加する．その結果，あるコアにおけるプログラム実行性能が，他コアで実行されるプログラム特性よって大きな影響を受ける．したがって，CMP 性能を最大限引き出すためには，共有型キャッシュの最適化が極めて重要となる．そこで本稿では，キャッシュ共有型 CMP を対象とし，複数アプリケーションの同時実行によるメモリ負荷変動を定量的に解析した．解析の結果，あるプログラム実行において，他コアとの競合性ミスに起因するメモリ負荷の増加が「大きく発生する区間」と「さほど発生しない区間」が存在することが分かった．Integrating multiple processor cores into a single chip, or chip-multiprocessors (CMPs) is one of the most promising approaches to achieve high-performance and low-power consumption at the same time. In CMPs employing a sheared L2 cache, conflict misses may be increased, because all of the cores share the limited cache resource. To solve this problem, this paper quantitatively analyzes the memory workload on CMPs. By means of observing the transition of a CPI stack, we can discuss the detail of the memory behavior. In this analysis, it is observed that intra- and inter-programs, there are time period in which the conflicts frequently take place.

記述言語：日本語  

本稿では,トランザクショナルメモリにおける性能向上を目的とした並列実行トランザクション数動的制御法を提案する.一般に,並列プログラムにおいては共有変数へのアクセスに関して排他制御を行う必要がある.トランザクショナルメモリでは,複数スレツドに対して共有変数の同時アクセスを許すことで高性能化を実現する.しかしながら,複数スレッドによる共有変数へのアクセスにおいて不都合が発生した場合には,それまでの実行を中断し,トランザクション実行のやり直しを行う必要がある.その結果,期待した並列効果を得ることができないだけでなく,場合によっては性能が低下する.この問題を解決するため,本稿では実行やり直しの発生可能性を事前に検知し,必要に応じて並列に実行されるトランザクション数を抑制する方式を提案する.32コアを搭載したチップマルチプロセッサを前提とした評価を行った結果,最大で1.6倍程度の性能向上を達成することを確認した.

記述言語：日本語  

本稿では，トランザクショナルメモリにおける性能向上を目的とした並列実行トランザクション数動的制御法を提案する．一般に，並列プログラムにおいては共有変数へのアクセスに関して排他制御を行う必要がある．トランザクショナルメモリでは，複数スレッドに対して共有変数の同時アクセスを許すことで高性能化を実現する．しかしながら，複数スレッドによる共有変数へのアクセスにおいて不都合が発生した場合には，それまでの実行を中断し，トランザクション実行のやり直しを行う必要がある．その結果，期待した並列効果を得ることができないだけでなく，場合によっては性能が低下する．この問題を解決するため，本稿では実行やり直しの発生可能性を事前に検知し，必要に応じて並列に実行されるトランザクション数を抑制する方式を提案する．32 コアを搭載したチップマルチプロセッサを前提とした評価を行った結果，最大で 1.6 倍程度の性能向上を達成することを確認した．This paper proposes a technique to improve the performance of CMPs by mans of managing the number of transactions to be executed in parallel. In parallel computing, we need to manage sheared data in order to ensure the exclusiveness. In transactional memories, it is allowed the threads to access the shared data, resulting in higher performance. This is because we can aggressively exploit thread-level parallelisms. However, when a conflict takes place in the transactional memory, the associated thread execution needs to be aborted in order to guarantee the correct execution results. This abort operation degrades the CMP performance. To solve this issue, we propose an adaptive management mechanism to throttle or un-throttle the thread-level parallelism. In our evaluation, it is observed that in the best case we can achieve 1.6x speedup.

記述言語：日本語  

現在我々は,チップマルチプロセッサの高性能化を目的とした演算/メモリ性能バランシング技術を提案している.本技術では,チップ内に搭載された複数コアを必要に応じて「演算用」もしくは「メモリ性能向上用」として使い分ける.本方式では,如何にして適切なコア配分を実現するかが極めて重要となる.そこで本稿では,性能モデリングに基づくコア分配法を提案する.また,本方式をCell/B.E.プロセッサに実装し,その有効性を評価する.ベンチマークプログラムを用いた定量的評価を行った結果,単純な並列処理に比べて最大で14.5%の性能向上を達成できた.

記述言語：日本語  

複数のプロセッサコアを1チップに搭載するチップマルチプロセッサ(CMP)が現在注目されている.チップ内スレッドレベル並列処理により高い演算性能を得ることができるためである.しかしながら,メモリバンド幅の制約や複数コア搭載によるメモリアクセス頻度の増加により,メモリウォール問題が深刻化する.その結果,多くのメモリ参照を必要とする並列プログラムの実行においては実効性能が低下するといった問題が生じる.そこで本稿では,CMPの性能向上を目的として,演算性能とメモリ性能のバランスを考慮したヘルパースレッド実行方式を提案する.従来の方式では,スレッドレベル並列性を高めるため,搭載された全てのプロセッサコアを利用して並列プログラムを実行する.これに対し,提案方式では,一部のプロセッサコアをプリフェッチを行うヘルパースレッドに割当てる.ヘルパースレッドの最適な数が既知であると仮定して提案方式の性能を評価した結果,従来方式と比較して,最大で47%の性能向上を得ることができた.

記述言語：日本語  

複数のプロセッサコアを１チップに搭載するチップマルチプロセッサ(CMP)が現在注目されている．チップ内スレッドレベル並列処理により高い演算性能を得ることができるためである．しかしながら，メモリバンド幅の制約や複数コア搭載によるメモリアクセス頻度の増加により，メモリウォール問題が深刻化する．その結果，多くのメモリ参照を必要とする並列プログラムの実行においては実効性能が低下するといった問題が生じる．そこで本稿では，CMP の性能向上を目的として，演算性能とメモリ性能のバランスを考慮したヘルパースレッド実行方式を提案する．従来の方式では，スレッドレベル並列性を高めるため，搭載された全てのプロセッサコアを利用して並列プログラムを実行する．これに対し，提案方式では，一部のプロセッサコアをプリフェッチを行うヘルパースレッドに割当てる．へルパースレッドの最適な数が既知であると仮定して提案方式の性能を評価した結果，従来方式と比較して，最大で 47％の性能向上を得ることができた．Conventional CMPs attempt to exploit the thread-level parallelism (TLP) by using all of the cores integrated in a chip. However, this kind of straightforward way does not always achieve the best performance. This is because the memory-wall problem becomes more critical in CMPs, resulting in poor performance in spite of high TLP. To solve this issue, we propose an efficient thread management technique, called performance balancing. We dare to throttle the TLP to execute software prefetchers as helper-threads. Our experimental results show 47％ speed up in the best case compared with a conventional parallel execution.

記述言語：日本語  

本稿では，通信性能の悪化の主要因である通信の衝突を避けるためのタスク配置最適化の評価を行った．著者らはメッセージのタイミングを制御しつつ，衝突を回避するタスク配置最適化の研究をしている．その中でその最適化をツリートポロジに適用して，その手法が有効であることを示した．一方，メッシュやトーラスなどのネットワークトポロジにはホップ数を評価関数とする通信衝突削減のためのタスク配置最適化が研究なされており，有効性があるとされている．そこで，ネットワークトポロジが3Dメッシュの際に通信衝突回数を評価関数としたタスク配置最適化を適用した場合とホップ数を評価関数したタスク配置最適化を適用した場合にどのような違いがあるか調べる実験をし，考察を行った．In this text, we evaluated the optimization of task allocation to avoid contentions that was the key factor of the communication performance degradation. We applied the optimization of task allocation controlling the timing of the message for avoiding contentions to the tree topology, and showed it was effectiveness. On the other hand, there were some optimizations of task allocation for reducing contentions. Those optimizations used the evaluation function which used the number of hops. Those optimizations against the mesh and torus topology were effective. We experimented and investigated what's the difference between the optimization of task allocation which the evaluation function was the number of contentions and the number of hops when the network topology was 3D mesh. We considered about it.

記述言語：日本語  

近年，コンピュータの頭脳であるマイクロプロセッサの信頼性低下が極めて深刻な問題として注目されている．微細加工技術の進歩に伴い劇的な性能向上を達成してきた反面，耐故障性の低下により外部/内部雑音などの影響を受け易くなった．その結果，システムには不具合がなくとも，コンピュータが正しくプログラムを実行できないという極めて深刻な事態となる．このような背景に基づき，近年，マイクロプロセッサの信頼性向上を目的とした様々なアーキテクチャ技術が提案された．本稿では，信頼性向上戦略を整理すると共に，商用マイクロプロセッサの動向も踏まえてアーキテクチャ・レベルでの信頼性向上技術を解説する．

記述言語：英語  

Multitude parameters involved in the design process of a reconfigurable accelerator which is exploited in embedded systems brings about a remarkable complexity and large design space. One effective technique is design space exploration which is capable to find a right balance between the different design parameters. Quantitative design approach is an alternative which uses the data collected from applications; however it is time consuming and highly depends on designer observations and analyses and might not conclude to an optimal design. In this paper a hybrid approach is introduced which uses an analytical approach to explore the design space for a reconfigurable accelerator and determine a wise design point based on the quantitative data collected from the targeted applications. It also provides flexibility for applying new design constraints as well as new applications characteristics. Furthermore this approach is a methodological approach which reduces the design time and results in a design which satisfies the design goals. Experimental results show the efficacy of the hybrid approach.Multitude parameters involved in the design process of a reconfigurable accelerator which is exploited in embedded systems brings about a remarkable complexity and large design space. One effective technique is design space exploration which is capable to find a right balance between the different design parameters. Quantitative design approach is an alternative which uses the data collected from applications; however it is time consuming and highly depends on designer observations and analyses and might not conclude to an optimal design. In this paper, a hybrid approach is introduced which uses an analytical approach to explore the design space for a reconfigurable accelerator and determine a wise design point based on the quantitative data collected from the targeted applications. It also provides flexibility for applying new design constraints as well as new applications characteristics. Furthermore, this approach is a methodological approach which reduces the design time and results in a design which satisfies the design goals. Experimental results show the efficacy of the hybrid approach.

記述言語：日本語  

チップマルチプロセッサでは並列処理によって性能向上を実現可能である．しかしながら，プロセッサコアの処理速度に比べ主記憶へのアクセス速度は非常に遅い．また，コア間での資源共有が必要であり，主記憶アクセスがプロセッサ性能抑制の主要因となっている．したがって，プロセッサシステム全体の性能向上のためには，各コアにおける演算の並化効率とメモリ性能の両方を向上させる必要がある．そこで本稿では，メモリ貸与法に基づくSPM型CMP向けコア協調実行方式を提案する．演算，メモリ性能の向上のため，それぞれにバランスよくコア資源を分配することでトータルでの性能向上を目指す．姫野ベンチマークをCellプロセッサに実装して評価した結果，単純な並列処理に比べて最大で13％の性能向上を確認した．This paper proposes performance balancing, that is core management technique focused on trade-off between calculation and memory performance．In CMPs, high-performance is achieved by exploiting TLP. However, resource sharing among the cores makes memory performance lower regardless of the already low performance compared with processor core's one. Thus, we have to consider not only scalability, but also the performance assumed ideal memory sub-systems. Our proposed technique attempts to select effective approach, exploit scalability or improve memory performance. We also focus on a software-controllable on-chip memory. By borrowing local memory of some cores to others, we achieve memory performance improvement,and try to improve processor performance.Our experimental results show 13% speed up in the best case, compared with conventional parallel processing on Cell Broadband Engine.

記述言語：日本語  

本稿では、アーキテクチャ・レベルでの安全性向上を目的としたセキュア・プロセッサに関する研究事例を紹介する。近年、コンピュータ・ウィルスや情報漏洩が極めて深刻な社会問題となっている。これまでに、ネットワーク・レベルやシステム・ソフトウェア・レベルにて多くの安全性向上技術が開発されており実用化も進んでいる。しかしながら、依然としてコンピュータ・システムに対する脅威は増加の一途を辿っている。1970 年代初頭にマイクロプロセッサが開発されて以来、トランジスタ集積度の向上に伴い順調な性能向上を達成してきた。また、携帯機器の普及に伴い、低消費電力化や低消費エネルギー化も進んでいる。しかしながら、安全性向上に関する議論は少なく、2000 年以降になって本格的にアーキテクチャ・レベルで安全性を考慮する必要性が認識されるようになった。今後、高性能化や低消費電力化と同様に、安全性向上技術は極めて重要な設計制約となる。This paper introduces architectural supports to improve the efficiency of computer security. In the social information infrastructures, we exactly face to "Security Problem" such as computer viruses and information leaks. Although a number of techniques to improve security efficiency, which focus on network and system software components, have so far been proposed, still many threats exist. Since 1970s, microprocessors have made incredible progress in terms of performance. In addition, from 1990s, many techniques to reduce power or energy consumption have been developed. However, a few discussions for computer security at the processor level have done. Now, it is the time to start considering, how we can improve the security efficiency by means of providing architectural supports.

記述言語：日本語  

大規模並列システムの設計開発ならびに性能解析に向けた相互結合網シミュレータPSI-NSIMについて述べる.PSI-NSIMは,評価対象とする相互結合網の仕様を記述した仕様ファイルとアプリケーション実行から生成した通信プロファイルを基にシミュレーションを行う.所望する相互結合網の評価に必要な各種情報を出力するのみならず,システム全体の性能を高速かつ精度良く予測するとともに,アプリケーションの性能解析や可視化のための各種情報も出力する.本稿では、シミュレータの実装、および既存のクラスタシステムの性能評価について報告する.

記述言語：日本語  

本稿では、通信性能の悪化の主要因である通信の衝突を避けるためのランク配置最適化技術の提案を行う。通信のタイミングを考慮することで、通信の衝突を回避する高精度な MPI ランク配置を行う目的関数の提案を行った。また、本稿提案の目的関数を適用することによる通信時間の削減効果を調べる評価実験を行った。対象プログラムとして recursive doubling の通信パターンや CG 法、umt2000 といったアプリケーションの通信パターンを用いた。評価実験では、通信時間が順配置に対して最大 45％、従来研究によるランク配置に対して最大 24％、通信時間が削減され、提案手法が有効であることが分かった。In this paper, this work proposes the optimization of rank allocation technology of avoiding the communication contention that is the key factor of the communication performance degradation. This work proposes the objective function for high-quality Optimization of MPI rank allocation to be able to avoid a communication contention by considering the communication-timing of each message. Moreover, in the evaluation experiment, this work checks how this objective function cuts down communication time. The communication pattern of the recursive doubling algorithm and the communication pattern of the application such as CG and umt2000 are used in the evaluation experiment. The ratio of reduction in the communication time are 45％ or less for order rank allocation, 24％ or less for previous work rank allocation in the experiment.

記述言語：日本語  

ペタフロップス級時代の次世代スーパーコンピュータの設計開発に向けた統合型システム性能評価環境 PSI-SIM について述べる。本環境は、実践的な並列アプリケーションから生成した通信プロファイルを基に、所望するインターコネクトやシステム全体の性能を高速かつ精度良く予測するとともに、アプリケーションの性能解析や可視化を支援する。本稿では、通信プロファイルを高速に生成するためのプログラムコード抽象化手法を提案する。また、PSI-SIM によるアプリケーションや既存のクラスタシステムの性能評価を行い、シミュレーション時間や見積もり誤差について議論する。This paper presents a system performance evaluation environment, PSI-SIM, toward peta-scale next generation supercomputer development. This environment estimates performances of desired interconnect and system based on communication profile which generated from execution of practical parallel application, and supports easy application analysis and visualization. We propose a program code abstraction method for fast communication profile generation. Furthermore, PSI-SIM simulates applications and an existing cluster system, then the elapsed simulation times and the error rates of the estimation are discussed.

記述言語：日本語  

本研究では、負荷バランスの不均衡によって生じるプロセス毎の到着遅れがブロードキャスト通信の性能を低下させる問題に着目し、それを解決する手段として、負荷状況に応じて通信順序を調整する動的最適化手法を提案した。この手法では、まずプロセスの負荷情報としてルートプロセスからの到着時刻の遅れ時間を算出し、それに応じてブロードキャスト通信アルゴリズム内の仮想ランクへのプロセス割り当てを変更する。本稿では、提案手法のプロトタイプを PC クラスタ環境に実装し、負荷の状況によって最大で 40％程度、ブロードキャスト通信の性能を向上できることを確認した。さらに、提案手法のブロードキャストを疎行列計算に適用することにより、通信時間を最大 25％程度削減できることを確認した。This work focuses on the problem that the load imbalance can decrease the performance of broadcast communication. To avoid the problem, the authors proposed a technique of optimization that adjusts the order of communications in a broadcast at runtime. In this technique, the information of the delay of each rank from the root rank is used to decide the optimal order. In This paper, a proto-type of this technique was implemented on a PC cluster, and showed that the optimization decreased the by 40％ at maximum. In addition to that, it was confirmed to be able to reduce the communication time by about 25％ or less by applying the broadcast of the proposal technique to the sparse matrix calculation.

記述言語：日本語  

本稿では、高速かつ正確なキャッシュシミュレーション法について述べ、先行研究と定量的な比較を行い有効性を評価する。一般に、キャッシュメモリのシミュレーションにはトレース・ドリブン方式が用いられる。設計空間の拡大に伴い評価対象が増加しており、評価時間が長くなる傾向にある。トレース・サイズの削減によりシミュレーション時間を短縮できるが、精度が低下するという問題が生じる。そこで、本手法はメモリ・アクセスの特徴を利用し、精度を維持しつつ時間の短縮を実現する。先行研究と比較した結果、トレース・サイズは平均 81.7％削減され、キャッシュ・ミス率の予測精度は平均 34.6％向上した。This paper proposes a fast, accurate cache simulation technique for efficient design space exploration, and shows its efficiency by means of comparing with a related approach. Trace-driven simulation is a well known methodology to measure memory-system performance, e.g. cache hit rates. One of advantages of this method is the high-speed of simulations. Since the trend increases the complexity of microprocessor chips, e.g. CMPs, however, it is strongly required to achieve much faster simulations without sacrificing the accuracy of performance prediction. The proposed approach first attempts to characterize the memory-access patters, and then generates a small but well-constructed memory-access trace as a stimulus of cache simulators. In our evaluation, it is observed that the proposed technique reduces the trace size by 81.7％ while the accuracy of cache miss rates is improved by 34.6％, compared with SimPoint approach.

記述言語：日本語  

Large Scale Reconfigurable Data Path (LSRDP) は、二次元アレイ状に配極した多数の演算器を搭載し、演算器の種類と演算器間のネットワークを再構成可能とするデータパスをもつプロセッサアクセラレータである。LSRDP において、演算器数と演算器間のネットワーク構成の間には面積に関してトレードオフの関係が存在する。本稿では LSRDP に量子化学計算の二電子積分の初期積分部分を実装し、クロスバースイッチにて演算器行間ネットワークを実装する場合の検討を行った。その結果、各演算器を他の９個の演算器と接続した場合、LSRDP 全体の面積が最小となることが明らかになった。Large Scale Reconfigurable Data Path (LSRDP) is a data path type processor accelarator. On the LSRDP, enormous Floating Point number processing Units (FPUs) are arranged as 2-dimensional array, and each FPU and FPU network is reconfigurable. There is a trade-off relation about the area size between the number of FPUs and network configuration for the LSRDP. In this research, the LSRDP area size is estimated under condition that the initial integral part of the quantum chemistry two electron integral calculation is implemented and the crossbar switch is assumed to implement the network connecting each FPU array. As a result, it was obtained that each FPU in an array is connected with the nine FPUs in next array for the minimized LSRDP area size.

記述言語：日本語  

本稿では,高速かつ正確なキャッシュシミュレーション法について述べ,先行研究と定量的な比較を行い有効性を評価する.一般に,キャッシュメモリのシミュレーションにはトレース・ドリブン方式が用いられる.設計空間の拡大に伴い評価対象が増加しており,評価時間が長くなる傾向にある.トレース・サイズの削減によりシミュレーション時間を短縮できるが,精度が低下するという問題が生じる.そこで,本手法はメモリ・アクセスの特徴を利用し,精度を維持しつつ時間の短縮を実現する.先行研究と比較した結果,トレース・サイズは平均81.7%削減され,キャッシュ・ミス率の予測精度は平均34.6%向上した.

記述言語：英語  

Active power used to be the primary contributor to total power dissipation of CMOS designs but with the technology scaling the share of leakage in total power consumption of digital systems continues to grow. Moreover temperature is another factor that exponentially increases the leakage current. In this paper we show the effects of temperature and technology nodes on the optimal (minimum-energy-consuming) cache configuration for low energy embedded systems. We show that a temperature-aware configurable cache is an effective way to save energy in finer technologies when the embedded system may be used in different temperatures. Our results show that using a temperature-aware configurable cache up to 66％ energy can be saved with only 1％ performance penalty for instruction cache and 74％ energy saving with 4.7％ performance loss for data cache.Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of digital systems continues to grow. Moreover, temperature is another factor that exponentially increases the leakage current. In this paper, we show the effects of temperature and technology nodes on the optimal (minimum-energy-consuming) cache configuration for low energy embedded systems. We show that a temperature-aware configurable cache is an effective way to save energy in finer technologies when the embedded system may be used in different temperatures. Our results show that using a temperature-aware configurable cache, up to 66％ energy can be saved with only 1％ performance penalty for instruction cache and 74％ energy saving with 4.7％ performance loss for data cache.

記述言語：日本語  

複数コアを１チップに搭載するチップマルチプロセッサ(CMP)が注目されている。CMP は、複数コアで並列処理することで高い演算性能を達成することができる。しかしながら、メモリバンド幅の制約や複数コア搭載によるメモリアクセス頻度の上昇により、メモリウォール問題が深刻化する。主記憶のアクセス時間を隠蔽する方法のひとつにデータ・プリフェッチがある。CMP においてデータ・プリフェッチを行う場合、コア間の相互作用があるため、シングルコアプロセッサとは異なる効果が現れる。そこで本稿では、CMP におけるデータ・プリフェッチが性能へ与える影響を分析した。その結果、プリフェッチしたデータが無効化される割合は極めて小さく、プリフェッチを発行したコア以外のメモリアクセス時間を隠蔽するプリフェッチが約５％あることが明らかになった。Chip Multiprocessors (or CMPs) can achieve higher performance by means of exploiting thread level parallelism. Increasing the number of processor cores in a chip dramatically improves the peak performance. However, since the memory bandwidth does not scale with the number of cores, the negative impact of the memory-wall problem becomes more critical. Data prefetching is a well known approach to compensating for the poor memory performance, and has been employed in commercial processor chips. Although a number of prefetching techniques have so far been proposed, in many cases, they have assumed that the processor core in a chip is only one. In CMP chips, there are some shared resources such as L2 caches, buses, and so on. Therefore, the effect of prefetching on CMPs should be different from that on single-core processors. In this paper, we analyze the effect of prefetching on CMP performance. This paper first classifies the impact of prefetch operations issued during a program execution. Then, we discuss qualitatively and quantitatively the effect of prefetching to the memory performance. The experimental results show that the negative effect of invalidation of prefetched data is very small. In addition, it is observed that about 5％ of prefetch operations improve the cache hit rates of other cores.

記述言語：日本語  

複数コアを1チップに搭載するチップマルチプロセッサ(CMP)が注目されている.CMPは,複数コアで並列処理することで高い演算性能を達成することができる.しかしながら,メモリバンド幅の制約や複数コア搭載によるメモリアクセス頻度の上昇により,メモリウォール問題が深刻化する.主記憶のアクセス時間を隠蔽する方法のひとつにデータ・プリフェッチがある.CMPにおいてデータ・プリフェッチを行う場合,コア間の相互作用があるため,シングルコアプロセッサとは異なる効果が現れる.そこで本稿では,CMPにおけるデータ・プリフェッチが性能へ与える影響を分析した.その結果,プリフェッチしたデータが無効化される割合は極めて小さく,プリフェッチを発行したコア以外のメモリアクセス時間を隠蔽するプリフェッチが約5%あることが明らかになった.

記述言語：日本語  

特定用途向けプロセッサとは,アプリケーションに特化した命令を実行することによって,汎用プロセッサに対して高性能を実現するものである.本稿では,特定用途向けプロセッサの実現方式として,データパスに動的再構成可能ハードウェアを用いたプロセッサVulcan2とそのソフトウェア開発環境ISAccを提案する.また,実際にISAccを用いてアプリケーションをVulcan2シミュレータ上に実装した結果を解析し,Vulcan2及びISAccの評価を行った.

記述言語：日本語  

Large Scale Reconfigurable Data Path(LSRDP)は,二次元アレイ状に配置した多数の演算器を搭載し,演算器の種類と演算器間のネットワークを再構成可能とするデータパスをもつプロセッサアクセラレータである.LSRDPにおいて,演算器数と演算器間のネットワーク構成の間には面積に関してトレードオフの関係が存在する.本稿ではLSRDPに量子化学計算の二電子積分の初期積分部分を実装し,クロスバースイッチにて演算器行間ネットワークを実装する場合の検討を行った.その結果,各演算器を他の9個の演算器と接合した場合,LSRDP全体の面積が最小となることが明らかになった.

記述言語：日本語  

本稿では，通信性能の悪化の主要因である通信の衝突を避けるためのランク配置最適化技術の提案を行う．メッセージごとに通信のタイミングを考慮することで，衝突を回避する高精度なMPIランク配置最適化の提案を行った．また，本手法では衝突を制御するためIn this paper, it proposes the rank optimization of rank allocation technology of avoiding the communication contention that is the key factor of the deterioration of the communication performance. It proposes the method is possible to ward off a communication contention was allcated by considering the communication-timing of each message. Moreover, this method has a overhead that it has to add synchronous function.In the evaluation experiment, it check how does this method cut down communication time including that overhead. The communication pattern of the recursive doubling and the communication pattern of the real application such as CG and umt2000 are used in this evalucation experiments. The ratio of reduction in the communication time are 45％ or less for order rank allocation , 24％ or less for previous work rank allcation in the experiment.

記述言語：日本語  

デスクサイドに設置可能な10テラフロップス級の超伝導コンピュータとして,単一磁束量子回路による再構成可能な大規模データパスをもつプロセッサを提案する.

記述言語：日本語  

組込み機器において、特にバッテリ駆動型のシステムでは消費エネルギーの削減が重要となる。近年、汎用プロセッサだけでなく組込み向けプロセッサにもキャッシュメモリが搭載されるようになってきている。また、回路の微細化によりキャッシュメモリにおけるリークエネルギーは年々増加しており、リークエネルギーの削減が求められている。キャッシュのリークエネルギー削減手法のひとつに、Drowdyキャッシュがある。この手法では、キャッシュラインのモードを低リークモードに切り替えることで、リークによる消費エネルギーを削減する。しかし、低リークモードのキャッシュラインへアクセスが発生した場合、ラインを通常モードに切り替える必要があり、この切替には１～数サイクルの切替ペナルティとエネルギーオーバーヘッドが発生する。本論文では、これらの性能低下を最小限に抑えつつ、リークエネルギーを小さくするアルゴリズムとして時間的局所性を応用しモード切替にウェイ予測を用いたウェイ予測Drowsyキャッシュを提案する。提案手法に対し、性能とリークエネルギーの削減に関しての評価を行う。In the design of embedded systems, especially battery-powered systems, it is important to reduce energy consumption. In these days, cache memories are used not only in general-purpose processors but also in processors for embedded systems. Static energy (leakage energy) consumed in cache has been increasing with the decrease of the feature size. The Drowsy cache is one of the techniques to reduce leakage energy consumption of caches. The Drowsy cache reduces leakage energy by changing cache line mode into the low-leakage mode. In the Drowsy cache, when the cache line in the low-leakage mode is accessed, it has to be changed into the normal mode, and it takes one or more clock sysles. Thus, these penalty cycles may significantly degrade the cache performance. In this paper, we propose three kinds of Way-Prediction Drowsy Cache which achieve a high-energy reduction with the minimum performance overhead. Experimental results demonstrate the effectiveness of the proposed cache architectures.

記述言語：日本語  

本稿では，高い精度を維持しつつ，短時間でのシミュレーションを可能とするメモリ・アーキテクチャ・ベンチマーキング手法を提案する．一般に，メモリ．アーキテクチャの評価では，アドレス・トレースに基づいたシミュレーションを行う.アプリケーション・プログラムの高機能化によりアドレス・トレースサイズが増加していることからシミュレーション時間が長くなる傾向にあり，シミュレーション時間の短縮が不可欠である．アドレス・トレースサイズを削減することでシミュレーション時間を短縮できるが，精度が低下するという問題がある．そこで本手法は，まず，トレースを小規模なトレースに分割し，それぞれの類似性に基づき代表となるトレースを選択する．これによりシミュレーションするトレースが小さくなり，時間を短縮できる．キャッシュ性能測定に基づく評価実験の結果，本手法はシミュレーション時間を平均77.6％短縮し，そのときのキャッシュヒット率の予測誤差は平均4.2％であった．In order to determine the memory architecture from a lot of design candidates, we use a trace-driven simulation. It is a common approach for evaluating memory architecture. However, it also demands much time. In this paper, we propose a Memory Architecture Benchmarking technique. It is possible that to reduce the simulation time while maintaining simulation accuracy. In order to evaluate validity of proposed technique, we measured the cache hit ratio. In our evaluation, the proposed technique reduces the simulation time about 77.6% and cache hit ratio prediction errors about 4.2% in the average.

記述言語：日本語  

本稿では高速なウイルス検索実現のため,近似文字列照合のアルゴリズムの1つであるBP法(Bit Parallel Algorithm)の高速プログラム実行に関して検討する.現在ウイルス検索は,不正プログラムの特徴を定義したファイルを用意し,診断対象ファイルとの完全一致を基本としている.そのため既存ウイルスを改変した亜種ウイルスを発見することができない.この問題の解決策として近似文字列照合の応用が考えられる.そこで,高速かつ高機能なウイルス検索の実現を目指し,近似文字列照合プログラム実行の特徴解析を行った.まず,プログラム実行時に必要となるメモリ容量と実行命令の出現頻度を解析した.その結果,メモリ性能に関しては現在のプロセッサに搭載されたL1キャッシュメモリの容量で十分であることが分かった.また命令の実行頻度解析において,データ依存関係のある命令列の実行頻度に偏りがあることを見いだした.さらに,データの依存関係のある命令列に対しRFU(Reconfigurable Function Unit)を利用することで,およそ14%の性能向上を期待できることが分かった.

記述言語：日本語  

本稿では,メモリ整合性検証を前提としたプロセッサ性能オーバヘッドの隠蔽技術を提案する.メモリ整合性検証では,保護対象メモリ空間の状態を安全な記憶領域に保持することで,ロードデータに対する改ざんを検出する.しかしながら,オンチップ・キャッシュやメモリバンド幅を浪費するため,プロセッサ性能に大きな悪影響を与える.この原因の1つは,プログラム実行にプロセッサが必要とするデータとメモリ整合性検証用データがキャッシュ領域で競合を引き起こすことにある.つまり,キャッシュミスに伴うメモリアクセスが発生し,その結果,プロセッサ性能が低下する.これを解決するために,衰退ラインと呼ばれるアクセス頻度の低いキャッシュ・ラインにメモリ整合性検証用データを配置する.これにより,プログラム実行に必要となるデータがキャッシュから追い出されることを防ぐ.ベンチマーク・プログラムを用いた定量定期評価を行った結果,従来の手法と比較して,平均23.8%の性能オーバヘッド削減を達成した.

記述言語：日本語  

近年，より高い性能の実現を目的として１つのチップ上に複数のプロセッサコアを搭載したＣＭＰ (Chip MultiProcessor) アーキテクチャが注目されている．メモリバンド幅の制約，メモリウォール問題のさらなる深刻化を背景として，今後プロセッサシステムの高性能化を実現するには，ＣＭＰに適したメモリシステムを構築することは不可欠となる.メモリシステムの中でもオンチップ・キャッシュの構成は性能に与える影響が大きく，その主な設計選択肢としてプロセッサコア間での共有/非共有がある．本稿では，ＣＭＰにおけるキャッシュの共有と非共有によるメモリ性能への影響を解析し，Ｌ２キャッシミス率の差によりメモリ性能の優劣が異なる事を明らかにした．To achieve higher performance, ＣＭＰ (Chip MultiProcessor) is focused today. Because of narrow bus bandwidth and the memory wall problem, it is necessary to design the memory system which is suitable for CMP. In the system, on-chip cache architecture has a large impact on performance, and to decide sharing/dedicating an on-chip cache among multiple processor cores is a important choice. In this paper, we studied the difference of performance in shared-cacheCMP and dedicate-cacheCMP. We analyzed the factor which impacts memory-access-time qualitatively and quantitatively, and revealed that L2cache miss rate makes the largest gap between them.

記述言語：日本語  

プロセッサにおけるソフトエラー耐性の低下が問題になっている.ソフトエラーとは,雑音が原因で回路が一時的に誤動作する現象である.信頼性を向上させるため,メモリではパリティやECC等の誤り検出/訂正コードが用いられる.しかしながら,組合せ回路にこのような誤り検出/訂正コードを加えることは難しく,多くの場合はプログラム実行を多重化(複数回実行)することでエラー検出を可能にしている.本研究では,演算結果の再利用に基づく高信頼かつ低消費エネルギーなプロセッサアーキテクチャを検討する.本手法ではプログラム中の同一命令の演算結果を演算結果再利用テーブルに保持しておき,それを再利用する.演算結果再利用テーブルはECCで保護するため,各命令の実行を多重化することなく高い信頼性を実現できる.これにより,信頼性の向上に伴う消費エネルギー・オーバーヘッドを削減する.定量的評価を行った結果,従来の多重化に基づく方式では,多重度2のとき100%であった消費エネルギー・オーバーヘッドを6.3%に削減することができた.

記述言語：日本語  

近年多くの高性能プロセッサは分岐予測器を搭載している．分岐予測ミスが発生した場合には誤った命令列が実行されるため，分岐予測精度がプロセッサの性能および消費エネルギーに与える影響は大きい．より高精度な分岐予測の実現を目的として，大規模かつ複雑な分岐予測器も提案されている．しかしながら，その結果分岐予測における消費エネルギーが増大し，プロセッサの全消費エネルギーに悪影響を及ぼすようになってきた．前述したように，分岐予測ミス時には将来無効化される命令が実行されるため，プロセッサの消費エネルギーを増加させる．したがって，高い分岐精度を維持しつつ分岐予測器の低消費エネルギー化を達成することが極めて重要となる．そこで本研究では，分岐予測精度の向上と消費エネルギーの低減を目的とし，実行経路の偏りに着目した新しい分岐予測法を提案する．プログラム中には実行頻度の高い命令列（ホットパス）が存在し，ホットパス中の分岐命令は高確率で決まった方向に分岐する．また，少数のホットパス実行時間が全実行時間の大部分を占める．提案する分岐予測法では，ホットパス中の分岐命令と分岐先を小容量のメモリに保持し，ホットパス実行中はそのメモリを参照することで分岐予測を行う．従来のGshare分岐予測器と比較した結果，提案手法の採用により分岐予測ミス率は約２２ポイント増加したが，分岐予測器の消費エネルギーを約４０％削減することができた．Modern high performance processors employ branch predictors. The accuracy of branch prediction in fluences the processor performance because the processor executes wrong instructions when a mis-prediction occurs. To improve accuracy of branch prediction, large scale and complex branch predictors have been proposed. How-ever,the energy of branch predictors has been increasing. As mentioned above, when a mis-prediction occurs, total chip energy is increased due to the execution of invalid instructions. Therefore, achieving high accuracy of branch prediction and reducing the energy consumption of the branch predictor are very important. We propose a new method to solve the issues. It is well known that there is a small number of instruction paths executed frequently in program executions. In the hotpath, branch instructions tend to be output the same execution results, i.e. the same branch direction and the same target address. Moreover, the execution time of some hotpaths have a majority of the total execution time. A method of branch prediction we propose predicts by accessing to small memory that have branch instruction address and branch target address for hotpaths. We compare this method with Gshare predictor, As a result, it is observed that although the mis-prediction rate increases by 2.2 points, we can reduce the energy consumption by 40%.

記述言語：日本語  

近年多くの高性能プロセッサは分岐予測器を搭載している.分岐予測ミスが発生した場合には誤った命令列が実行されるため,分岐予測精度がプロセッサの性能および消費エネルギーに与える影響は大きい.より高精度な分岐予測の実現を目的として,大規模かつ複雑な分岐予測器も提案されている.しかしながら,その結果分岐予測における消費エネルギーが増大し,プロセッサの全消費エネルギーに悪影響を及ぼすようになってきた.前述したように,分岐予測ミス時には将来無効化される命令が実行されるため,プロセッサの消費エネルギーを増加させる.したがって,高い分岐精度を維持しつつ分岐予測器の低消費エネルギー化を達成することが極めて重要となる.そこで本研究では,分岐予測精度の向上と消費エネルギーの低減を目的とし,実行経路の偏りに着目した新しい分岐予測法を提案する.プログラム中には実行頻度の高い命令列(ホットパス)が存在し,ホットパス中の分岐命令は高確率で決まった方向に分岐する.また,少数のホットパス実行時間が全実行時間の大部分を占める.提案する分岐予測法では,ホットパス中の分岐命令と分岐先を小容量のメモリに保持し,ホットパス実行中はそのメモリを参照することで分岐予測を行う.従来のGshare分岐予測器と比較した結果,提案手法の採用により分岐予測ミス率は約2.2ポイント増加したが,分岐予測器の消費エネルギーを約40%削減することができた.

記述言語：日本語  

プロセッサにおけるソフトエラー耐U性の低下が問題になっている.ソフトエラーとは 雑音が原因で回路が一時的に誤動作する現象である.信頼性を向上させるため メモリではパリティやＥＣＣ等の誤り検出/訂正コードが用いられるしかしながら 組合せ回路にこのような誤り検出/訂正コードを加えることは難しく 多くの場合はプログラム実行を多重化(複数回実行)することでエラー検出を可能にしている本研究では 演算結果の再利用に基づく高信頼かつ低消費エネルギーなプロセッサアーキテクチャを検討する本手法ではプログラム中の同一命令の演算結果を演算結果再利用テーブルに保持しておき それを再利用する.演算結果再利用テーブルはＥＣＣで保護するため 各命令の実行を多重化することなく高い信頼性を実現できるこれにより 信頼性の向上に伴う消費エネルギー・オーバーヘッドを削減する.定量的評価を行った結果 従来の多重化に基づく方式では 多重度２のとぎ100％であった消費エネルギー・オーバーヘッドを６３％に削減することができた．The decrease in the soft error tolerance in processors becomes a problem. The soft error is a phe nomenon that the circuit does not malfunctions temporarily by the noise. To improve reliability, there is parity and ECC in the memory. However, it is difficult to add the error detection/correction code in combinational circuits. It enables the error detection by multiplexing the execution program. It has the problem that increases the energy consumption. In this research, We investigate the reliable datapath by reusing execution results. It does not execute the same instruction in detail. It maintains the result in a table, and obtains the result without ALU. The table with ECC can have reliability. The energy consumption depends on the table composition. Result of examining table composition, it can adjust the amount of the increased energy consumption to 6.3%. Key words soft error, reliability, energy consumption

記述言語：英語  

This paper presents a reconfigurable functional unit (RFU) for an adaptive dynamic extensible processor. The processor can tune its extended instructions to the target applications, after chip-fabrication, which brings about more flexibility. The custom instructions (CIs) are generated deploying the hot basic blocks during the training mode. In the normal mode, CIs are executed on the RFU. A quantitative approach was used for designing the RFU. The RFU is a matrix of functional units with 8 inputs and 6 outputs. Performance is enhanced up to 1.5 using the proposed RFU for 22 applications of Mibench. The size of configuration memory has been reduced by 40% through making the RFU partially reconfigurable, finding subsets of CIs and merging small CIs into one configuration. This processor needs no extra opcodes for CIs, new compiler, source code modification and recompilation.

記述言語：日本語  

New Generation Microprocessor Architecture (2):Security and Reliability of Advanced Microprocessors

記述言語：日本語  

これまでに多くの低リーク・キャッシュが提案された．しかしながら，これらの手法は待機状態ラインのデータを破棄するため，ミス回数が増加し必然的に性能が低下する．そこで本稿では低リーク・キャッシュにおける性能低下抑制方式として，常活性ライン方式を提案する．具体的には，性能低下の原因となる待機状態ライン・アクセスの局所性を考慮し，アクセスが集中するラインは常活性ラインにする．これまでに提案されたCache decay方式では，15.1%程度の性能低下をもたらす事で92.7%のリーク削減率を達成した．これに対し，本稿で提案する方式を適用すると，同程度のリーク削減率90.6%を維持しつつ，性能低下を5.0%に抑制することができた．A number of techniques to reduce cache leakage energy have so far been proposed. However, in these techniques, flushing the data of a turning off line causes a new cache miss. And, the increase miss degrade processor performance. We have analyzed the detail of cache-access behavior, and have found that there is a locality of accesses to the turning-off lines. Based on this observation, we propose a cache management technique to alleviate the negative effect of low-leakage caches. In our approach, cache lines having high degree of increase-miss locality are forced to stay in the high-speed but high-leakage mode. In our evaluation, the proposed scheme worsens the performance by only 5.0% with the same degree of energy reduction of the Cache decay approach.

記述言語：日本語  

本稿では、コンピュータ・システムの安全性向上を目的とした、動的プログラム認証方式を提案する。また、その安全性に関する定性的評価、ならびに、コスト/性能オーバヘッドに関する定量的評価を行う。本方式では、実行の振舞いを共通の秘密鍵情報として利用することで、1) 低い性能オーバヘッド、ならびに、2)連続的なプログラム認証、を可能にする。アプリケーション発行側では、共通秘密鍵から決定される「プログラム実行の振舞い」を実現するオブジェクト・コードを生成する。一方、利用者がわでは、専用プロファイラを用いて鍵となる実行の振舞いを動的に検出する。もし、「鍵としての実行の振舞い」 が検出できなかった場合にはプロセッサに実行停止割り込みを発行する。To challenge the security problem, we propose a hardware-base intrusion detection technique which regards the dynamic program-execution behavior as a certification key. Based on secret key. Based on secret key information, we determine an execution behavior. Then an object code which generates the determined execution behavior at run time is constructed by a secure compiler. While the program execution, a secure profiler monitors the execution behavior. If the secure profiler can not see the determined behavior, it alarms the microprocessor for terminating the current program execution. Since the viruses do not know the behavior required to continue the execution on the microprocessor, we can detect and prohibit the malicious attacks at the beginning of its execution.

記述言語：日本語  

これまでに多くの低リーク・キャッシュが提案されてきた。しかしながら、これらの手法を用いると待機状態ラインへの低速なアクセスが発生するため、必然的に性能が低下する。そこで本稿では低リーク・キャッシュにおける性能低下抑制方式として、常時活性化（always-awake）ライン方式を提案する。具体的には、性能低下の原因となる待機状態ライン・アクセスの局所性を考慮し、アクセスが集中するラインは常時活性化状態にする。これまでに提案されたDrowsy方式では、15％程度の性能低下をもたらす事で84％のリーク削減率を達成した。これに対し、本稿で提案するalways-awakeラインを用いた場合、同程度のリーク削減率を維持しつつ、性能低下を8?11％に抑制することができた。A number of techniques to reduce cachu leakage energy have so far been proposed.However,in these techniques,low speed accesses to a standby mode line degrade processor performance.We have analyzed the detail of cache-access behavior,and have found that there is a locality of accesses to the standby-mode lines.Based on this observation,we prppose a cache management technique to alleviate the nagative effect of low-leakage caches.In our approach,cache lines having high degree of sleep-hit locality are forced to stay in the high-speed but high-leakage mode.In our evaluation,it has bee observed that the Drowsy cache can achieve the performance by only 8縲鰀11% with the same degree of energy reduction of the Drowsy approach.

記述言語：日本語  

メモリ・ウォール問題（プロセッサ?主記憶間の性能差拡大）を解決する有効な手段の1つとして，Delinquent命令の活用がある．例えば，Delinquent命令のアドレス計算用コードを別スレッドとして生成し，これを投機実行する事でプリフェッチ精度を向上できる．しかしながら，プロセッサ?主記憶間の性能差は依然として拡大の一途を辿っており，Delinquent命令に着目したより効果的な高性能化方式の確立が望まれる．そこで本稿では，D命令に関する特徴解析を行う．具体的には，Delinquent命令の発生頻度や入力依存性，生存区間，アクセス・パタン等について調査する．本研究で得られた結果は，Delinquent命令に基づくメモリ性能高性能化技術開発の基礎データとして用いる事ができる．Recent remarkable advances of VLSI technology have been increasing processor speed and DRAM capacity dramatically. However, the advances also have introduced a large and growing performance gap between the processor and DRAM, this problem is referred to as "Memory Wall", resulting in poor total system performance in spite of higher processor performance. In order to solve this problem, researchers have been proposed high-performance techniques to alleviate the effect of delinquent memory-access instructions. In this paper, we investigate the detail of behavior of the delinquent memory-access instructions. The results presented in this paper will be useful to develop new approaches against the memory wall problem.

記述言語：日本語  

マイクロプロセッサと主記憶との動作周波数差は，年々拡大する一方である．両者の周波数差は，マイクロプロセッサの性能阻害要因であり，一般的にメモリ・ウォール問題と呼ばれる．本稿では，メモリ・ウォール問題の解決策のうち，再計算に基づくメモリ・システム高性能化手法 CCC (Computing Centric Computation)を提案する．CCC は，キャッシュ・ミス頻発命令を実行する代わりに再計算を行なうことで，主記憶へのアクセス回数を削減する．本稿では，性能向上が得られる可能性があるかどうかに関する予備的な評価を行なった．評価対象ベンチマークにおいて最大 45.3% の実行サイクル数削減率を達成した．In recent years,the performance gap between microprocessor speed and main memory Latency has been increasing.This problem prevents higher throughput improvements and is well-known in the literature as the Memory-Wall Problem (MWP).This paper proposes a new method to minimize the MWP effect by means of [re-computation].The basic idea is to replace frequently cache-missed loads (or delinquent loads) with a piece of code that regenerates the missed value (recomputation code).This method can be reduce the number of main memory accesses and consequently alliviate the MWP.From the experiments,one can obtain up to 45.3% reduction on computation time for SPEC2000 benchmark programs.

記述言語：日本語  

コンピュータ・システムの高い信頼性を保つためには,障害の原因となる故障を検出する必要がある.故障を検出する一般的な手法として,時間的または空間的冗長性の利用が挙げられる.しかし,それらの冗長性の実現には追加ハードウェアや実行時間の増加といった問題が生じる.本稿では,ハードウェアの大幅な変更をすることなく空間的冗長性を実現するデータパス分割方式を提案する.また,演算時に必要となる最小のビット幅を考慮し,実行時間オーバヘッドを削減する方式を提案する.最善の場合を想定し実行時間を測定した結果,冗長度2の場合で平均1.62倍,4の場合で平均3.09倍の実行時間増加となり,本手法は非常に有効であることが確認できた.

記述言語：日本語  

本稿では，コンピュータ・システムの安全性向上を目的とし，それを実現するためのアーキテクチャ・アプローチとしてセキュア・キャッシュ(SCache)を提案する．また，その安全性，性能，ならびに，消費エネルギーに関する評価を行う．近年，多くのコンピュータ・ウィルスはバッファ・オーバフローを引き起こし，関数戻りアドレスを改ざんする事でプログラム実行制御を乗っ取る．この問題を回避するため，SCache は書き込まれた戻りアドレス値の複製を生成する．ベンチマーク・プログラムを用いて定量的評価を行った結果，多くのプログラムにおいて99.7%以上の戻りアドレスの安全性を保障することができた．This paper proposes an architectural support to improve computer security, called Secure Cache (SCache), and evaluates its energy/security efficiency. A number of malicious codes attempt to hijack program-execution flow by causing stack smashing that corrupts the return address stored in a stack. In order to avoid the return address corruption, SCache generates a replica data in the cache area. In our evaluation, for many benchmarks, it is observed that more than 99.7% of return-address loads can be protected.

記述言語：日本語  

本稿では、オペランド再利用によるレジスタ・ファイル・アクセス数の削減手法を提案する。プログラム実行時、演算対象となるソース・オペランドはレジスタ・ファイルから読み出される。従来のプロセッサでは、2つの連続した命令が同一ソース・オペランドを必要とする場合、それぞれの命令に関してレジスタ・ファイル読出しが実行される。これに対し、提案手法では、先行命令によって読み出されたソース・オペランドの値をパイプライン・レジスタ内に保存し、後続命令のオペランド・フェッチ時に再利用する。また、RAWハザードを解決するために実装されたフォワーディング機能を活用することで、レジスタ・ファイル書込みに関するアクセス数も削減する。ベンチマーク・プログラムを用いて実験を行った結果、最大で62%のレジスタ・ファイル・アクセス数を削減できた。This paper proposes an energy reduction technique for register files. The proposed approach attempts to reuse operand data read from the register file in order to reduce the number of register-file accesses. If sequentially executed instructions, i and j, specify the same source operand, then the operand data read from the register file by the instruction i is reused for the instruction j. In this case, the operand fetch for the instruction j can be performed without register file activation, saving energy consumption. As well as the read operation, we can eliminate register-file write accesses by exploiting forwarding unit, which is used for solving RAW pipeline hazard problem. In our simulation, it is observed that the proposed approach can reduce the total number of register-file accesses by 62% from a conventional model.

記述言語：日本語  

これまでに我々は,ダイレクト・マップ命令キャッシュの低消費エネルギー化を目的として,ヒストリ・ベース・タグ比較(HBTC:History Based Tag-Comparison)方式を提案した.従来型キャッシュでは,ヒット/ミス判定のために,タグ比較が毎アクセス実行される.これに対し,HBTCキャッシュでは,プログラムの実行履歴に基づき必要に応じてタグ比較を行う.そして,無駄なタグ比較処理を動的に検出・削除し,命令キャッシュの低消費エネルギー化を実現する.本稿では,これまでに提案したHBTCキャッシュを改良し,オーバヘッドの小さい新しい実現方式を示す.また,信号処理アプリケーションを中心としたベンチマーク・プログラムを用いて,性能ならびに消費エネルギーに関するより詳細な評価を行う.

記述言語：日本語  

これまでに我々は,ダイレグト・マップ命令キャッシュの低消費エネルギー化を目的として,ヒストリ・ベース・タグ比較(HBTC:History Based Tag-Comparison)方式を提案した.従来型キャッシュでは,ヒット/ミス判定のために,タグ比較が毎アクセス実行される.これに対し,HBTCキャッシュでは,プログラムの実行履歴に基づき必要に応じてタグ比較を行う.そして,無駄なタグ比較処理を動的に検出・削除し,命令キャッシュの低消費エネルギー化を実現する.本稿では,これまでに提案したHBTCキャッシュを改良し,オーバヘッドの小さい新しい実現方式を示す.また,信号処理アプリケーションを中心としたベンチマーク・プログラムを用いて,性能ならびに消費エネルギーに関するより詳細な評価を行う.

記述言語：日本語  

命令発行メモリ（命令ウィンドウ）の低消費電力化を目的として、適応型命令発行メモリが提案された。プログラムが有する命令レベル並列度に応じて使用可能なエントリ数（命令発行メモリ・サイズ）を動的に最適化し、負荷容量を削減することで低消費電力化できる。本稿では、更なる低消費電力化を実現するため、二電源電圧を用いた適応型命令発行メモリを提案する。従来の適応型命令発行メモリでは、単一電源電圧が用いられる。これに対し、提案手法では、命令発行メモリ・サイズを縮小した際に低電源電圧を使用する。つまり、命令発行メモリ・サイズの変更に応じて電源電圧も変化させる。CMOS 回路の消費電力は電源電圧の２乗に比例するため、低電源電圧化により大幅な消費電力の削減を期待できる。また、命令発行メモリ・サイズを縮小した場合にのみ低電源電圧を用いるため、低電源電圧化に伴う遅延時間オーバヘッドを隠蔽できる。評価を行った結果、本手法を適用することで、大幅な性能低下を伴うことなく最大３６％の命令発行メモリ消費電力を削減できた。This paper presents a novel architectural technique to reduce energy dissipation of adaptive issue queue, whose functionality is dynamically adjusted at runtime to match the changing computational demands of instruction stream. In contrast to existing schemes, the technique exploits a new freedom in queue design, namely the voltage per access. Since Since loading capacitance operated in the adaptive queue varies in time, the clock cycle budget becomes inefficiently exploited. We propose to trade-off the unused cycle time with supply voltage, lowering the voltage level when the queue functionality is reduced and increasing it with the activation of resources in the queue. Experiments show that the approach can save up to 36% of the issue queue energy without large performance and area overhead.

記述言語：日本語  

本稿では，低消費エネルギー化を実現する新しい命令キャッシュ・アーキテクチャとして、ヒストリ・ベース・ルックアップ・キャッシュ（HBLキャッシュ）を提案する。また、ベンチマーク・プログラムを用いた定量的評価を行い、その有効性を明らかにする。あるデータを格納可能なキャッシュ内ロケーションが複数存在するセット・アソシアティブ・キャッシュでは、参照データが唯一のウェイにのみ存在する（ヒットの場合）。それにも関わらず、従来型キャッシュでは、アクセス時間を短縮するために全てのウェイが並列に検索される。これに対し、HBL キャッシュは、過去のタグ比較結果を再利用し、参照データ検索における無駄なウェイ・アクセスを回避することで、低消費エネルギー化を実現する。ベンチマーク・プログラムを用いた定量的評価を行った結果、従来型キャッシュと比較して、約0.2％の性能低下を伴うだけで、最大72％のキャッシュ・アクセス消費エネルギーを削減できた。This paper proposes a novel architecture for low-power instruction caches called "history-based look-up cache (HBL cache)". In conventional n-way set-associative cashes, there are ｎ locations where a cache line can be placed in the cache space, and all ways are activated on every cache access because of the parallel search strategy. On the other hand, the HBL cache attempts to reuse the tag comparison results, and reduces the cache-access energy by avoiding the unnecessary way activations. The tag-comparison results are recorded in an extended BTB (Branch Target Buffer) for branch prediction. In our evalutation, it is observed that the HBL cache reduces the energy consumption by about 72% while it degrades the performance by only 0.2%, compared with a conventional set-associative cache.

記述言語：日本語  

本稿では、データ圧縮による画像処理用メモリの低消費電力化手法を提案する。画像処理システムでは、FIFOなどの逐次アクセスを基本動作とするメモリ（フレームメモリ等）が使用される。従来のメモリシステムでは、ワードデータ中に含まれる全てのビットデータが読み出し、書き込みの対象となる。これに対し、本手法では、連続するデータ間の差分情報のみを読み出し・書き込みの対象とする。これにより、活性化すべきビットライン数を削減し、低消費電力化を実現できる。一般に、連続する画素間には相関関係があるため、連続メモリ・アクセス対象データ間の差分をとることで効率的にデータ圧縮を行える。６種類の動画像データを用いて評価を行った結果、フレームメモリの消費電力を１１?１６％削減できた。This paper propses an idea for reducing power consumption of video memories through data compression. In video memory system, in-order-access memories are used, e.g., frame memory. In a conventional memory, all bitlines are activated for reading or writing. On the other hand, our approach attempts to compress the read (or write) data, and activates only bitlines corresponding to the difference-bits between the successively sccessed data. As a result, we can reduce the power consumption for the memory access by means of reducing the total number of bitline switching. In our simulation, it is ovserved that our approach can reduce the power consumption of frame memory by 11% - 16% for many video sequences.

記述言語：その他  

A Low-Power Instruction Cache Architecture Exploiting Program Execution Footprints