Language：English   Publishing type：Research paper (scientific journal)  

Multi-operand adders that calculate the summation of more than two operands usually consist of compressor trees, which reduce the number of operands to two without any carry propagation, and carry-propagate adders for the two operands in the ASIC implementation. Compressor trees that consist of full adders and half adders cannot be implemented efficiently on LUT-based FPGAs, and carry-chains or dedicated structures have been utilized to produce multi-operand adders on FPGAs. Recent studies indicate that compressor trees can be implemented efficiently on LUTs using Generalized Parallel Counters (GPCs) as the building blocks of compressor trees. This paper addresses the problem of synthesizing compressor trees based on GPCs. Based on the observation that characteristics such as the area, power, and delay correlate roughly to the total number and the maximum level of GPCs, the target problem can be regarded as a minimization problem for the total number of GPCs and the maximum levels of the GPCs, for which an ILP-based approach is proposed. The key point of our formulation is not to model the problem based on the structures of compressor trees like the existing approach, but instead the compression process itself is used to reduce the number of variables and constraints in the ILP formulation. The experimental results demonstrate the advantage of our formulation in terms of the quality and runtime.

Language：English   Publishing type：Research paper (scientific journal)  

This paper presents two acceleration techniques of fault simulation for analyzing soft error propagation in sequential circuits. One is an exact technique and the other is a heuristic technique. Since these techniques are independent on how the logic functions of circuits are evaluated, they can be combined with other techniques which accelerate evaluations of the logic functions of circuits, such as event-driven simulation, single pattern parallel fault propagation (SPPFP). Experimental results show that applying the exact technique makes a fault simulator with event-driven simulation and SPPFP 30-143 times faster. A fault simulator with the exact technique finished for several large-scale circuits in 4.6 hours or less, while a fault simulator without the exact technique could not finish for such circuits in 72 hours. Furthermore, applying the heuristic technique makes a fault simulator with the exact technique about 7-17 times faster with only 0.5-2.2% estimation error.

DOI： http://dx.doi.org/10.2197/ipsjtsldm.6.127

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.2197/ipsjtsldm.5.63

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.2197/ipsjtsldm.5.55

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1587/transfun.E94.A.2579

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Repository Public URL： http://hdl.handle.net/2324/13532

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Language：Japanese   Publishing type：Research paper (scientific journal)  

On boolean mathing algorithm for LUT-type FPGA based on functional decomposition

Language：English   Publishing type：Research paper (scientific journal)  

Yusuke Matsunaga, An Efficient Algorithm Finding Simple Disjoint Decompositions Using BDDs, IEICE Transactions on Fundamentals, Vol. E85-A, No. 12, pp. 2715-2724, Dec. 2002

Language：English  

DOI： 10.1016/j.bbrc.2024.150001

Web of Science

PubMed

Language：English   Publisher：北里医学会  

Language：English  

DOI： 10.3389/fcvm.2024.1369831

Web of Science

PubMed

Language：English   Publisher：(一社)日本睡眠学会  

COVID-19のパンデミック中にあった日本の女子大学生の集団で、睡眠およびレジリエンスという要因がストレス反応に与える影響について検討した。東京都にある単一の女子大学の学生103名(平均20.2±1.0歳)を2022年に調査した。睡眠の評価にはピッツバーグ睡眠質問票の日本語版(PSQI-J)を、レジリエンスの評価には大学生用レジリエンス尺度(RS-S)を、ストレス反応の評価には心理的ストレス反応測定尺度(SRS-18)を使用した。重回帰分析の結果、SRS-18スコアのおよそ40%は、PSQI-JスコアとRS-Sスコアによって説明可能であることが示された。特に、PSQI-Jで評価された主観的な睡眠の質のスコア、日中覚醒困難スコア、総合スコアは、SRS-18へ直接に影響を及ぼしていた。

Language：English  

DOI： 10.3389/fcvm.2023.1212882

Web of Science

PubMed

DOI： 10.1016/j.pdj.2023.04.001

Web of Science

Language：English   Publisher：BioMed Central  

血液透析(HD)患者を対象に、抑うつ症状と身体機能がそれぞれ独立して、または交互作用を示しつつ日常身体活動量に関連しているかどうか検討した。国内の単一透析センターにおいて、臨床的に安定した状態にあった外来HD患者157名(男性91名、年齢中央値68.0歳)を2018年4月～2019年3月に横断解析した。身体活動量は、加速度計を用いて1日当たりの歩数を透析日ではない連続4日間で計測することで評価した。身体機能の評価には10m歩行試験で記録された通常時の歩行速度を、抑うつ症状の評価にはCES-D尺度の10項目版を使用した。臨床的諸特性から成る回帰モデルに、身体機能、抑うつ症状、身体機能と抑うつ症状の交互項を順次加えてゆき、決定係数(R2値)の変化をみる階層的重回帰分析を施行した。その結果、HD患者では身体機能は独立して身体活動量に強く関連しているが、抑うつ症状と身体活動量の間には独立した関連性はないことが判明した。さらに単純傾斜分析も施行した結果、身体機能が比較的高く独歩可能なHD患者では、身体機能と抑うつ症状は交互的に日常身体活動量と関連していることが示された。

Language：English   Publisher：BioMed Central  

安定的な血液透析(HD)治療を週3回受けている外来患者203名(年齢中央値69歳)を対象として、その精神症状の有病率と数を調査し、精神症状と日常生活動作(ADL)との関係を評価した。精神症状としては抑鬱症状(DS)、アパシー(APA)、睡眠障害(SD)を取り上げ、年齢、性別などの患者特性は医療記録から収集し、機能状態はADL項目の自己評価質問票で評価した。その結果、59名がDS、100名がAPA、83名でSD症状の報告があった。3症状の重複度は31名が3症状、43名が2症状、63名が1症状のみで、66名には精神症状を認めなかった。多重ロジスティック回帰分析では、患者特性と歩行速度の調整後でも重複精神症状がADLと独立的に有意な関連を示した。これらの結果から、DS、APA、SDなどの重複症状は、HD患者のADL低下と独立して関連していることが明らかになった。

Language：English  

DOI： 10.1177/11795484221146374

Web of Science

PubMed

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Event date： 2020.7

Language：English   Presentation type：Oral presentation (general)  

Venue：ロードス島   Country：Greece  

This paper presents a novel efficient SAT-attack algorithm for logic
encryption.
The existing SAT-attack algorithm can decrypt almost all encrypted
circuits proposed so far, however, there are cases that it takes
a huge amount of CPU time.
This is because the number of clauses being added during the
decryption increases drastically in that case.
To overcome that problem, a novel algorithm is developed,
which considers the equivalence of clauses to be added.
Experiments show that the proposed algorithm is much faster than
the existing algorithm.

Event date： 2020.3

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：沖縄県・那覇市（新型コロナウィルスの影響の実際の講演中止）   Country：Japan  

本稿では論理IPの剽窃や盗用を防ぐための論理暗号化手法として
提案したアフィン変換に基づく手法の一実装例として単純な
アフィン変換を取り上げる．
これは対象となる出力に関する部分回路を複製して他の回路と分離した上で
外部入力部分にアフィン変換を施すもので，
アフィン変換部分以外まったく新たな回路を設計する必要がない．
このような単純な方法であるにも関わらずSAT攻撃に耐性があることがわかっ
た．
暗号化を施す対象の部分回路の選択方法に関していくつかの方法を提案し，
評価実験を行った．

Event date： 2020.1

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：慶應義塾大学（神奈川県・横浜市）   Country：Japan  

本稿では論理IPの剽窃や盗用を防ぐための論理暗号化手法として
アフィン変換を用いた手法の提案を行う．
現在のところ最も堅固と考えられる暗号化手法であるSFLL(stripped
funcitionality logic locking)に比べて回路を変更する自由度が高く
付加回路のオーバーヘッドも少ない特長を持つ．

Event date： 2019.8

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：山代温泉ゆのくに天祥（石川県）   Country：Japan  

本稿では論理IPの剽窃や盗用を防ぐための論理暗号化手法およびそれに対する攻撃手法
について概観した上で，現在のところ最も強力な攻撃手法と考えられている
SAT攻撃アルゴリズムに耐性を持つ論理暗号化手法であるTTLockの紹介を行う．
TTLockの暗号化を実現する上での論理合成における課題を提示したうえで，
誤り修正手法に基づく論理暗号化手法について考察する．

Event date： 2019.7

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：袋田温泉   Country：Japan  

本稿では論理IPの剽窃や盗用を防ぐための論理暗号化手法およびそれに対する攻撃手法
について概観した上で，現在のところ最も強力な攻撃手法と考えられている
SAT攻撃アルゴリズムに耐性を持つ論理暗号化手法であるTTLockの紹介を行う．
TTLockの暗号化を実現する上での論理合成における課題を提示したうえで，
誤り修正手法に基づく論理暗号化手法について考察する．

Event date： 2019.2 - 2019.3

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：沖縄県青年会館   Country：Japan  

本稿では論理IPの剽窃や盗用を防ぐための論理暗号化手法に対する攻撃手法
であるSAT攻撃の効率的なアルゴリズムの評価結果について報告する．
既存のSAT攻撃アルゴリズムと，
追加する節の元となっている論理回路の等価性を調べることで
重複した節の追加を行わない改良版のSAT攻撃アルゴリズム
をベンチマーク回路に適用して計算時間などの評価を行った．
ほとんどの例で生成される変数や節の数，計算時間などが
削減されており，提案手法の有効性を明らかにしている．

Event date： 2018.12

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：広島県立大学   Country：Japan  

本稿では論理IPの剽窃や盗用を防ぐための論理暗号化手法に対する攻撃手法
であるSAT攻撃の効率的なアルゴリズムについて述べる．
既存のSAT攻撃アルゴリズムは従来の暗号化手法のほとんどを解読することが
可能であるが，
多大な計算時間を要する場合もある．
これはSAT問題を繰り返し解いていく際に追加される節の数が膨大になってい
ることに起因する．
そこで，追加する節の元となっている論理回路の等価性を調べることで
重複した節の追加を行わない改良版のSAT攻撃アルゴリズムを開発した．
実験結果によればほとんどの例題に対してより短い時間で処理を行っており，
最大で35倍の高速化を達成している．

Event date： 2018.8

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：山代温泉　ゆのくに天祥（石川県加賀市山代温泉19-49-1）   Country：Japan  

本稿ではLSIの製造故障に対するテストパタン集合の最小化問題に対する新しい定式化を示す．
通常，一つのテストパタンは複数の故障を検出することができる．この特徴を考慮すると
テストパタン集合の最小化問題は集合被覆問題と考えることができる．
一方，不定値('X')を含む複数のテストパタンは同じビット位置に相反する値を持たない限りマージして
一つのテストパタンにまとめることが可能である．
この特徴を考慮するとテストパタンの最小化問題は
グラフ彩色問題とみなすことができる．
実際には，この2つの特徴を同時に考慮する必要があるため既存の組み合わせ最適化問題として定式化することは
難しい．そこで両立集合被覆問題と名付けた新たな組み合わせ最適化問題を定義する．
また，この問題に対するヒューリスティック解法を提案する．

Event date： 2018.3

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：沖縄県青年会館   Country：Japan  

Event date： 2017.11

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：熊本県民交流会館パレア   Country：Japan  

本稿ではSATソルバを用いた低消費電力向けテストパタン圧縮手法の提案を行
う．
基本となるアイデアは，元の制約式に複数の変数のXORで構成された制約式を追加することで
SAT問題のサンプリングを行う手法を用いて候補となるパタンを生成し，
そのなかから与えられた信号遷移回数の制約を満たしつつ要素数が少なくなる
テストパタン集合を最小集合被覆問題を解くことで得るというものである．
実験結果より，サンプリングの数を増やすことでより要素数の少ないテストパ
タン集合が得られることが確認されている．
提案するヒューリスティックの有効性およびロバスト性を示している．

Event date： 2017.8 - 2016.9

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：山代温泉　ゆのくに天祥（石川県加賀市山代温泉19-49-1）   Country：Japan  

Event date： 2017.6

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：新潟大学五十嵐キャンパス   Country：Japan  

本稿では信号遷移回数を考慮した遷移故障向けテストパタンを生成する
SATソルバを用いた手法について考察を行う．
通常のSATソルバを用いた手法では故障を検出する論理的な制約を
満たすテストパタンが唯一得られるだけで信号遷移回数のコントロールを
行うことはできない．
そこで，テストパタン生成問題を表すCNF式にランダムに生成した式を追加
することで元の問題に対するランダムサンプリングを行う手法を用いて
テストパタンのランダムサンプリングを行うアルゴリズムを提案する．
生成された複数のパタンの中から信号遷移回数や消費電力などの尺度
で優れたパタンを選択することで従来不可能であったSATソルバを
用いたテストパタン生成において解の質をコントロールすることが
可能となっている．

Event date： 2016.11

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：弘前市立観光館   Country：Japan  

本稿では信号遷移回数を考慮した遷移故障向けテストパタンを生成する
SATソルバを用いた手法について考察を行う．
通常のSATソルバを用いた手法では故障を検出する論理的な制約を
満たすテストパタンが唯一得られるだけで信号遷移回数のコントロールを
行うことはできない．
そこで，SATを用いたテストパタン生成アルゴリズムに修正を行って，
故障検出を行うパタンの集合を積和形論理式の形で出力し，
そこからランダムサンプリングを行い，
そのなかから信号遷移回数の少ないパタンを選択する手法を提案する．

Event date： 2016.9

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：山代温泉　ゆのくに天祥（石川県加賀市山代温泉19-49-1）   Country：Japan  

本稿ではモンテカルロ木探索をLUT型FPGA向けテクノロジマッピングに応用し
たアルゴリズムについて述べる．
テクノロジマッピング問題が複雑になる原因はファンアウト部分の取り扱いに
ある．
そこで，予め回路のどの部分がファンアウト境界になるかを決めた上で
既存のテクノロジマッピングのアルゴリズムであるDAG Coveringアルゴリズム
を適用することで解空間を区切って探索する方法を考案した．
このアルゴリズムとモンテカルロ木探索を組み合わせたテクノロジマッピング
アルゴリズムの紹介を行う．

Event date： 2016.6

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：弘前市立観光館   Country：Japan  

本稿ではランダムパタンを用いて遷移故障向けのテストパタン生成をする際に，
信号遷移回数を考慮する手法について提案する．
具体的には各々のパタンを印加した時の信号遷移回数に基づいた確率分布を持
つマルコフ連鎖モデルを構築し，
そのマルコフモデル上でランダムサンプリングを行うことで信号遷移回数を考
慮したランダムパタンの生成を行うものである．
ベンチマークを用いた実験の結果，提案手法で生成されたパタンは検出する故
障数では信号遷移回数に制限を設けない単純な手法の結果とほぼ同等の結果を
得られることがわかった．
ただしパタン数は多くなる傾向にある．

Event date： 2015.12

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：長崎県勤労福祉会館   Country：Japan  

Event date： 2015.12

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：長崎県勤労福祉会館   Country：Japan  

Event date： 2015.8

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：山代温泉　ゆのくに天祥（石川県加賀市山代温泉19-49-1）   Country：Japan  

Event date： 2015.6

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：小樽商科大学   Country：Japan  

本稿では大規模回路に適用可能なテストパタン集合最小化手法の高速化技術につ
いて述べる．
具体的には，故障もしくは故障集合の検出条件に対する，十分割り当てと必要割
り当てという概念を提案し，それらを用いて，故障間の支配関係や両立関係の
検査を効率よく行うアルゴリズムを提案している．
ベンチマーク回路を用いた評価実験の結果，
同様の処理を行う既存手法に比べて同等の解をはるかに高速に求めることに成功している．
特に大規模な回路に対して高速化の効果が大きい．

Event date： 2015.5

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：北九州国際会議場   Country：Japan  

Event date： 2015.1

Language：English   Presentation type：Oral presentation (general)  

Venue：Chiba   Country：Japan  

This paper describes two speed-up techniques for Boolean matching of LUT-based circuits. One is one-hot encoding technique for variables representing input assignments. Though it requires more variables than existing binary encoding technique, almost all added clauses using one-hot encoding are binary clauses, which are suitable for efficient Boolean constraint propagation. The other is CEGAR (counter example guided abstraction refinement) technique which reduces the CPU time significantly. With both techniques, we can solve Boolean matching problem with 9 input function in 20 milliseconds on average, which is faster than the existing algorithms more than one order of magnitude.

Event date： 2014.11

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：東北大学   Country：Japan  

本稿では並列インデックス生成器を合成する際に必要となるベクタ集合の分割を効率よく表現する手法に
ついて述べる．具体的には，分割により区別されるベクタ対の集合を2 分決定グラフを用いて非明示的に列挙し，分
割に関する演算を2 分決定グラフを用いた論理演算で実現するものである．

Event date： 2014.10

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：東北大学   Country：Japan  

本稿では並列インデックス生成器を用いた実
現を対象にした入力変換回路の合成手法について提案を行う．
実験の結果，提案した合成手法で生成した変換回路を並列イン
デックス生成器の入力として用いることで，均一に分布してい
ない例に対しても下限に近いサイズのメモリ量でインデックス
生成器を構成できることが示されている．

Event date： 2014.7

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：北海道大学   Country：Japan  

本稿では複数のLUT からなる回路が与えられた論理関数を実現できるかどうかを調べるブーリアンマッチ
ングの高速化手法について述べる．従来の手法ではナイーブな段階的探索を用いていたのに対して，本稿で提案する
改良アルゴリズムはCEGAR(counter example guided abstraction refinment: 反例に基づく段階的抽象化) と呼ばれる手法
を用いてさらなる高速化を達成している．

Event date： 2014.3

Language：English   Presentation type：Oral presentation (general)  

Venue：Dresden, Germany   Country：Germany  

The index generation function is a multi-valued logic function which checks if the given input vector is a registered or not, and returns its index value if the vector is registered. If the latency of the operation is critical, dedicated hardware is used for implementing the index generation functions. This paper proposes a new method implementing the index generation functions. This method requires only one memory access while the existing method requires twice. The proposed method also has an advantage for total memory size against to the existing method.

Other Link： www.date-conference.com

Event date： 2014.1

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：慶應義塾大学日吉キャンパス   Country：Japan  

本稿では複数のLUTからなる回路が与えられた論理関数を実現できるかどうかを
調べるブーリアンマッチングの高速化手法について述べる．
高速化手法は2つある．1つは入力順序の割り当てをone-hot符号化された変数を
用いて表す手法であり，従来の2進符号化に比べると必要となる変数の数は増え
るが，ほとんどの制約が2項節の形で与えられるため，
SATソルバにおいて効率的な値の伝搬が行える．
もう1つは段階的探索手法で，マッチングが失敗する例において，
部分的な制約式のみを評価することで早めに充足不能と判定を行い，無駄な探
索を省いている．充足可能となる場合でも以前の評価の結果得られた学習節が
後の評価の際にも用いられるのでオーバーヘッドは少ない．

Event date： 2013.11

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：鹿児島県文化センター   Country：Japan  

インデックス生成関数とは，与えられた入力ベクタが既に登録されたものであるかを調べ，もし登録されていた場合にはそのインデックス番号を返すたち論理関数である．
本稿では複数のインデックス生成器を並列に構成してインデックス生成関数を実現する場合の合成アルゴリズムについて述べる．
具体的には，``コンフリクトフリー分割''と呼ばれる新規の効果的なアルゴリズムを提案している．実験結果によれば既存手法に比べて約半分程度のメモリ容量でインデックス生成関数を実現できている．

Event date： 2013.8

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：岐阜県下呂温泉水明館   Country：Japan  

与えられたデータの集合に対して重複しないインデックスを返す関数を完全ハッシュ関数と呼ぶ．
本稿では，ハードウェアの実装に適した完全ハッシュ関数の構成法について述べ る．

Event date： 2013.7

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：熊本大学   Country：Japan  

インデックス生成関数とは，与えられた入力ベクタが既に登録されたものであるかを調べ，もしも登録されていた場合にはそのインデックス番号を返す多値論理関数である．インデックス生成関数の応答時間が重要な場合には，専用のハードウェアを用いた実現方法が用いられる．本稿では，従来手法では連続した2回のメモリアクセスを必要としてのに対して，1回のメモリアクセスで結果を出力するインデックス生成関数の実現方法について述べる．本手法は総メモリ量の面においても従来手法よりも効率的である．

Event date： 2013.6

Language：English   Presentation type：Oral presentation (general)  

Venue：Marriott Countryyard, Austin, TX   Country：United States  

The index generation function is a multi-valued logic function which checks if the given input vector is a registered or not, and returns its index value if the vector is registered. If the latency of the operation is critical, dedicated hardware is used for implementing the index generation functions. This paper proposes a new method implementing the index generation functions. This method requires only one memory access while the existing method requires twice. The proposed method also has an advantage for total memory size against to the existing method.

Other Link： www.iwls.org/iwls2012

Event date： 2013.2

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：機械振興会館   Country：Japan  

SATソルバを用いてテスト生成を行なう場合，単純な方法では1つの故障に対するテスト生成問題を1つの充足可能性判定問題として表してSATソルバを起動する．本稿では複数の故障に対するテスト生成問題をいくつかの制御変数を付加した1つの充足可能性判定問題として表すことで，テスト生成全体にかかる計算時間の短縮を行なう手法について述べる．いくつかの工夫を行なうことで，数倍から10倍程度の高速化を達成している．

Event date： 2012.11

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：九州大学百年記念講堂   Country：Japan  

論理合成処理のテクノロジマッピングやローカルリライティングではサイズの小さな多数のパタンを用いている．メモリの使用を効率化するために，複数のパタン中の同形の部分グラフを共有しているが，それでも多くのメモリ領域を必要とする場合が多い．そこで，本稿では枝に入力変数の反転と置換を行なうNP変換の属性を付加することでより多くの部分グラフ共有可能とするデータ構造について提案を行なう．

Event date： 2012.7

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：京都リサーチパーク   Country：Japan  

本稿では，論理回路の2つの信号線間に成り立つ含意関係のうち，直接的な操作では求めることのできない間接含意を効率よく求めるアルゴリズムについて述べる．本アルゴリズムは個々の信号線の値を0または1に決定する原因となる値の割り当てリストを推移的に計算することによって高速に多くの間接含意を求めるものである．また，比較のためにSAT(充足可能性判定問題)ソルバを用いて全ての間接含意を列挙する実験を行い，提案アルゴリズムの効率性と効果を確認した．

Event date： 2012.6

Language：English   Presentation type：Oral presentation (general)  

Venue：University of Californica, Berkeley   Country：United States  

Other Link： www.iwls.org/iwls2012

Event date： 2012.3

Presentation type：Oral presentation (general)  

Venue：University of Illinois, IL, USA   Country：United States  

Event date： 2012.3

Language：English   Presentation type：Oral presentation (general)  

Venue：University of Illinois   Country：United States  

Event date： 2012.3 - 2013.3

Presentation type：Oral presentation (general)  

Venue：ビーコンプラザ、大分   Country：Japan  

Event date： 2011.11

Presentation type：Oral presentation (general)  

Venue：ニューウェルシティ宮崎   Country：Japan  

Event date： 2011.10

Presentation type：Oral presentation (general)  

Venue：Marriott Vancouver Pinnacle Hotel, Vancouver, Canada   Country：Canada  

Event date： 2011.9

Presentation type：Oral presentation (general)  

Venue：会津大学   Country：United States  

Event date： 2011.8

Presentation type：Oral presentation (general)  

Venue：Fukuoka   Country：Japan  

Event date： 2011.7

Presentation type：Oral presentation (general)  

Venue：Metropolitan hotel, Athens, Greece   Country：Greece  

Event date： 2011.7

Presentation type：Oral presentation (general)  

Venue：Metropolitan hotel, Athens, Greece   Country：Greece  

Event date： 2011.6

Presentation type：Oral presentation (general)  

Venue：University of California, San Diego, CA, USA   Country：United States  

Event date： 2011.6

Presentation type：Oral presentation (general)  

Venue：University of California, San Diego, CA, USA   Country：United States  

Event date： 2011.5

Presentation type：Oral presentation (invited, special)  

Venue：Dana Point, CA, USA   Country：United States  

Event date： 2010.5

Presentation type：Oral presentation (general)  

Venue：北九州国際会議場   Country：Japan  

Event date： 2010.5

Presentation type：Oral presentation (general)  

Venue：北九州国際会議場   Country：Japan  

Repository Public URL： http://hdl.handle.net/2324/17764

Event date： 2010.4

Presentation type：Oral presentation (general)  

Venue：軽井沢プリンスホテル   Country：Japan  

Event date： 2010.3

Presentation type：Oral presentation (general)  

Venue：沖縄県男女共同参画センター「てぃるる」   Country：Japan  

Repository Public URL： http://hdl.handle.net/2324/16892

Event date： 2009.12

Presentation type：Oral presentation (general)  

Venue：高知市文化プラザ   Country：Japan  

Event date： 2009.12

Presentation type：Oral presentation (general)  

Venue：高知市文化プラザ   Country：Japan  

Repository Public URL： http://hdl.handle.net/2324/16081

Event date： 2009.9

Presentation type：Oral presentation (general)  

Venue：ホテルアローレ（石川県）   Country：Japan  

Event date： 2009.9

Presentation type：Oral presentation (general)  

Venue：大阪大学   Country：Japan  

Repository Public URL： http://hdl.handle.net/2324/16080

Event date： 2009.8

Presentation type：Oral presentation (general)  

Venue：ホテルアローレ（石川県）   Country：Japan  

Repository Public URL： http://hdl.handle.net/2324/16078

Event date： 2009.7 - 2009.8

Presentation type：Oral presentation (general)  

Venue：Cadence Berkeley Lab. , Berkeley, CA   Country：United States  

Repository Public URL： http://hdl.handle.net/2324/15427

Event date： 2009.7 - 2009.8

Presentation type：Oral presentation (general)  

Venue：Cadence Berkeley Lab. , Berkeley, CA   Country：United States  

Event date： 2009.5

Presentation type：Oral presentation (general)  

Country：United States  

Event date： 2009.4

Presentation type：Oral presentation (general)  

Venue：首都大学東京秋葉原サテライトキャンパス   Country：Japan  

Repository Public URL： http://hdl.handle.net/2324/16076

Event date： 2009.4

Presentation type：Oral presentation (general)  

Venue：首都大学東京秋葉原サテライトキャンパス   Country：Japan  

Repository Public URL： http://hdl.handle.net/2324/16990

Event date： 2009.4

Presentation type：Oral presentation (general)  

Venue：首都大学東京秋葉原サテライトキャンパス   Country：Japan  

Event date： 2009.3

Presentation type：Oral presentation (general)  

Venue：愛媛大学   Country：Japan  

Event date： 2009.3

Presentation type：Oral presentation (general)  

Venue：沖縄県男女共同参画センター「てぃるる」   Country：Japan  

Repository Public URL： http://hdl.handle.net/2324/13844

Event date： 2009.1

Presentation type：Oral presentation (general)  

Venue：岩手県民情報交流センター   Country：Japan  

Repository Public URL： http://hdl.handle.net/2324/14702

Event date： 2008.10

Presentation type：Oral presentation (general)  

Venue：Lake Tahoe   Country：United States  

Event date： 2008.10

Presentation type：Oral presentation (general)  

Venue：岩手県民情報交流センター   Country：Japan  

Event date： 2008.10

Presentation type：Oral presentation (general)  

Venue：岩手県民情報交流センター   Country：Japan  

Event date： 2008.9

Presentation type：Oral presentation (general)  

Venue：大分大学   Country：Japan  

Event date： 2008.8

Presentation type：Oral presentation (general)  

Venue：遠鉄ホテルエンパイア（静岡県浜松市）   Country：Japan  

Repository Public URL： http://hdl.handle.net/2324/12505

Event date： 2008.5

Presentation type：Oral presentation (general)  

Venue：神戸大学   Country：Japan  

Event date： 2008.5

Presentation type：Oral presentation (general)  

Venue：神戸大学   Country：Japan  

Event date： 2008.1

Presentation type：Oral presentation (general)  

Venue：Seoul   Country：Korea, Republic of  

Event date： 2008.1

Presentation type：Oral presentation (general)  

Venue：Seoul   Country：Korea, Republic of  

Event date： 2007.10

Presentation type：Oral presentation (general)  

Venue：札幌   Country：Japan  

Event date： 2007.10

Presentation type：Oral presentation (general)  

Venue：Atlanta   Country：United States  

Event date： 2007.5 - 2007.6

Presentation type：Oral presentation (general)  

Venue：San Diego   Country：United States  

Event date： 2007.3

Presentation type：Oral presentation (general)  

Venue：Stresa   Country：Italy  

Presentation type：Oral presentation (general)  

Venue：仙台   Country：Japan  

Y. Matsunaga, An Exact and Efficient Algorithms for Disjunctive Decomposition, Synthesis And System Integration of Mixed Technologies (SASMI'98), Oct. 1998

Event date： 2023.3

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：電気ビル共創館カンファレンス（福岡県福岡市）   Country：Japan  

Event date： 2022.1

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：福岡市　天神クリスタルビル   Country：Japan  

Event date： 2022.1

Language：Japanese  

Venue：福岡市 天神クリスタルビル   Country：Japan  

researchmap

Event date： 2021.1

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：オンライン   Country：Japan  

Event date： 2014.3

Language：English  

Venue：Dresden   Country：Germany  

The index generation function is a multi-valued logic function which checks if the given input vector is a registered or not, and returns its index value if the vector is registered. If the latency of the operation is critical, dedicated hardware is used for implementing the index generation functions. This paper proposes a method implementing the index generation functions using parallel index generation units. A novel and efficient algorithm called 'conflict free partitioning' is proposed to synthesis parallel index generation units. Experimental results show the proposed method outperforms other existing methods.

Event date： 2012.6

Language：English  

Venue：Sitges   Country：Spain  

This paper presents a novel neutron-induced soft-error-rate (SER) estimation tool with a particle transport code: PHITS. The proposed tool can calculate the SER according to various data patterns and the layout of the memory cells in an SRAM. As layouts, two kinds of an NMOS-PMOS-NMOS 6T and an inside-out PMOS-NMOS-PMOS versions are considered. The proposed tool distinguishes a single-event-upset (SEU) SER, a horizontal multiple-cell-upset (MCU) SER, and a vertical MCU SER using an extracting function. The horizontal MCU SER in the inside-out version of the PMOS-NMOS-PMOS 6T SRAM cell layout was expected to be 26-41% less than that of the general NMOS-PMOS-NMOS 6T cell layout.

Event date： 2011.10

Language：English  

Venue：Vancouver, BC   Country：Canada  

In advanced technology, soft error tolerance of VLSIs decreases. Soft errors might cause VLSIs to failure. However, there is no exact method to estimate soft error tolerance for sequential circuits of VLSIs. We propose an exact method to estimate soft error tolerance for sequential circuits. The failure due to soft errors in sequential circuits is defined by using the modified product machine. The behavior of the modified product machine is analyzed using Markov model strictly. We also propose two acceleration techniques to apply the exact method to larger scale circuits. Two acceleration techniques reduce the number of variables of simultaneous linear equations. We apply the proposed method to ISCAS'89 and MCNC benchmark circuits and estimate soft error tolerance for sequential circuits. Experimental results shows that two acceleration techniques reduce up to 10 times from its original execution time.

Event date： 2011.8

Language：English  

Venue：Fukuoka   Country：Japan  

Recent researches have indicated that multi-operand addition on FPGAs can be efficiently realized as the architecture consisting of a compressor tree which reduces the number of operands and a carry-propagate adder like ASIC by utilizing generalized parallel counters(GPCs). This paper addresses power and delay aware synthesis of GPC-based compressor trees. Based on the observation that dynamic power would correlate to the number of GPCs and the levels of GPCs, our approach targets to minimize the maximum levels and the total number of GPCs, and an ILP-based algorithm and heuristic approaches are proposed. Several experiments targeting Altera Stratix III architecture show that the proposed approach reduced the delay by up to 20% under a slight increase in total power dissipation.

Event date： 2011.7

Language：English  

Venue：Athens   Country：Greece  

Analyzing logic masking effects in combinational circuits is an important key to evaluate soft error tolerance of circuits. Logic masking effects can be analyzed exactly with employing fault simulation. The computing complexity of a fault-simulation-based algorithm, however, is proportional to the square of circuit size, which might be unacceptable to achieve a scalable analyzer. On the other hand, a heuristic algorithm AnSER can analyze logic masking effects approximately in runtime proportional to circuit size. AnSER, however, is possible to analyze logic masking effects optimistically especially for circuits protected with spatial redundancy, which might not be suitable for soft error tolerant designs. This paper shows a robust algorithm to analyze logic masking effects pessimistically. Pessimistic analysis is guaranteed with employing the proposed algorithm, while the computing complexity of the proposed algorithm is proportional to circuit size. Experimental results show that the proposed algorithm runs about 91 times faster than a fault-simulation-based exact algorithm with 11.5% overestimate for average susceptibility to errors. For circuits partially protected with spatial redundancy, the proposed algorithm has estimated average susceptibility with 37.9% overestimates on average, while AnSER has estimated average susceptibility with 96% underestimates on average.

Event date： 2011.7

Language：English  

Venue：Athens   Country：Greece  

This paper presents a new 8T (8-transistor) SRAM cell layout mitigating multiple-bit upset (MBU) in a divided wordline structure. Because bitlines along unselected columns are not activated, the divided wordline structure eliminates a half-select problem and achieves low-power operation, which is often preferred for low-power / low-voltage applications. However, the conventional 8T SRAM with the divided wordline structure engenders MBUs because all bits in the same word are physically adjoining. Consequently, error correction coding (ECC) techniques are difficult to apply. This paper presents a new 8T cell layout pattern that separates internal latches in SRAM cells using both an n-well and a p-substrate. We investigated an SEU cross section of nMOS that is 3.5-4.5 times higher than that of pMOS. Using an iRoC TFIT simulator, we confirmed that the proposed 8T cell has better neutron-induced MBU tolerance. The MBU in the proposed 8T SRAM is improved by 90.70% and the MBU soft error rate (SER) is decreased to 3.46 FIT at 0.9 V when ECC is implemented. Additionally, we conducted Synopsys 3-D TCAD simulation, which indicates that the LET threshold (LETth) in single-event upset (SEU) is also improved by 66.47% in the proposed 8T SRAM by a common-mode effect.

Event date： 2010.1

Language：English  

Venue：Taipei   Country：Taiwan, Province of China  

Multi-operand adders usually consist of compression trees which reduce the number of operands per a bit to two, and a carry-propagate adder for the two operands in ASIC implementation. The former part is usually realized using full adders or (3;2) counters like Wallace-trees in ASIC, while adder trees or dedicated hardware are used in FPGA. In this paper, an approach to realize compression trees on FPGAs is proposed. In case of FPGA with m-input LUT, any counters with up to m inputs can be realized with one LUT per an output. Our approach utilizes generalized parallel counters (GPCs) with up to m inputs and synthesizes high-performance compression trees by setting some intermediate height limits in the compression process like Dadda's multipliers. Experimental results show its effectiveness against existing approaches at GPC level and on Altera's Stratix III.

Repository Public URL： http://hdl.handle.net/2324/15428

Event date： 2009.5

Language：English  

Venue：Boston, MA   Country：United States  

Recent technology mappers for LUT based FPGAs employ cut enumeration. Although many cuts are often needed to find good network, enumerating all cuts with large size consumes run-time very much. The number of cuts exponentially increases with the size of cuts, which causes long runtime. Furthermore, an inefficiency of bottom-up merging in existing algorithms makes the run-time much longer. This paper presents a novel cut enumeration. The proposed algorithm is efficient because it enumerates cuts without bottomup merging. Our algorithm has two modes; exhaustive enumeration and partial enumeration. Exhaustive enumeration enumerates all cuts. Partial enumeration enumerates partial cuts with a guarantee that a depth-minimum network can be constructed. The experimental results show that exhaustive enumeration runs about 3 times and 8 times faster than existing bottom-up algorithm [1] [2] for K = 8, 9, respectively. The quality of network are the same. Furthermore, partial enumeration runs about 6 times and 18 times faster than bottom-up algorithm for K = 8, 9, respectively. Area of network derived by the set of cuts enumerated by partial enumeration is only 4 % larger than that derived by exhaustive enumeration on average, and the depth is the same.

Repository Public URL： http://hdl.handle.net/2324/14703

Event date： 2008.10

Language：English  

Venue：Lake Tahoe, CA   Country：United States  

This paper addresses parallel prefix adder synthesis which targets minimization of the total switching activities under bitwise timing constraints. This problem is treated as synthesis of prefix graphs which represent global structures of parallel prefix adders at technology-independent level. An approach for timing-driven area minimization has been proposed which first finds the exact minimum solution on a specific subset of prefix graphs by dynamic programming, then restructures the result for further reduction by removing restriction on the subset. This approach can be applied for switching cost minimization almost directly, though it is not so effective as area minimization in some cases. In this paper, a heuristic is proposed which estimates the effect of the restructuring phase and improve cost calculation fo some specific cases. Through various kinds of experiments, conditions where this approach can be executed effectively is also discussed. & copy; 2008 IEEE.

Event date： 2008.3

Language：English  

Venue：Seoul   Country：Korea, Republic of  

In this paper we present the post-processing algorithm, Cut Substitution, for technology mapping for LUT-based FPGAs to minimize the area under depth minimum constraint. The problem to generate a LUT's network whose area is minimum under depth minimum costraint seems to be as difficult as NP-Hard class problem. Cut Substitution is the process to generate a local optimum solution by eliminating redundant LUTs while the depth of network is maintained. The experiments shows that the proposed method derives the solutions whose area are 9% smaller than the solutions of a previous state-of-the-art, DAOmap on average.

Repository Public URL： http://hdl.handle.net/2324/12504

Event date： 2008.3

Language：English  

Venue：Seoul   Country：Korea, Republic of  

This paper proposes a novel Behavioral Synthesis method that improves performance of synthesized circuits utilizing specialized functional units effectively. Specialized functional units (e.g. Multiply-Accumulator) are designed for specific operation patterns to achieve shorter delay and/or smaller area than cascaded basic functional units. Almost all conventional methods cannot use specialized functional units effectively under a total area constraint because of their less flexibility for resource sharing. The proposed method makes it possible to solve module selection, scheduling, and functional unit allocation problems utilizing specialized functional units in practical time with some heuristics, and to reduce the number of clock cycles under total area and clock cycle time constraints. Experimental results show that the proposed method has achieved up to 35% and on average 14% reduction of the number of cycles with specialized functional units in practical time.

Event date： 2007.3

Language：English  

Venue：Stresa-Lago Maggiore   Country：Italy  

This paper addresses parallel prefix adder synthesis which targets area minimization under given timing constraints. This problem is treated as synthesis of prefix graphs which represent global structures of parallel prefix adders, and a two-folded robust heuristic is proposed. The first process is dynamic programming based area minimization (DPAM), where the search space is limited to a specific subset of the whole set of prefix graphs by imposing some restrictions on structure of prefix graphs, and an exact minimum prefix graph for the limited space can be found efficiently by dynamic programming. The second process is area reduction with re-structuring (ARRS),which removes imposed restrictions on structure, and restructures the result of DPAM for further area reduction. Experimental results show that the size of prefix graph can be reduced by about 10% compared to an existing approach, and area at gate level can also be reduced by more than 30% compared to a commercial tool in some case.

Event date： 2006.11

Language：English  

Venue：Fukuoka   Country：Japan  

An ATPG tool is constructed by many functions which are pattern generation functions, fault simulation functions, static compaction functions, etc. For evaluating new idea of only one subfunction accurately, it is necessary to develop all functions of the ATPG tool. It is a serious problem for evaluating new ideas. Many of efficient techniques like static learning don't satisfy all evaluation standards of ATPG tools (high fault efficiency, short length of test patterns, and short CPU time, etc.). Effectiveness of these efficient techniques is according to the structure of circuits. If ATPG tools aren't practical, these techniques are not accurately evaluated. In FLEETS, practical and open EDA tools include ATPG tool have been developed for evaluating new ideas. The purpose of developing these EDA tools is to provide environment that facilitates evaluating new ideas. An ATPG tool which has flexible interfaces is developed as a part of environment for developing EDA tools. This ATPG tool has been developed for evaluating new ideas. To achieve this propose, new algorithms as well as the existing algorithms have been developed. Flexible command interfaces are designed to facilitate adding new ideas in the future. The command interface has been written in Tcl/TK[2]. Table 1 shows the command interfaces. A flexible interface was added to this ATPG tool to conduct various experiments. One of examples is that relations between order of selecting faults, number of patterns and CPU Time are examined. Another is that correlation of the number of test patterns and processing time to combination of each algorithm of pattern generation, static compaction, and fault simulation is examined. And, relations between results of static learning and pattern generation are examined. This ATPG tool has been written in C language and can be executed on Linux and Solaris. This ATPG tool was evaluated to combinational circuits of ITC99 benchmark circuits [1]. A fault model was the single stuck-at fault model. The ATPG tool was executed on Pentium4 3.05GHz with 1GB Memory running Linux OS. In the result to 21 all circuits, the number of patterns was 776, processing time were 459.3 seconds and fault efficiency were 99.74% on average. Practical and open ATPG tool for evaluating new ideas has been described. New ideas of ATPG tools can be easily evaluated in a short term. One of the problems in the future is to enable an addition of the algorithm by the user. For solving this problem, it will be designed APIs of ATPG tool which is used by users when users will develop the new algorithms.

Event date： 2006.9

Language：English  

Venue：Monterey, CA   Country：United States  

The character projection (CP) is utilized for maskless lithography and is a potential for the future photomask manufacture because the CP lithography can project ICs much faster than point beam projection or variable-shaped beam (VSB) projection. In this paper, we present CP mask optimization for multi-column-cell (MCC) systems, in which column-cells can project patterns in parallel with the CP and the VSB, so that their throughput is maximized. This paper presents an MINLP (mixed integer nonlinear programming) model as well as an MIP (mixed integer programming) model for optimizing a CP mask set of an MCC projection system so that projection time is minimized. The experimental results show that our optimization has achieved 71.3% less projection time for a two-column-cell system than that for a single-column-cell (SCC) system. For the two-column-cell system, it has also achieved 42.6% less projection time than a naive CP mask development approach. The experimental results denote that our optimization achieves projection time reduction more than parallelizing two column-cells by virtually increasing logic cells which are placed on CP masks and decreasing VSB projection.

Event date： 2006.5

Language：English  

Venue：Kos   Country：Greece  

We propose a character size optimization technique to enhance the throughput of maskless lithography as well as photomask manufacture. The number of electron beam shots to draw the patterns of circuits is a dominant factor in the manufacture time and the cost for devices. Our technique is capable of drastically reducing them by optimizing the size of characters, which are the patterns to project and are placed on CP masks. Experimental results show that our technique reduced 72.0% of EB shots in the best case, comparing with the ad hoc character sizing.

Event date： 2006.1

Language：English  

Venue：San Jose, CA   Country：United States  

The character projection is utilized for maskless lithography and is a potential for the future photomask manufacture. The drawback of the character projection is its low throughput and leads to a price rise of ICs. This paper discusses a technology mapping technique for enhancing the throughput of the character projection. The number of EB shots to draw an entire chip determines the fabrication time for the chip. Reduction of the number of EB shots, therefore, increases the throughput of character projection equipment and reduces the cost to produce ICs. Our technology mapping technique aims to reduce the number of EB shots to draw an entire chip for increasing the throughput of character projection equipment. Our technique treats the number of EB shots as an objective to minimize. Comparing with an conventional technology mapping, our technology mapping technique achieved 19.6% reduction of the number of EB shots without any performance degradation of ICs. Moreover, our technology mapping technique achieved 48.8% reduction of the number of EB shots under no performance constraints. Our technique is easy for both IC designers and equipment developers to adopt because it is a software approach with no additional modification on character projection equipment.

Event date： 2005.11

Language：English  

Venue：Tampere   Country：Finland  

We propose a cell library development methodology for throughput enhancement of electron beam direct-write (EBDW) systems. First, an ILP (Integer Linear Programming)-based cell selection is proposed for EBDW systems in which both of the character projection (CP) and the variable shaped beam (VSB) methods are available, in order to minimize the number of electron beam (EB) shots, that is, time to fabricate chips. Secondly, the influence of cell directions on area and delay time of chips is examined. The examination helps to reduce the number of EB shots with a little deterioration of area and delay time because unnecessary directions of cells can be removed to increase the number of cells on a CP aperture mask Finally, a case study is shown in which the numbers of EB shots are examined under several cases.

Event date： 2004.2

Language：English  

Venue：Lafayette, LA   Country：United States  

In testing system-on-a-chip (SOC), external pins for test are getting more and more precious hardware resources because the number of external pins is strongly restricted. Cores, which are basic components to build SOCs, are tested via test access mechanisms (TAMs) such as a test bus architecture. When cores are tested via TAMs, test stimuli and test responses for cores have to be transported over these TAMs. There is often the difference between the numbers of input/output ports of cores and the widths of TAMs. This difference causes the serialization of test patterns. It is probable that some parts of TAMs are unused because of the difference. This is a wasteful usage of TAMs. Test scheduling should be done in order to remove such a wasteful usage of TAMs. In this paper, a novel and practical test architecture optimization is proposed such that test time is minimized with floorplanning constraints abided. In this proposal, the computation time for the optimization can be alleviated by floorplanning manipulation. Several experimental results to this optimization are shown to validate this proposal using a commercial LP solver.

Repository Public URL： http://hdl.handle.net/2324/6093

Event date： 2004.1

Language：English  

Venue：Yokohama   Country：Japan  

In this paper we enhance the performance of multi-cycle path analysis in an industrial setting. Industrial designs are, in general, more complicated, but contain more information than fundamental sequential circuits. We show how such information is used for improving the quality and the efficiency of multi-cycle path analysis. Specifically, we propose local FSM learning to take into account reachability information. We also propose FF enable learning to accelerate multi-cycle path analysis. Experimental results show that our methods can handle large industrial designs with tens of thousands of FFs and detects more multi-cycle paths faster than conventional ones.

Repository Public URL： http://hdl.handle.net/2324/6092

Event date： 2002.12

Language：English  

Venue：Monterey, CA   Country：United States  

This paper presents an algorithm for estimating, in the sense below, the length of a longest path of a given directed acyclic graph (DAG) whose edge lengths are given as random variables with normal distributions. Let F(x) be the distribution function of the length of a longest path of a given DAG. The algorithm computes a normal distribution function F̃(x) such that F̃(x) ≤ F(x) if F(x) ≥ α, given a constant α (0.5 ≤ α < 1.0). We conduct two experiments to demonstrate the accuracy of F̃(x).

Event date： 1996.6

Language：English  

Venue：Las Vegas, NV, USA   Country：Other  

This paper proposes a state reduction algorithm for incompletely specified FSMs. The algorithm is based on iterative improvements. When the number of compatibles is likely to be too large to handle explicitly, they are represented by a BDD. Experimental results are given to demonstrate that the algorithm described here is faster and obtains better solutions than conventional methods.

Event date： 1995.8 - 1995.9

Language：English  

Venue：Chiba, Jpn   Country：Other  

This paper proposes a new implicit algorithm for excluding dominated compatibles. The algorithm utilizes a novel notion of signatures of compatibles to exclude dominated compatibles efficiently. Though this dominance check is weaker than the conventional one, experimental results show that in many cases the number of excluded compatibles is the same as that by class sets. Proposed method computes prime compatibles more efficiently than conventional methods for many tested large ISFSM's.

Event date： 1993.6

Language：English  

Venue：Dallas, TX, USA   Country：Other  

We describe a new, recursive-descent procedure for the computation of the transitive closure of a transition relation. This procedure is the classic binary matrix procedure of [1], adapted to a BDD data structure, We demonstrate its efficacy when compared to standard iterative methods.

Event date： 1992.3

Language：English  

Venue：Amsterdam, Neth   Country：Other  

We have developed multi-level logic minimization programs using Binary Decision Diagram (BDD). Here we present variable ordering methods of BDD. The variable ordering algorithm for two-level circuits is based on cover patterns and selects most binate variables first, and the one for multi-level circuits is based on depth first traverse of circuits. In both cases, the acquired variable orderings are optimized by exchanging a variable with its neighbor in the ordering.

Event date： 1991.11

Language：English  

Venue：Santa Clara, CA, USA   Country：Other  

The authors present a method for multilevel logic minimization which is particularly suitable for the minimization of look-up table type FPGAs (field programmable gate arrays). Given a set of nodes to be minimized, one first calculates sets of supports which are necessary to construct the functions for the given nodes by applying functional reduction. The functional reduction process guarantees that one can get the minimal support for each node. One then makes a covering table for the set of nodes to be minimized so that one can get the minimal supports to cover all the functions for the given set of nodes to be minimized. The authors present a preliminary implementation and its results for ISCAS combinational benchmark circuits combined with MIS2.1 standard script and a Boolean resubstitution minimizer, and show the effectiveness of the presented method.

Event date： 1991.6

Language：English  

Venue：San Francisco, CA, USA   Country：Other  

An algorithm, RENO (resynthesis for network optimization), for the optimization of multilevel combinational networks is presented. In RENO, a given network is minimized for area by optimally resynthesizing each gate, using other existing gates in the network. The resynthesis process is based on a covering-set algorithm, which enables one to resynthesize using complex gates instead of only simple gates (e.g., NAND and NOR), thereby exploring more reconfiguration possibilities. Due to the reconfiguration ability of the RENO algorithm, networks optimized by RENO have good quality, even if no network don't-care is used. The RENO algorithm has been implemented in both cube and shared-OBDD data structures. Experimental results obtained by RENO for benchmark functions and comparison with the optimization algorithm used in MIS 2.2 show that RENO is effective for multilevel network optimization.

Event date： 1990.11

Language：English  

Venue：Santa Clara, CA, USA   Country：Other  

Automatic and semi-automatic verification methods for switch-level circuits are presented. Switch-level circuits with no delay (but with/without charge effects) are automatically verified using a formalism with binary decision diagrams (BDD) and temporal logic. Purely bidirectional transistors, such as those whose signal directions are dynamically determined in operations, are treated in the uniform way as nonbidirectional transistors. In the case of switch-level circuits with arbitrary delays, based on the work by M. E. Leeser (1989), the authors present a semi-automatic verification method which uses a propositional theorem prover using BDD. First some assignments of propositional variables to terms of temporal logic are manually given, and then the automatic theorem prover does verification.

Event date： 1990.11

Language：English  

Venue：Santa Clara, CA, USA   Country：Other  

A method to minimize sequential circuits is presented. It uses permissible functions extended for sequential circuits, and can make use of don't cares derived from network topology. Also, an efficient binary decision diagram (BDD) implementation of the extended permissible functions is presented by introducing edge attributes that indicate time label to the BDD. Circuits including latches can be efficiently minimized with the proposed method.

Event date： 1990.9

Language：English  

Venue：Cambridge, MA, USA   Country：Other  

A Boolean technology mapping with permissible functions is presented. This technique makes use of complementary intermediate logic functions of circuits. Therefore, complementary outputs of ECL gates can be easily handled. High-quality synthesized ECL circuits and CMOS circuits free of logical redundancies are generated. Technology-independent networks are converted into technology-dependent virtual gates network. Virtual gates have an arbitrary number of fan-ins. CMOS virtual networks consist of only NOR and NAND gates, while ECL virtual networks consists of only OR gates (but each gate has complementary outputs). By considering logic function and the device restrictions these virtual gate networks are translated into cell networks using permissible functions.

Event date： 1990.6

Language：English  

Venue：Orlando, FL, USA   Country：Other  

A new Boolean resubstitution technique with permissible functions and ordered binary decision diagrams (OBDDs) is presented. Boolean resubstitution is one technique for multilevel logic optimization. Permissible functions are special don't care sets. The data structure of permissible functions and logic functions at each node in Boolean networks is represented in terms of OBDD. Therefore, logic functions can be flexibly manipulated and rapidly executed. Boolean resubstitution was also applied to a multilevel logic synthesis. Results of experiments employing the improved OBDD operation and Boolean resubstitution techniques are presented.

Event date： 1989.11

Language：English  

Venue：Santa Clara, CA, USA   Country：Other  

A multilevel logic optimizer, which is based on the transduction method, is introduced. The original transduction method is good for optimization, but its calculation time and storage area increase exponentially with the number of inputs because of the use of truth tables. To save CPU time and memory space, the authors implemented this algorithm using ordered binary decision diagrams (OBDD) as the data structure for representing logic functions. Since OBDD does not become as large as other representations, it can handle large circuits without partitioning.

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Number of participants：600

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Number of participants：150

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Number of participants：3,000

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Number of participants：180

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Type：Competition, symposium, etc. 

Number of participants：150

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Type：Competition, symposium, etc. 

Number of participants：600

Type：Competition, symposium, etc. 

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