Language：English   Publishing type：Research paper (international conference proceedings)  

A 10+K qubit Quantum-Classical Interface (QCI) is essential to realize the quantum supremacy. However, it is extremely challenging to architect scalable QCIs due to the complex scalability trade-offs regarding operating temperatures, device and wire technologies, and microarchitecture designs.Therefore, architects need a modeling tool to evaluate various QCI design choices and lead to an optimal scalable QCI architecture.

In this paper, we propose (1) QIsim, an open-source QCI simulation framework, and (2) novel architectural optimizations for designing 10+K qubit QCIs toward quantum supremacy. To achieve the goal, we first implement detailed QCI microarchitectures to model all the existing temperature and technology candidates. Next, based on the microarchitectures,we develop our scalability-analysis tool (QIsim) and thoroughly validate it using previous works, postlayout analyses, and real quantum machine experiments. Finally, we successfully develop our 60,000+ qubit-scale QCI designs by applying eight architectural optimizations driven by QIsim.

DOI： 10.1145/3579371.3589036

Authorship：Lead author   Language：English   Publishing type：Research paper (international conference proceedings)  

10+K qubit quantum computer is essential to achieve a true sense of quantum supremacy. With the recent effort towards the large-scale quantum computer, architects have revealed various scalability issues including the constraints in a quantum control processor, which should be holistically analyzed to design a future scalable control processor. However, it has been impossible to identify and resolve the processor’s scalability bottleneck due to the absence of a reliable tool to explore an extensive design space including microarchitecture, device technology, and operating temperature.

In this paper,we present XQsim, an open-source cross-technology quantum control processor simulator. XQsim can accurately analyze the target control processors’ scalability bottlenecks for various device technology and operating temperature candidates. To achieve the goal, we first fully implement a convincing control processor microarchitecture for the Fault-tolerant Quantum Computer (FTQC) systems. Next, on top of the microarchitecture, we develop an architecture-level control processor simulator (XQsim) and thoroughly validate it with post-layout analysis, timing-accurate RTL simulation, and noisy quantum simulation. Lastly, driven by XQsim, we provide the future directions to design a 10+K qubit quantum control processor with several design guidelines and architecture optimizations. Our case study shows that the final control processor architecture can successfully support ~59K qubits with our operating temperature and technology choices.

DOI： 10.1145/3470496.3527417

DOI： 10.1145/3470496.3527417

Language：English   Publishing type：Research paper (international conference proceedings)  

Cryogenic computing, which runs a computer device at an extremely low temperature, is promising thanks to its significant reduction of wire resistance as well as leakage current. Recent studies on cryogenic computing have focused on various architectural units including the main memory, cache, and CPU core running at 77K. However, little research has been conducted to fully exploit the fast cryogenic wires, even though the slow wires are becoming more serious performance bottleneck in modern processors.

In this paper, we propose a CPU microarchitecture which extensively exploits the fast wires at 77K. For this goal, we first introduce our validated cryogenic-performance models for the CPU pipeline and network on chip (NoC), whose performance can be significantly limited by the slow wires. Next, based on the analysis with the models, we architect CryoSP and CryoBus as our pipeline and NoC designs to fully exploit the fast wires. Our evaluation shows that our cryogenic computer equipped with both microarchitectures achieves 3.82 times higher system-level performance compared to the conventional computer system thanks to the 96% higher clock frequency of CryoSP and five times lower NoC latency of CryoBus.

DOI： 10.1145/3503222.3507749

Language：English   Publishing type：Research paper (international conference proceedings)  

Cryogenic computing, which runs a computer device at an extremely low temperature, is highly promising thanks to the significant reduction of the wire latency and leakage current. A recently proposed cryogenic DRAM design achieved the promising performance improvement, but it also reveals that it must reduce the DRAM’s dynamic power to overcome the huge cooling cost at 77K. Therefore, researchers now target to reduce the cryogenic DRAM’s refresh power by utilizing its significantly increased retention time driven by the reduced leakage current. To achieve the goal, however, architects should first answer many fundamental questions regarding the reliability and then design a refresh-free, but still robust cryogenic DRAM by utilizing the analysis result.

In this work, we propose a near refresh-free, but robust cryogenic DRAM (NRFC-DRAM), which can almost eliminate its refresh overhead while ensuring reliable operations at 77K. For the purpose, we first evaluate various DRAM samples of multiple vendors by conducting a thorough analysis to accurately estimate the cryogenic DRAM’s retention time and reliability. Our analysis identifies a new critical challenge such that reducing DRAM’s refresh rate can make the memory highly unreliable because normal memory operations can now appear as rowhammer attacks at 77K. Therefore, NRFC DRAM requires a cost-effective, cryogenic-friendly protection mechanism against the new row-hammer-like “faults” at 77K.

To resolve the challenge, we present CryoGuard, our cryogenicfriendly row-hammer protection method to ensure the NRFCDRAM’s reliable operations at 77K. With CryoGuard applied, NRFC-DRAM reduces the overall power consumption by 25.9% even with its cooling cost included, whereas the existing cryogenic DRAM fails to reduce the power consumption.

DOI： 10.1109/ISCA52012.2021.00056

Authorship：Lead author   Language：English   Publishing type：Research paper (scientific journal)  

The superconductor single-flux-quantum (SFQ) logic family has been recognized as a promising solution for the post-Moore era, thanks to the ultrafast and lowpower switching characteristics of superconductor devices. Researchers have made tremendous efforts in various aspects, especially in device and circuit design. However, there has been little progress in designing a convincing SFQbased architectural unit due to a lack of understanding about its potentials and limitations at the architectural level. This article provides the design principles for SFQ-based architectural units with an extremely high-performance neural processing unit (NPU). To achieve our goal, we developed and validated a simulation framework to identify critical architectural bottlenecks in designing a performance-effective SFQ-based NPU. We propose SuperNPU, which outperforms a conventional state-of-the-art NPU by 23 times in terms of computing performance and 1.23 times in power efficiency even with the cooling cost of the 4K environment.

DOI： 10.1109/MM.2021.3070488

Authorship：Lead author   Language：English   Publishing type：Research paper (scientific journal)  

Cryogenic computing can achieve high performance and power efficiency by dramatically reducing the device’s leakage power and wire resistance at low temperatures. Recent advances in cryogenic computing focus on developing cryogenic-optimal cache and memory devices to overcome memory capacity, latency, and power walls. However, little research has been conducted to develop a cryogenic-optimal core architecture even with its high potentials in performance, power, and area efficiency. In this article, we first develop CryoCore-Model, a cryogenic processor modeling framework that can accurately estimate the maximum clock frequency of processor models running at 77 K. Next, driven by the modeling tool, we design CryoCore, a 77 K-optimal core microarchitecture to maximize the core’s performance and area efficiency while minimizing the cooling cost. The proposed cryogenic processor architecture, in this article, achieves the large performance improvement and power reduction and, thus, contributes to the future of high-performance and power-efficient computer systems.

DOI： 10.1109/MM.2021.3070133

Authorship：Lead author   Language：English   Publishing type：Research paper (international conference proceedings)  

DOI： 10.1109/MICRO50266.2020.00018

Language：English   Publishing type：Research paper (international conference proceedings)  

DOI： 10.1109/ISCA45697.2020.00037

Language：English   Publishing type：Research paper (international conference proceedings)  

DOI： 10.1145/3373376.3378513

Authorship：Lead author   Language：English   Publishing type：Research paper (international conference proceedings)  

DOI： 10.1145/3307650.3322219

Event date： 2021.6

Language：English   Presentation type：Oral presentation (general)  

Venue：online  

DOI： 10.1109/ISCA52012.2021.00056

Event date： 2020.10

Language：English   Presentation type：Oral presentation (general)  

Venue：online  

DOI： 10.1109/MICRO50266.2020.00018

Event date： 2020.5 - 2020.6

Language：English   Presentation type：Oral presentation (general)  

Venue：online  

DOI： 10.1109/ISCA45697.2020.00037

Event date： 2020.3

Language：English   Presentation type：Oral presentation (general)  

Venue：online  

DOI： 10.1145/3373376.3378513

Event date： 2019.6

Language：English   Presentation type：Oral presentation (general)  

Venue：Phoenix, Arizona   Country：United States  

DOI： 10.1145/3307650.3322219

Event date： 2025.6

Language：English   Presentation type：Oral presentation (keynote)  

Venue：Prague   Country：Czech Republic  

Quantum computing has emerged as a promising candidate for innovating various areas with a quantum nature. However, practical applications require thousands of noiseless ideal qubits, while real-world physical qubits are very fragile. To bridge this gap, we eventually need an error-corrected quantum computer with millions of physical qubits.

In this presentation, we introduced a computer architect's approach to developing a practical quantum computer system. Next, as an example of our approach, we shared our recent research on quantum computer architecture, published in top-tier architecture conferences. Lastly, we discussed a computer architect's perspective for pacing with rapidly evolving quantum computing technologies.

Event date： 2024.10

Language：English   Presentation type：Oral presentation (invited, special)  

Venue：Osaka   Country：Japan  

Event date： 2024.5

Language：English   Presentation type：Oral presentation (invited, special)  

Venue：Fukuoka   Country：Japan  

Event date： 2022.9

Language：English   Presentation type：Oral presentation (invited, special)  

Venue：Kyoto   Country：Japan