Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Publisher：Materials Science in Semiconductor Processing  

Germanium is an attractive material for advanced devices such as high speed transistors and high efficiency optical devices. To realize the high performance operation, low resistive contacts to Ge are required. However, the Fermi level in Ge at metal/Ge contacts is often pinned near the valance band edge. This Fermi level pinning generates high Schottky barrier heights at metal/Ge contacts regardless the work function of the metals, which results in low resistive contacts to p-type Ge but high resistive contacts to n-type Ge. Thus, a technique for modulating the Schottky barrier heights at metal/Ge contacts is desired. For this purpose, effects of surface treatments of Ge using phosphoric acid coating and excimer laser annealing (LA) were investigated. After LA without phosphoric acid coating, the reverse current of the Al/n-type Ge contacts is increased by an order of magnitude. On the other hand, the reverse current is significantly increased by three orders of magnitude after LA with phosphoric acid coating. Here, the Schottky barrier heights are decreased from 0.56 to 0.50 eV and from 0.59 to 0.49 eV after LA for samples without and with phosphoric acid coating, respectively. These phenomena are attributed to formation of very thin GeOx surface layers and very shallow doped layers having very high P concentrations, respectively. This technique is useful for modulation of the Fermi level pinning for metal/Ge contacts with the low thermal budget.

DOI： 10.1016/j.mssp.2023.107433

Web of Science

Scopus

Publisher：Materials Science in Semiconductor Processing  

DOI： 10.1016/j.mssp.2023.107386

Web of Science

Scopus

Publisher：30th International Workshop on Active-Matrix Flatpanel Displays and Devices: TFT Technologies and FPD Materials, AM-FPD 2023 - Proceedings  

To achieve high performance of advanced devices, a doping process with low thermal budget is required. For this purpose, excimer laser doping into Si is investigated. By using ultra-thin Al films deposited on n-type Si substrates as diffusion source, p-type regions are formed on the surfaces of the n-type Si substrates after laser irradiation. The electrical properties and surface morphologies of the samples are investigated as a function of the laser fluence. PN junctions showing good rectifying characteristics without surface roughening are obtained by optimization of the laser fluence. This technique will be useful to realize next-generation high-performance devices with low thermal budget.

Scopus

Publisher：30th International Workshop on Active-Matrix Flatpanel Displays and Devices: TFT Technologies and FPD Materials, AM-FPD 2023 - Proceedings  

Solid-phase crystallization of Sn-doped Si thin films (Sn concentration: 1%, thickness: ≤ 30 nm) on insulator has been investigated. After annealing of the Sn-doped Si thin films at temperatures below 600oC, domain structures were observed. The growth velocities of the domains decreased with decreasing film thickness. However, they are significantly higher compared with the reported values of the solid-phase epitaxy of Si. The crystal structures of the grown films also depended on the film thickness, and larger grain sizes are obtained for thicker films.

Scopus

Publisher：30th International Workshop on Active-Matrix Flatpanel Displays and Devices: TFT Technologies and FPD Materials, AM-FPD 2023 - Proceedings  

A technique to obtain high carrier mobility of Sn-doped Ge thin-films (thickness: ≤20 nm) on insulators is proposed. In a conventional approach, the grain sizes of Sn-doped poly-Ge films grown by solid-phase crystallization decrease with decreasing thickness. This significantly deteriorates the carrier mobility. To solve this problem, thinning of thick Ge films having large grain sizes is investigated. Moreover, to eliminate the crystal defects, post-Annealing is examined. This achieves high carrier mobility (~200 cm2/Vs) even for thin-films (thickness: 20 nm). A good transistor operation is demonstrated using the thinned Ge films. This technique will be useful to realize advanced thin-film transistors for next-generation electronics.

Scopus

Publisher：Journal of Applied Physics  

Rapid-thermal annealing (RTA) of InSb precursor films, deposited by sputtering using an Ar plasma at room temperature, has been investigated to achieve high carrier mobility on low-cost glass substrates. Although InSb films containing residual Ar (∼1%) were partially lost by evaporation during RTA, such evaporation during RTA is suppressed by reducing the residual Ar to ∼0.3%. The crystallinity of the films is significantly increased by RTA at temperatures above 400 °C. The electron mobilities of the films increase with increasing RTA temperature up to 490 °C, showing the maximum values (9000-10 000 cm2 V-1 s-1) at 490 °C, and then, the mobilities decrease at RTA temperatures above 490 °C. The mobilities of 9000-10 000 cm2 V-1 s-1 are obtained for films with a wide range of thickness (300-1000 nm) grown at 490 °C. Detailed analysis indicated that the high carrier mobilities are realized by preferentially (111)-oriented large crystal domains (diameter: >100 μm), obtained by the regrowth of randomly oriented small grains, together with a low barrier height (16 meV) at the sub-domain boundaries (twin boundaries) in the large domains. The RTA after the sputtering technique will facilitate high-performance InSb-based devices with low production costs.

DOI： 10.1063/5.0105045

Web of Science

Scopus

Language：English  

Rapid-thermal annealing (RTA) of InSb precursor films, deposited by sputtering using an Ar plasma at room temperature, has been investigated to achieve high carrier mobility on low-cost glass substrates. Although InSb films containing residual Ar (∼1%) were partially lost by evaporation during RTA, such evaporation during RTA is suppressed by reducing the residual Ar to ∼0.3%. The crystallinity of the films is significantly increased by RTA at temperatures above 400 °C. The electron mobilities of the films increase with increasing RTA temperature up to 490 °C, showing the maximum values (9000–10 000 cm^2 V^<−1> s^<−1>) at 490 °C, and then, the mobilities decrease at RTA temperatures above 490 °C. The mobilities of 9000–10 000 cm^2 V^<−1> s^<−1> are obtained for films with a wide range of thickness (300–1000 nm) grown at 490 °C. Detailed analysis indicated that the high carrier mobilities are realized by preferentially (111)-oriented large crystal domains (diameter: >100 μm), obtained by the regrowth of randomly oriented small grains, together with a low barrier height (16 meV) at the sub-domain boundaries (twin boundaries) in the large domains. The RTA after the sputtering technique will facilitate high-performance InSb-based devices with low production costs.

CiNii Research

Publisher：Proceedings of the International Display Workshops  

High-speed fully-depleted thin-film transistors (TFTs) are required for next-generation electronics, such as three-dimensional large-scale integrated circuits and advanced system-in-displays. For this purpose, a novel growth technique, i.e., interface-modulated solid-phase crystallization, of Sn-doped Ge has been developed. This achieves high carrier mobility (~100 cm2/Vs) of ultrathin films (20 nm) on insulators.

Scopus

Web of Science

Publisher：Proceedings of AM-FPD 2022 - 29th International Workshop on Active-Matrix Flatpanel Displays and Devices: TFT Technologies and FPD Materials  

Thin poly-Ge films (thickness: ≤ 50 nm) having high carrier mobility are required for advanced thin-film devices. However, carrier mobility of poly-Ge films obtained by conventional solid-phase crystallization (SPC) significantly decreases with decreasing thickness below 50 nm. To solve this problem, we develop an interface-modulated SPC of Sn-doped Ge combined with a-Si capping. In the present study, we investigate growth characteristics of a-Si capped Sn-doped Ge films on insulator. It is clarified that a-Si capping enhances SPC of Sn-doped Ge films and results in large crystal grains, which improves the carrier mobility of Sn-doped Ge thin films. This technique will be useful to realize advanced thin-film devices for next-generation electronics.

DOI： 10.23919/AM-FPD54920.2022.9851292

Scopus

Language：English   Publishing type：Research paper (scientific journal)  

DOI： https://doi.org/10.1109/JEDS.2019.2956991

Other Link： https://doi.org/10.1109/JEDS.2019.2956991

Language：English   Publishing type：Research paper (scientific journal)  

DOI： http://dx.doi.org/10.1149/2.0281910jss

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.23919/AM-FPD.2019.8830601

Language：English   Publishing type：Research paper (scientific journal)  

DOI： https://doi.org/10.1063/1.5087235

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1117/12.2509141

Language：English   Publishing type：Research paper (scientific journal)  

Low-temperature (≤250°C) formation of Sn-doped Ge (GeSn) (substitutional Sn concentration: 2-3%) on insulator is desired to realize flexible electronics, where high-speed thin-film transistors are integrated on flexible plastic-substrates (softening temperature: ∼300°C). To achieve this, gold-induced lateral crystallization of amorphous GeSn (a-GeSn) is investigated. Here, a-GeSn (Sn concentration: 0%-20%) on insulator structures, having Au-island patterns, were annealed. For initial Sn concentrations of 0%-5%, high-speed lateral crystallization proceeds around Au-patterns, and large grown regions (∼5-20 μm) are obtained by low-temperature short-time annealing (150°C-250°C, 10 min). However, bottom regions of GeSn are not crystallized at 150°C-200°C, while the whole films including bottom regions are crystallized at 250°C. These phenomena are caused by the following temperature-dependent growth mechanisms. At 150°C-200°C, Au atoms are supplied into surface-regions of a-GeSn films from Au-islands by surface-diffusion, resulting in crystallization of only surface-regions. On the other hand, at 250°C, layer-exchange of Au/GeSn occurs, which increases supply channel of Au for diffusion. This results in complete crystallization of GeSn to the bottom. Substitutional Sn concentrations in grown layers are increased with increasing annealing temperature. As a result, GeSn films (substitutional Sn concentration: ∼3%) are obtained at ∼250°C.

DOI： 10.1149/2.0281910jss

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.23919/AM-FPD.2018.8437343

Language：English   Publishing type：Research paper (scientific journal)  

The authors wish to retract their publication.1 This action is taken because an error in film thicknesses used in determining the mobilities reported in the manuscript resulted in mobility overestimates by factors of two, three, and four for the films with thicknesses of 100, 150, and 200 nm, respectively. Since the high value of the mobility was the central result of the manuscript and drove much of the discussion, the authors are retracting the publication. The authors sincerely apologize for any inconvenience this mistake may have caused.

DOI： 10.1063/1.5046407

Language：English   Publishing type：Research paper (scientific journal)  

High-speed thin-film transistors (TFTs) are required to develop the next generation of electronics, such as three-dimensional large-scale integrated circuits and advanced system-in-displays. For this purpose, high-carrier-mobility semiconductor films on insulator structures should be fabricated with low-temperature processing conditions (≤500 °C). To achieve this, we investigate solid-phase crystallization of amorphous-GeSn (a-GeSn) films (Sn concentration: 2% and thickness: 50-200 nm) on insulating substrates, where thin a-Si under-layers (thickness: 0-20 nm) are introduced between a-GeSn films and insulating substrates. The GeSn films are polycrystallized by annealing (450 °C, 20 h) for all samples irrespective of a-GeSn and a-Si thickness conditions, while the Si films remain amorphous. Analysis of crystal structures of GeSn films (thickness: 50 nm) reveals that grain sizes decrease from ∼10 μm to 2-3 μm by the introduction of a-Si under-layers (thickness: 3-20 nm). This phenomenon is attributed to the change in dominant nucleation sites from the interface to the bulk, which significantly decreases grain-boundary scattering of carriers through a decrease in the barrier heights at grain boundaries. Bulk-nucleation further becomes dominant by increasing the GeSn film thickness. As a result, a high carrier mobility of ∼550 cm²/V s is realized for GeSn films (thickness: 100 nm) grown with a-Si under-layers. This mobility is the largest among ever reported data for Ge and GeSn grown on an insulator. This technique will facilitate realization of high-speed TFTs for use in the next generation of electronics.

DOI： 10.1063/1.5024307

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (other academic)  

Language：English   Publishing type：Research paper (other academic)  

Effects of film-Thickness on substitutional Sn concentration in GeSn films on insulator grown by combination of laser irradiation and subsequent thermal annealing are investigated. Here, the laser fluence is chosen as weak, which is below the critical fluence for crystallization of GeSn. It is clarified that for samples irradiated with low fluence, complete crystallization of a-Ge0.8Sn0.2 films (thickness: 50200 nm) is achieved by subsequent thermal annealing at 180°C for 5 h without incubation time. The substitutional Sn concentrations increase with decreasing film thickness. As a result, very high substitutional Sn concentration of ∼15%, which corresponds to high-substitution fraction of ∼75% of total Sn atoms, is achieved for film thickness of 50 nm. This technique will be useful to realize next-generation high performance devices on flexible insulating substrates.

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.23919/IWJT.2017.7966503

Language：English   Publishing type：Research paper (other academic)  

Low-temperature (≤200°C) formation of GeSn (substitutional Sn concentration: >8%) films on insulator is desired to realize high-speed thin film transistors (TFTs) and high-efficiency optical devices on flexible plastic substrates (softening temperature: ∼200°C). This is because GeSn (substitutional Sn concentration: >8%) has higher carrier mobility than Si and Ge due to the direct-transition energy band structure with smaller effective mass of carriers.

DOI： 10.23919/IWJT.2017.7966502

Language：English  

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1002/sdtp.11659

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1063/1.4971825

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1063/1.4971825

Language：English  

Language：English  

Language：English  

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1016/j.matlet.2016.05.007

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1109/AM-FPD.2016.7543662

Language：English   Publishing type：Research paper (scientific journal)  

DOI： dx.doi.org/10.1063/1.4955059

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1016/j.matlet.2016.01.056

Language：English  

DOI： dx.doi.org/10.1016/j.tsf.2015.10.057

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.7567/JJAP.55.03CB01

Language：English   Publishing type：Research paper (scientific journal)  

Low-temperature (≤ 300 °C) formation of orientation-controlled large-grain (≥ 10 μm) Ge-rich (≥ 50%) SiGe crystals on insulator are realized by the gold-induced layer-exchange technique. Stacked structures of a-Si_{1 - x}Ge_x (0 ≤ x ≤ 1)/Au/SiO₂ are employed as starting materials. Here, thin-Al₂O₃ layers are introduced as diffusion barrier at a-SiGe/Au interfaces to suppress random bulk-nucleation and make (111)-oriented interface-nucleation on SiO₂ dominant. For samples with Ge fraction of 80%-100%, (111)-oriented large-grains (≥ 10 μm) are obtained through layer-exchange during annealing at 250 °C. On the other hand, layer-exchange for Ge fraction of 50% does not proceed at 250 °C. This phenomenon is attributed to retardation of lateral growth by introduction of Si. To enhance lateral growth, increase of annealing temperature is examined. As a result, (111)-oriented large-grains (≥ 10 μm) are realized for SiGe with Ge fraction of 50%-100%, having uniform composition profiles, by annealing at 300 °C. This technique is very useful to realize high-performance flexible electronics, employing plastic substrates (softening temperature: ∼350 °C).

DOI： 10.1016/j.tsf.2015.10.057

Language：English   Publishing type：Research paper (scientific journal)  

GeSn with a high substitutional Sn concentration (> 7%) is an attractive direct band gap material for high-efficiency photodevices that can be merged with large-scale integrated circuits (LSIs). To achieve GeSn with high Sn concentration, low-temperature solid-phase epitaxy using amorphous-GeSn (a-GeSn) (Sn concentration: 10%-36%)/crystal-Ge (c-Ge) stacked structures was investigated. Solid-phase growth of GeSn was enhanced as Sn concentration was increased, which enabled epitaxial growth at very low temperature (150-200 °C). Interestingly, concentrations of substitutional Sn increased with decreasing growth temperature. As a result, epitaxial growth of GeSn with substitutional Sn concentrations of ~ 8% was achieved by decreasing the growth temperature to 150 °C using a-GeSn (Sn concentration: 36%)/c-Ge stacked structures. This technique is expected to be useful to realize multi-function LSIs, where high-efficiency photodevices are integrated with transistors.

DOI： 10.1016/j.tsf.2015.09.069

Language：English  

DOI： 10.1016/j.tsf.2015.09.069

Language：English  

Language：Others   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1149/07510.0095ecst

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1149/2.0161603jss

Language：English  

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1149/07510.0109ecst

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1149/07510.0105ecst

Language：English  

Language：English   Publishing type：Research paper (scientific journal)  

To realize next-generation flexible thin-film devices, solid-phase crystallization (SPC) of amorphous germanium tin (GeSn) films on insulating substrates combined with seeds formed by laser annealing (LA) has been investigated. This technique enables the crystallization of GeSn at controlled positions at low temperature (∼180°C) due to the determination of the starting points of crystallization by LA seeding and Sn-induced SPC enhancement. The GeSn crystals grown by SPC from LA seeds showed abnormal lateral profiles of substitutional Sn concentration. These lateral profiles are caused by the annealing time after crystallization being a function of distance from the LA seeds. This observation of a post-annealing effect also indicates that GeSn with a substitutional Sn concentration of up to ∼10% possesses high thermal stability. These results will facilitate the fabrication of next-generation thin-film devices on flexible plastic substrates with low softening temperatures (∼250°C).

DOI： 10.1063/1.4939109

Language：English  

レーザアニール法によるSn溶融シード形成技術とGeSn固相成長技術を融合し、絶縁膜上における大面積GeSn結晶の低温成長を実現。次世代フレキシブル・エレクトロニクスの実現を加速する重要な成果である。

Language：English  

DOI： 10.1063/1.4929878

Language：English  

Language：English   Publishing type：Research paper (scientific journal)  

Ultra-low temperature (≤300 °C) growth of Ge-rich SiGe on Si substrates is strongly desired to realize advanced electronic and optical devices, which can be merged onto Si large-scale integrated circuits (LSI). To achieve this, annealing characteristics of a-GeSn/c-Si structures are investigated under wide ranges of the initial Sn concentrations (0%-26%) and annealing conditions (300-1000 °C, 1 s-48 h). Epitaxial growth triggered by SiGe mixing is observed after annealing, where the annealing temperatures necessary for epitaxial growth significantly decrease with increasing initial Sn concentration and/or annealing time. As a result, Ge-rich (∼80%) SiGe layers with Sn concentrations of ∼2% are realized by ultra-low temperature annealing (300 °C, 48 h) for a sample with the initial Sn concentration of 26%. The annealing temperature (300 °C) is in the solid-liquid coexisting temperature region of the phase diagram for Ge-Sn system. From detailed analysis of crystallization characteristics and composition profiles in grown layers, it is suggested that SiGe mixing is generated by a liquid-phase reaction even at ultra-low temperatures far below the melting temperature of a-GeSn. This ultra-low-temperature growth technique of Ge-rich SiGe on Si substrates is expected to be useful to realize next-generation LSI, where various multi-functional devices are integrated on Si substrates.

DOI： 10.1063/1.4929878

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1109/AM-FPD.2015.7173225

Language：English  

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1063/1.4922266

Language：English   Publishing type：Research paper (other academic)  

A low-temperature (≤300°C) growth technique of quasi-single crystal, i.e., orientation-controlled large-grain (≥10 μm), Ge-related semiconductors, on insulator is desired for realization of advanced flexible electronics. To achieve this, we have developed the gold-induced layer-exchange crystallization technique using a-SiGe/Au stacked structures. By introduction of a diffusion barrier with appropriate thickness into the a-SiGe/Au interface, (111)-oriented quasi-single crystal SiGe is achieved on insulating substrates at low temperatures (∼300°C). Based on these results, this technique is developed to form quasi-single crystal Ge on flexible plastic sheets. The grown layers have high carrier mobility, because residual Au hardly deteriorates the electrical properties of grown layers due to the low solubility of Au in Ge. This technique will facilitate the realization of advanced flexible electronics.

DOI： 10.1149/06910.0021ecst

Language：English   Publishing type：Research paper (other academic)  

Solid-phase crystallization (SPC) of amorphous-GeSn (a-GeSn) films on insulating substrates has been developed combining with laser-anneal seeding, to realize next generation thin-film devices. By this technique, we have realized crystallization of GeSn (>10%) at low temperatures (∼180°C), which is applicable to flexible thin-film devices on low cost plastic substrates with low softening temperatures (∼200°C). In addition, the starting point of crystallization can be controlled by seeding, which is a big advantage in circuit designing.

DOI： 10.1149/06905.0301ecst

Language：English   Publishing type：Research paper (other academic)  

To realize high-speed thin film transistors, we investigated formation of Ge_1-xSn_x (0蠆x蠆0.2) crystals on quartz by pulsed laser annealing. The process-window necessary for crystallization was found to be significantly expanded by introducing Sn, i.e., 16 mJ/cm² for Ge, ∼130 mJ/cm² for GeSn. Moreover, Ge_0.8Sn_0.2 samples had high substitutional Sn concentration (∼7%) after the growth. These results are expected to be useful to realize highspeed thin film transistors and multi-functional devices.

DOI： 10.1149/06905.0297ecst

Language：English   Publishing type：Research paper (scientific journal)  

Low-temperature (≤250°C) solid-phase crystallization of amorphous-GeSn films (Sn-concentration: 20%-30%, thickness: 30-100 nm) on insulating-substrates are investigated. As a result, we have realized high growth-rate (∼13 μm/h) for samples (film-thickness: 100 nm, initial Sn-concentration: 30%) at surprisingly low-temperature (150°C), which is very useful to realize flexible thin-film transistors. During this study, we encountered interesting phenomena that growth rates significantly decrease with decreasing filmthickness. In addition, substitutional Sn-concentrations in grown layers increased with decreasing film thickness. These phenomena are attributed to change in bond arrangement processes caused by interface. This technique is expected to facilitate next generation flexible thin-film transistors.

DOI： 10.1149/2.0021512ssl

Language：English   Publishing type：Research paper (scientific journal)  

DOI： doi.org/10.1063/1.4902344

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1063/1.4902344

Language：English   Publishing type：Research paper (scientific journal)  

DOI： doi.org/10.1063/1.4901262

Language：English   Publishing type：Research paper (scientific journal)  

DOI： doi: 10.1063/1.4895512

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1063/1.4895512

Language：English  

DOI： 10.1149/2.0011411jss

Language：English   Publishing type：Research paper (scientific journal)  

フレキシブルなプラスチックシート上に、方位制御された大粒径Ge結晶を実現。電気特性を評価し、高いキャリヤ移動度を実証。プラスチック上に多機能を有する異種デバイスを混載する基盤技術の創出であり、次世代エレクトロニクスの実現を加速する重要な成果である。

DOI： http://dx.doi.org/10.1063/1.4885716

Language：English   Publishing type：Research paper (scientific journal)  

High-carrier-mobility semiconductors on flexible-plastic are essential to realize flexible electronics, for this purpose, electrical properties of orientation-controlled large-grain Cie crystals on flexible-plastic dircctly formed by nucleation-controlled gold-induced-crystallization (GIC) are examined, and compared with those obtained by aluminum-induced-crystallization (AIC). The Ge crystals show p- Type conductions. Here, hole concentrations are 2.2 x10¹⁷ and 5.8 x 10²⁰cm ³ for GIC-Ge and AIC-Ge, respectively, which are explained on the basis of the solubility of Au and AL in Ge. Thanks to the low hole concentration, GIC-Ge shows high hole mobility (160cm²V^-1 'S^-1') compared with AIC-Ge (37cm²V^-1 'S^-1'). These demonstrate significant advantage of GIC to realize high-performance flexible-electronics.

DOI： 10.1063/1.4885716

Language：English  

DOI： 10.1016/j.tsf.2013.08.123

Language：Japanese   Publishing type：Research paper (scientific journal)  

Low-temperature (≤250℃) formation technique of orientation-controlled large-grain Ge thin films on insulator is desirable for realization of advanced flexible electronics. To achieve this, the Au-induced crystallization technique combined with inter-diffusion-control and interface-energy-modulation techniques has been investigated. Consequently, selective formation of (100) or (111)-oriented large-grain (>20 μm) Ge crystals on insulator have been realized. Moreover, formation of (111)-oriented large-grain Ge crystals directly on plastic substrates is demonstrated. This technique facilitates realization of future flexible electronics.

Language：Japanese   Publishing type：Research paper (scientific journal)  

Low-temperature (≤250℃) formation technique of orientation-controlled large-grain Ge thin films on insulator is desirable for realization of advanced flexible electronics. To achieve this, the Au-induced crystallization technique combined with inter-diffusion-control and interface-energy-modulation techniques has been investigated. Consequently, selective formation of (100) or (111)-oriented large-grain (>20 μm) Ge crystals on insulator have been realized. Moreover, formation of (111)-oriented large-grain Ge crystals directly on plastic substrates is demonstrated. This technique facilitates realization of future flexible electronics.

Language：English   Publishing type：Research paper (scientific journal)  

Low-temperature formation (∼ 150 °C) of Ge films on insulator is investigated for realization of advanced flexible devices. We propose utilization of Sn as catalyst to enhance the crystallization at low-temperatures. By annealing (150-200 °C) of a-Ge/Sn stacked structures formed on insulators, the composition distributions of Ge/Sn layers are inverted, and Sn/poly-Ge stacked structures are obtained. The results demonstrate that the crystallization occurs at 150 °C, which is slightly below the eutectic temperatures. This Sn-induced crystallization technique is useful to obtain poly-Ge on low-cost flexible substrates (softening temperature: ∼ 200 °C).

DOI： 10.1016/j.tsf.2013.08.123

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1016/j.tsf.2013.08.035

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1016/j.tsf.2013.08.129

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1016/j.tsf.2013.08.127

Language：English  

DOI： 10.1016/j.tsf.2013.08.035

Language：English  

DOI： 10.1016/j.tsf.2013.08.127

Language：English  

DOI： 10.1016/j.tsf.2013.08.129

Language：English  

DOI： 10.1149/2.003405ssl

Language：English  

Language：English  

Language：English  

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.7567/JJAP.53.020302

Language：English   Publishing type：Research paper (scientific journal)  

不定型なプラスチック基板上における方位制御された大粒径Ge結晶の低温成長を実現。フレキシブルなプラスチック上に多機能を有する異種デバイスを混載する基盤技術の創出であり、次世代エレクトロニクスの実現を加速する重要な成果である。

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1109/ISTDM.2014.6874633

Language：English   Publishing type：Research paper (other academic)  

To develop a new low-temperature crystallization technique, annealing characteristics of a-GeSn/Si(100) structures are investigated. It is revealed that epitaxial growth accompanying Si-Ge mixing is generated at temperatures in the liquid-solid coexisting region of the Ge-Sn system. The annealing temperature necessary for epitaxial growth is significantly decreased by increasing annealing time and/or Sn concentration. Consequently, epitaxial growth at 300°C becomes possible. These findings are expected to be useful to realize next-generation large-scale integrated circuits, where various multi-functional devices are integrated.

DOI： 10.4028/www.scientific.net/AMM.481.137

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1149/2.003405ssl

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1109/AM-FPD.2014.6867200

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1149/06103.0097ecst

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.4028/www.scientific.net/AMM.481.27

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1109/ISTDM.2014.6874683

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1063/1.4901262

Language：Others   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1149/2.0011411jss

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.3390/ma7021409

Language：English  

DOI： 10.1149/2.005303jss

Language：English  

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1149/2.005303jss

Language：English   Publishing type：Research paper (scientific journal)  

不定型な絶縁基板上における方位制御された大粒径Ge結晶の低温成長を実現。プラスチック上に多機能を有する異種デバイスを混載する基盤技術の創出であり、次世代エレクトロニクスの実現を加速する重要な成果である。

DOI： http://dx.doi.org/10.1063/1.4819015

Language：English   Publishing type：Research paper (scientific journal)  

Selective formation of Ge(100) and (111) on amorphous-insulator at low-temperatures (∼250 °C) is realized through gold-induced- crystallization using a-Ge/Au/SiO₂ stacked-structures by combining interface-energy-modulation of substrates. Introduction of thin-Al ₂O₃ layers (∼7 nm thickness) at a-Ge/Au interfaces enables large-grain (≥20 μm) Ge(111) formation, which is speculated to be due to suppression of random bulk-nucleation and domination of (111)-oriented interface-nucleation on SiO₂. To examine this speculation, Al ₂O₃-covered substrates are employed. This results in formation of Ge(100), due to energetically favorable (100)-oriented interface-nucleation on Al₂O₃. Consequently, large-grain (≥20 μm) Ge(100) and (111) are achieved on amorphous-insulators at 250 °C. This technique is very useful to realize flexible-electronics.

DOI： 10.1063/1.4819015

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1149/2.008309ssl

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1149/2.002307ssl

Language：English  

DOI： 10.1149/2.008309ssl

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1016/j.tsf.2013.02.129

Language：English  

DOI： 10.1149/2.002307ssl

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Language：Japanese  

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1063/1.4794409

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1149/05809.0179ecst

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1149/05809.0213ecst

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1149/05809.0257ecst

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.3390/ma6115047

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1109/IWJT.2013.6644498

Language：English   Publishing type：Research paper (scientific journal)  

Orientation-controlled Si_1-xGe_x (0≤ x≤1) films on insulating substrates are essential to achieve high-efficiency solar-cells and highspeed thin-film-transistors. We investigate Al-induced crystallization of amorphous-Si_1-xGe_x/Al-oxide/Al/quartz stacked-structures as a function of Ge-fraction, air-exposure time of Al surfaces, and thicknesses of Al and SiGe films. By tuning interfacial Al-oxide layer thickness, which is controlled by air-exposure time, (100) or (111) Si_1-xGe_x (x < 0.2) layers are selectively formed. However, increase of Ge-fraction significantly enhances the random bulk-nucleation, which results in poly-crystalline Si_1-xGe _x (x ≥ 0.2) with random-orientations. To enhance interfacial-nucleation at Al/quartz over bulk-nucleation, film-thickness of Al and SiGe are thinned to 50 nm. This achieves (111)-oriented Si _1-xGe_x films with the whole Ge fractions. This oriented-growth can be explained by the theoretical calculation that (111) SiGe has the minimum surface energy on quartz substrates.

DOI： 10.1149/2.010203jss

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1149/05005.0059ecst

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1063/1.4769998

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1149/05009.0431ecst

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DOI： 10.1149/05009.0747ecst

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (other academic)  

Language：English   Publishing type：Research paper (other academic)  

Language：English   Publishing type：Research paper (other academic)  

Language：English  

DOI： 10.1149/05005.0059ecst

Language：English  

DOI： 10.1149/05009.0431ecst

Language：English  

DOI： 10.1149/05009.0747ecst

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1063/1.4748328

Language：English  

DOI： 10.1149/2.010203jss

Language：English   Publishing type：Research paper (scientific journal)  

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DOI： 10.1109/IMFEDK.2012.6218600

Language：English  

DOI： 10.1143/JJAP.51.06FF04

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1143/JJAP.51.06FF04

Language：Japanese   Publishing type：Research paper (scientific journal)  

Language：Japanese   Publishing type：Research paper (scientific journal)  

The development of high-quality Ge-on-insulator (GOI) structures is essential for making a breakthrough into the scaling limit of Si large-scale integrated circuits. In the present paper, we review a new GOI growth technique, i.e., the SiGe-mixing-triggered rapid-melting growth technique, which enables chip-sized and mesh-shaped GOI structures. In addition, the integration of GOI(111) on Si(100) substrates becomes possible by combining this method with the Si-microseeding technique. These progresses pave the way for the artificial single-crystal technology.

DOI： 10.11470/oubutsu.81.5_410

Language：Japanese   Publishing type：Research paper (scientific journal)  

Melting growth of Si-doped Ge films, i.e., Ge(Si) films, on insulator has been investigated. After rapid-thermal annealing of Ge(Si) films in the temperatures region surrounded with the liquidus curve and solidus curve of the phase diagram of the SiGe system, SiGe crystals with large-grains (15-30μm) were formed. The Si concentration profiles in the grains showed peaks at the center of grains. The peak Si concentrations were almost the same as the Si concentrations along the solidus curve at the annealing temperature. These phenomena were explained based on the formation of Si-rich micro-crystals during annealing and subsequent Si-segregated lateral-growth during cooling.

Language：Japanese   Publishing type：Research paper (scientific journal)  

A technique for low-temperature(<〜350℃) formation of orientation-controlled large-grain Ge films on insulating layers is desirable for realization of flexible high-speed thin film transistors. In line with this, we have investigated Au-induced layer-exchange crystallization using a-Ge/Au/insulator stacked structures where Al_2O_3 layers were inserted at a-Ge/Au interfaces. Consequently, (111)-oriented large-grain (20-50 μm) films are obtained by inserting the interfacial layers (〜3 μm). These phenomena are explained based on the retardation of random bulk nucleation in Au films and thus domination of(111)-oriented nucleation on insulators, caused by suppression of Ge/Au interdiffusion.

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1063/1.4705733

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Language：English  

DOI： 10.1016/j.tsf.2011.10.076

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1063/1.3691258

Language：English   Publishing type：Research paper (scientific journal)  

Low-temperature (∼250°C) layer exchange crystallization of poly-Si _{1 - x}Ge _x (x = 1-0) films on insulators has been investigated for realization of advanced flexible devices. We propose utilization of Au as catalyst to enhance the crystallization at low temperatures. By annealing (∼250°C, 20 h) of the a-Si _{1 - x}Ge _x (x = 1-0)/Au stacked structures formed on insulating substrates, the SiGe and Au layers exchange their positions, and Au/poly-SiGe stacked structures are obtained. The Ge fractions of the obtained poly-SiGe layers are identical to that of the initial a-SiGe layers, and there is no Si or Ge segregation. This low temperature crystallization technique enables poly-SiGe films on plastic substrates, which are essential to realize advanced flexible devices.

DOI： 10.1016/j.tsf.2011.10.087

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1016/j.tsf.2011.10.088

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1016/j.tsf.2011.10.076

Language：English  

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DOI： 10.1016/j.tsf.2011.10.088

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1016/j.phpro.2012.01.006

Language：Japanese   Publishing type：Research paper (scientific journal)  

It is necessary two processes (crystal-nucleus formation and crystal grain growth) for crystallization. In general, the activation energy of crystal-nucleus formation is higher than that of grain growth. To realize low-temperature crystallization, we tried to form the quasi-nucleus by soft X-ray irradiation. In this study, the effects of soft X-ray irradiation on crystallization of a-Si and a-Ge films were investigated. The crystallization temperatures of a-Si film and a-Ge film were decreased from 680℃ to 580℃ and 500℃ to 420℃ by soft X-ray irradiation, respectively. The decrease in crystallization temperature is also related to enhancement of atomic migration and atoms transitioning into a quasi-nuclei phase in the films.

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1016/j.tsf.2011.05.024

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1016/j.tsf.2011.05.018

Language：English   Publishing type：Research paper (other academic)  

The gold-induced crystallization technique has been investigated to achieve poly-SiGe films on insulators at low temperatures (≤ 300°C). By annealing of the amorphous SiGe (Ge concentration: 0-100%)/Au stacked structures formed on insulating substrates, positions of the SiGe and Au layers are inverted, and the Au/SiGe stacked structures are obtained. Crystallization of the SiGe layers in the inverted samples is confirmed by the Raman scattering spectroscopy analysis. Moreover, the Raman measurements reveal that the Ge fractions in the crystallized SiGe layers are almost the same as those of the initial amorphous SiGe layers. This gold-induced layer-exchange crystallization technique of SiGe layers at a low temperature (∼250°C) will be very useful to obtain poly-SiGe layers on plastic substrates, which are essential to realize flexible high-speed thin-films transistors and high-efficiency solar cells.

DOI： 10.1149/1.3570774

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1149/1.3570776

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1149/1.3570777

Language：English   Publishing type：Research paper (scientific journal)  

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DOI： 10.1063/1.3611904

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DOI： 10.1016/j.sse.2011.01.037

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1016/j.sse.2011.01.037

Language：English   Publishing type：Research paper (scientific journal)  

Metal-induced lateral crystallization (MILC) of amorphous Ge has been investigated to realize low temperature formation of poly-Ge films on insulating substrates. From a comparative study of MILC with various catalysis metals (Ni, Co, Pd, and Cu), it was found that Cu enhanced both nucleation and subsequent nucleus growth the most significantly among the species. Consequently, low temperature (∼ 250°C) growth with a high velocity (∼1 m/h) of poly-Ge films becomes possible by employing Cu as the catalyst. This technique will accelerate the realization of advanced high-speed TFT on flexible substrates.

DOI： 10.1149/1.3582794

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1016/j.sse.2011.01.039

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DOI： 10.1016/j.sse.2011.01.033

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DOI： 10.1016/j.sse.2011.01.033

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DOI： 10.1016/j.sse.2011.01.039

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DOI： 10.1016/j.sse.2011.01.039

Language：English   Publishing type：Research paper (scientific journal)  

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DOI： 10.1063/1.3586259

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DOI： 10.1149/1.3570777

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DOI： 10.1149/1.3570776

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DOI： 10.1149/1.3570774

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DOI： 10.1149/1.3570777

Language：English   Publishing type：Research paper (scientific journal)  

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DOI： 10.1149/1.3562275

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.4028/www.scientific.net/KEM.470.8

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.3390/s110303067

Language：English  

DOI： 10.1149/1.3551465

Language：English   Publishing type：Research paper (scientific journal)  

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DOI： 10.1143/JJAP.50.010101

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1063/1.3544057

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DOI： 10.1063/1.3535606

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DOI： 10.1016/j.phpro.2011.01.004

Language：English   Publishing type：Research paper (scientific journal)  

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Language：English   Publishing type：Research paper (scientific journal)  

High-strain Si-pillars are desirable for achieving high-speed three-dimensional transistors. The effects of postannealing (400-1150C) on strain-enhancement in Si-pillars covered with Si₃N₄ stress-liners are investigated. Before annealing, the Si₃N ₄ stress-liners induce strain in Si, where the direction of strain, which can be compressive or tensile, depends on the Si₃N₄ deposition parameters. After postannealing (800C), the strain becomes highly compressive, because of dehydrogenation-induced structural relaxation in Si ₃N₄ films. Consequently, compressive strains (1.6) are induced in the 200-nm-thick Si-pillars covered in 200-nm-thick Si ₃N₄ films after high temperature postannealing (1000-1150C). This strain-enhancement technique is useful for the realization of advanced high-speed three-dimensional transistors.

DOI： 10.1149/1.3551465

Language：English   Publishing type：Research paper (scientific journal)  

Au-induced crystallization of Si through a layer-exchange process has been investigated to achieve poly-Si films on insulators at low-temperatures (∼250°C). By annealing (250-350°C) of amorphous Si (a-Si)/Au stacked structures formed on insulators, the positions of Si/Au layers are inverted, and Au/poly-Si stacked structures are obtained. This Au-induced layer-exchange growth technique at low-temperatures (∼250°C) should be very useful to obtain poly-Si films on flexible substrates, which are employed as template layers for growth of high quality Si_1-xGe_x (x: 0-1) films to realize flexible high-speed thin-film transistors and flexible high-efficiency solar cells.

DOI： 10.1149/1.3562275

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1149/1.3487571

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1109/ICSICT.2010.5667440

Language：English  

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DOI： 10.1149/1.3486089

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DOI： 10.1063/1.3493184

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DOI： 10.1149/1.3486089

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1142/S0217979210056657

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1143/APEX.3.075603

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1142/S0217979210056050

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Language：Japanese   Publishing type：Research paper (scientific journal)  

Large grain polycrystalline silicon-germanium (poly-SiGe) with controlled crystal orientation on glass substrates is required to achieve high speed thin-film transistors and high-efficiency thin-film solar cells. For this purpose, we have developed an advanced Al-induced crystallization (AIC) technique by controlling the interfacial oxide layers. As a results, homogeneous and large-grained (>10 μm) AIC growth was achieved for samples with the whole Ge fractions (0-100%). In addition, we evaluated crystal orientation of the poly-SiGe and discuss the growth mechanism.

Language：Japanese   Publishing type：Research paper (scientific journal)  

We proposed SiGe mixing triggered melting growth, and realized (100)-oriented Ge on insulator (GOI) stripes (〜400μm) by using Si(100) substrates as crystal seed. To expand the application fields of such GOI structures, GOI stripes with various crystal orientations should be achieved. In the present study, growth-direction-dependent characteristics of GOI from Si(100), (110), (111) seeding substrates are investigated. During the study, we encountered a phenomenon of rotating growth of Ge layers. The detail of the rotation growth is investigated, and a guideline to prevent this phenomenon is clarified. As a results, GOI(110) and (111) stripes without the rotation are realized, together with GOI(100) stripes. Moreover, a large mesh (500μm × 250μm) of GOI stripe is realized based on these findings.

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1143/JJAP.49.04DA08

Language：English   Publishing type：Research paper (scientific journal)  

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DOI： 10.1063/1.3368701

Language：Japanese  

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DOI： 10.1143/APEX.3.031301

Language：English  

DOI： 10.1016/j.tsf.2009.10.106

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1016/j.tsf.2009.10.106

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1016/j.tsf.2009.10.084

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DOI： 10.1016/j.tsf.2009.10.081

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DOI： 10.1016/j.tsf.2009.10.083

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DOI： 10.1016/j.tsf.2009.10.107

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DOI： 10.1016/j.tsf.2009.10.082

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DOI： 10.1016/j.tsf.2009.10.107

Language：English  

DOI： 10.1016/j.tsf.2009.10.084

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DOI： 10.1016/j.tsf.2009.10.082

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DOI： 10.1016/j.tsf.2009.10.081

Language：English  

DOI： 10.1016/j.tsf.2009.10.083

Language：Others   Publishing type：Research paper (scientific journal)  

フレキシブルな高速薄膜トランジスタ(TFT)の実現には，高移動度を有する半導体薄膜をプラスチックの軟化温度(∼300^oC)以下の極低温で高品質形成する必要がある．我々は，共晶温度の低いAu/Ge系（共晶点: 361^oC）に着目し，高移動度半導体(Ge)の低温成長を検討した．非晶質Ge（100 nm）/ Au（100 nm）の積層構造を石英基板上に作製した．熱処理（200∼400^oC）後の試料の組成分布の変化と結晶性を評価した処，低温(250^oC)で，Ge/Auが層交換すると共に，Geが結晶化することが明らかとなった．フレキシブルな高速TFTの実現を加速する画期的な成果である．

DOI： 10.11527/jceeek.2010.0.584.0

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1063/1.3422477

Language：English   Publishing type：Research paper (other academic)  

The gold-induced crystallization technique has been investigated to achieve poly-Si films on insulators at low temperatures (≤250°C). By annealing (∼250°C) the amorphous Si (a-Si)/Au stacked structures formed on insulating substrates, the positions of Si/Au layers are inverted, and Au/poly-Si stacked structures are obtained. On the other hand, by annealing (>400°C) the structures, mixed layers of c-Si and Au are obtained. These growth phenomena are explained on the basis of the eutectic reaction. This gold-induced layer-exchange growth technique at low-temperatures (∼250°C) is very useful to obtain poly-Si on flexible substrates, which are essential to realize flexible high-speed thin-films transistors and high-efficiency solar cells.

DOI： 10.1109/TENCON.2010.5686705

Language：English   Publishing type：Research paper (scientific journal)  

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DOI： 10.1063/1.3278596

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DOI： 10.1063/1.3231925

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DOI： 10.1063/1.3241076

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DOI： 10.1063/1.3182795

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DOI： 10.1016/j.sse.2009.08.002

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DOI： 10.1063/1.3136857

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DOI： 10.1063/1.3130211

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1063/1.3065985

Language：Japanese   Publishing type：Research paper (scientific journal)  

Low-temperature (<550℃) Al-induced crystallization (AIC) of amorphous Si_<1-x>Ge_x (x=0-1) on glass substrate has been investigated to achieve high-speed thin-film transistors and high-efficiency thin-film solar cells. Crystal growth morphology drastically changed with Ge fraction, and layer exchange occurred heterogeneously for high Ge fractions (>50%). To solve this problem, the effects of interfacial oxide thickness on AIC growth were investigated. As a result, homogeneous layer exchange was achieved for samples with the whole Ge fractions (x=0-1) by controlling the air exposure time. These new findings will be a powerful tool to obtain high quality poly-SiGe films on glass substrates.

Language：English   Publishing type：Research paper (scientific journal)  

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DOI： 10.1143/JJAP.48.03B007

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DOI： 10.1143/JJAP.48.03B002

Language：Others   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

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DOI： 10.1143/JJAP.48.03B004

Language：Others   Publishing type：Research paper (scientific journal)  

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DOI： 10.3938/jkps.54.451

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1109/ICSICT.2008.4734647

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DOI： 10.1149/1.2986782

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DOI： 10.1149/1.2986773

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DOI： 10.1149/1.2986768

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DOI： 10.1149/1.2986783

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DOI： 10.1016/j.tsf.2008.08.110

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DOI： 10.1016/j.tsf.2008.08.030

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DOI： 10.1016/j.tsf.2008.08.057

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DOI： 10.1016/j.tsf.2008.08.121

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DOI： 10.1016/j.tsf.2008.08.021

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Oxidation of SiGe/SOI (Ge fraction: 0-50%) structures was investigated in a wide temperature range. Different oxidation features were observed for samples oxidized in low (< 680 °C), middle (700-800 °C), and high (> 800 °C) temperature regions. Very thin SiO₂ layers (< 150 nm) were formed during low (< 680 °C) temperature oxidation. Thus, the Ge fractions at the SiO₂/SiGe interfaces were almost the same as the initial Ge fractions (< 50%). Therefore, the initial Ge fraction dependent enhanced oxidation was observed. On the other hand, very thick SiO₂ (> 200 nm) was formed during high (> 800 °C) temperature oxidation. Thus, the oxidation rate was limited by the diffusion process of O in SiO₂. Therefore, the oxidation rate did not depend on the Ge fraction. At middle temperatures, the oxidation rate does not depend on the temperature for samples with high initial Ge fractions (> 20%). This is due to that increase in oxidation rate by increasing temperature was cancelled by the retardation of oxidation due to high Ge fractions (> 50%) piled-up at the SiO₂/SiGe interfaces.

DOI： 10.1016/j.tsf.2008.08.025

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DOI： 10.1016/j.tsf.2008.08.055

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DOI： 10.1063/1.2996581

Language：English   Publishing type：Research paper (scientific journal)  

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DOI： 10.1063/1.2977866

Language：Japanese  

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DOI： 10.1016/j.sse.2008.05.009

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DOI： 10.1016/j.apsusc.2008.02.139

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DOI： 10.1016/j.apsusc.2008.02.146

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DOI： 10.1093/ietele/e91-c.5.708

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1093/ietele/e91-c.5.708

Language：Japanese  

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1117/12.792280

Language：Japanese  

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DOI： 10.1143/JJAP.47.1876

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DOI： 10.1063/1.2894583

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DOI： 10.1149/1.2778396

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DOI： 10.1149/1.2778404

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DOI： 10.1149/1.2778406

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DOI： 10.1149/1.2778405

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DOI： 10.1063/1.2801705

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DOI： 10.1016/j.tsf.2007.02.019

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DOI： 10.1063/1.2764447

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DOI： 10.1016/j.tsf.2007.02.052

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DOI： 10.1143/JJAP.46.1250

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DOI： 10.1149/1.2355858

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DOI： 10.1063/1.2378399

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1063/1.2374849

Language：English   Publishing type：Research paper (scientific journal)  

Poly-Ge thin-film transistors (TFTs) with Schottky source/drain (S/D) contacts were fabricated on glass by low-temperature (<500 °C) processing. First, the annealing characteristics of Ni/crystal-Ge stacked structures were examined. The results indicated that NiGen-Ge Schottky contacts (φ Bn =0.51 eV, n=1) with flat interfaces and low reverse leakage current [(2-5) × 10-2 A cm2] could be obtained by choosing an appropriate annealing temperature (200-300 °C). Based on this result, p -channel TFTs were fabricated with poly-Ge formed on glass by solid-phase crystallization at 500 °C. TFTs showed relatively high hole mobility (about 140 cm2 V s) with very low S/D parasitic resistance and no kink effect. The potential capability of the proposed devices for high-performance TFTs was demonstrated.

DOI： 10.1063/1.2387136

Language：English   Publishing type：Research paper (scientific journal)  

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DOI： 10.1016/j.tsf.2005.07.316

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DOI： 10.1016/j.tsf.2005.10.005

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DOI： 10.1016/j.tsf.2005.07.315

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DOI： 10.1016/j.tsf.2005.06.102

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DOI： 10.1016/j.tsf.2005.07.317

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DOI： 10.1143/JJAP.45.4370

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DOI： 10.1143/JJAP.45.4351

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DOI： 10.1143/JJAP.45.3147

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DOI： 10.1063/1.2192644

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DOI： 10.1143/JJAP.45.3598

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DOI： 10.1541/ieejeiss.126.1073

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DOI： 10.1016/j.tsf.2005.01.037

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Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Postannealing characteristics of in situ doped B atoms in poly- Si1-x Gex (x≤0.5) films on SiON have been investigated. Supersaturated electrically active B (2× 1020 cm-3) is obtained for as-chemical vapor deposition samples, and their thermal stability is significantly improved by increasing Ge fraction, e.g., the stability for poly- Si0.6 Ge0.4 is ten times as high as that for poly-Si at 700-800°C. Such a Ge induced improvement will be a powerful tool to achieve poly-SiGe gate electrode for the next generation ultralarge scale integrated circuits. In addition, the deactivation process of electrically active B has been analyzed. Results indicated that deactivation processes consist of fast and slow processes. The former is due to movement of B atoms from substitutional to interstitial sites, which is enhanced by a local strain induced by the difference in atomic radii between Si and B atoms. The slow process was due to trapping of B at grain boundaries during grain growth. The two-state model based on the local strain compensation by Ge doping is proposed, which can well explain the Ge dependent thermal stability of electrically active B atoms.

DOI： 10.1063/1.1854731

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1063/1.1935028

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DOI： 10.1143/JJAP.44.2405

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DOI： 10.1143/JJAP.44.2357

Language：English   Publishing type：Research paper (scientific journal)  

Au-induced low-temperature (400 °C) crystallization of amorphous-Si_1-xGe_x (x: 0-1) thin films on SiO₂ has been investigated. Although the growth velocity decreased with increasing Ge fraction, growth velocity exceeding 20 μm/h was obtained in all Ge fractions. As a result, strain-free poly-Si_1-xGe_x with large areas (>20 μm) were obtained at a low temperature (400 °C). These new polycrystalline SiGe films on insulator could be used for advanced system in display and three-dimensional ULSI.

DOI： 10.1016/j.mssp.2004.09.060

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1016/j.mssp.2004.09.043

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1016/j.mssp.2004.09.036

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1557/proc-0908-oo05-21

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1143/JJAP.44.2357

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1117/12.596398

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1016/j.tsf.2004.06.010

Language：English   Publishing type：Research paper (scientific journal)  

Solid-phase growth of the [a-Si/a-FeSiGe] _n (n: 1, 2, 4; total thickness: 500nm) stacked structure has been investigated. After annealing at 700°C, the [a-SiGe/β-FeSi ₂ (Ge)] _n stacked structures were formed. From the analysis of the X-ray diffraction spectra, it was found that β-FeSi ₂ (Ge) was strained by 0.4-0.5% for n = 1. With increasing n, the strains decreased, which was due to segregation of Ge atoms from the a-FeSiGe layers to the a-Si layers. After annealing at 800°C, agglomeration of β-FeSi ₂ occurred and Ge atoms vanished completely from the β-FeSi ₂ lattice. Thus, nanocrystals of relaxed β-FeSi ₂ and c-Si _0.7 Ge _0.3 were formed. These new structures can be useful for formation of opto-electrical devices.

DOI： 10.1016/S0169-4332(04)01007-4

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Growth of SiGe/β-FeSi₂ superstructures by annealing of a-Si/a-FeSiGe layered structures was investigated for control of the strains in β-FeSi₂ by Ge doping. The [a-SiGe/β-FeSi ₂(Ge)]_n multi-layered structures were formed after annealing at 700°C. From the analysis of the X-ray diffraction (XRD) spectra, it was found that β-FeSi₂(Ge) was strained by 0.4-0.5% for the sample with n=1. The strains decreased with increasing n, which was due to that the segregation of the Ge atoms from the a-Fe_0.4Si _0.5Ge_0.1 layers to the a-Si layers became large with increasing n. After annealing at 800°C, agglomeration of β-FeSi ₂ occurred, and nanocrystals of relaxed β-FeSi₂ and c-Si_0.7Ge_0.3 were formed. These demonstrate that the SiGe/β-FeSi₂ superstructures were formed by the Ge segregation. These new structures are useful for formation of opto-electrical devices.

DOI： 10.1016/j.tsf.2004.02.068

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1016/j.tsf.2004.02.048

Language：English   Publishing type：Research paper (scientific journal)  

Dependence of solid-phase growth of β-FeSi₂ thin films on the crystal orientation of Si substrates has been investigated by using a-Fe (thickness: 20 nm)/c-Si(100), (110) and (111) stacked structures. X-ray diffraction (XRD) measurements suggested that the substrate orientation dependence of the formation rate of β-FeSi₂ was as follows: (100)>(111)>(110). This dependence can be explained on the basis of the lattice mismatch between β-FeSi₂ and Si substrates, i.e., the lattice mismatch between β-FeSi₂(100) and Si(100), β-FeSi₂(110) or (101) and Si(111), and β-FeSi ₂(010) or (001) and Si(110) of 1.4-2.0%, 5.3-5.5% and 9.2%, respectively. The substrate orientation dependence of solid-phase growth becomes relatively remarkable for very thin films.

DOI： 10.1016/j.tsf.2004.02.065

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1063/1.1780595

Language：English   Publishing type：Research paper (scientific journal)  

Carrier transport in ion-beam synthesized (IBS) β-FeSi₂ was investigated by using Hall effect measurement at low temperatures (15-300 K). The measurement showed p-type conduction in the temperature range of 15-300 K. The Hall coefficient increased with increasing temperature up to 25 K, and then it decreased, which suggested the two carrier conduction, i.e., the impurity conduction, as well as the conduction in the valence band, play an important role in the carrier transport. Based on the two carrier model, the hole concentration and mobility for the impurity conduction at 25 K were evaluated to be 9.9×10¹⁷ cm^-3 and 0.85 cm² V ^-1 s^-1, respectively, which suggested that the acceptors were isolated and did not form the impurity band at the impurity concentration of 9.9×10¹⁷ cm^-3. Thus, the threshold concentration for the impurity band formation was more than three orders of magnitude higher than that for GaAs (2×10¹⁶ cm^-3), which could be explained on the basis of the Mott criterion.

DOI： 10.1016/j.tsf.2004.02.071

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1063/1.1707216

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1143/JJAP.43.1852

Language：English   Publishing type：Research paper (scientific journal)  

The solid-phase growth of [a-Si/a-Fe_0.4Si_0.5Ge_0.1]_n (n=1, 2, 4; total thickness: 500 nm) multilayered structures has been investigated. After annealing at 700°C, [a-SiGe/polycrystalline β-FeSi_2−xGe_x]_n (x=0.5, 0.4, 0.2 for n=1, 2, 4, respectively) multilayered structures were formed. From the analysis of X-ray diffraction spectra, it was found that the lattice constants of β-FeSi_1.5Ge_0.5 changed from those of relaxed β-FeSi₂ by 0.4–0.5%. The change decreased with increasing n, which was due to the segregation of Ge atoms from the a-Fe_0.4Si_0.5Ge_0.1 layers to the a-Si layers becoming larger with increasing n. After annealing at 800°C, Ge atoms were completely swept out from the β-FeSi_2−xGe_x lattice. In addition, the agglomeration of β-FeSi₂ occurred, and nanocrystals of relaxed β-FeSi₂ and c-Si_0.7Ge_0.3 were formed. This technique for the formation of β-FeSi_2−xGe_x is expected to be useful for energy gap modulation for advanced optoelectrical devices.

DOI： 10.1143/JJAP.43.1879

Language：English   Publishing type：Research paper (scientific journal)  

The solid-phase growth of [a-Si/a-Fe_0.4Si_0.5Ge _0.1]_n (n = 1, 2, 4; total thickness: 500 nm) multilayered structures has been investigated. After annealing at 700°C, [a-SiGe/polycrystalline β-FeSi_2-xGe_x]_n (x = 0.5, 0.4, 0.2 for n = 1, 2, 4, respectively) multilayered structures were formed. From the analysis of X-ray diffraction spectra, it was found that the lattice constants of β-FeSi_1.5Ge_0.5 changed from those of relaxed β-FeSi₂ by 0.4-0.5%. The change decreased with increasing n, which was due to the segregation of Ge atoms from the a-Fe _0.4Si_0.5Ge_0.1 layers to the a-Si layers becoming larger with increasing n. After annealing at 800°C, Ge atoms were completely swept out from the β-FeSi_2-xGe_x lattice. In addition, the agglomeration of βFeSi₂ occurred, and nanocrystals of relaxed β-FeSi₂ and c-Si_0.7Ge _0.3 were formed. This technique for the formation of βFeSi _2-xGe_x is expected to be useful for energy gap modulation for advanced optoelectrical devices.

DOI： 10.1143/JJAP.43.1879

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1143/JJAP.43.1901

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1143/JJAP.43.1901

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1016/j.apsusc.2003.08.051

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1016/j.tsf.2003.11.011

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1016/j.apsusc.2003.08.050

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1016/j.tsf.2003.11.059

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1143/JJAP.43.1879

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.15017/1515848

Language：English   Publishing type：Research paper (scientific journal)  

Solid-phase growth of [a-Si/a-Fe_0.4Si_0.5Ge_0.1]_n stacked-structures has been investigated. [a-Si/a-Fe_0.4Si_0.5Ge_0.1]_n/c-Si (n=1, 2, 4) samples were annealed at 700-900°C for 30 min in a vacuum. The grown layers were analyzed by using Auger electron spectroscopy, the X-ray diffraction, Raman spectroscopy, and the transmission electron microscopy. After annealing at 700°C, β-FeSi₂(Ge) strained by 0.4-0.5% was successfully formed for the sample with n=1. The strains became small with increasing n, i.e., with thinning layer. In addition, superstructures consisting of β-FeSi₂ and c-Si_0.7Ge_0.3 nanocrystals were obtained by Ge segregation after annealing at 800°C. These new structures are useful for fabrication of opto-electrical devices.

Language：English   Publishing type：Research paper (scientific journal)  

Orientation dependent solid-phase growth of β-FeSi₂ thin films on (100), (110), and (111) Si substrates has been investigated by using a-Fe(thickness: 20 nm)/c-Si stacked structures. XRD measurements suggested that the substrate orientation dependence of the formation rate of β-FeSi₂ was as follows: (100) > (111) > (110). This dependence can be explained on the basis of the lattice mismatch between β-FeSi₂ and Si substrates, i.e., the lattice mismatch between β-FeSi₂ (100) and Si (100), β-FeSi₂ (110) or (101) and Si (111), and β-FeSi₂ (010) or (001) and Si (110) are 1.4-2.0%, 5.3-5.5%, and 9.2%, respectively. The substrate orientation dependence of solid-phase growth becomes relatively remarkable for very thin films.

Language：English   Publishing type：Research paper (scientific journal)  

Orientation dependent solid-phase growth of β-FeSi_2 thin films on (100), (110), and (111) Si substrates has been investigated by using a-Fe (thickness: 20 nm)/c-Si stacked structures. XRD measurements suggested that the substrate orientation dependence of the formation rate of β-FeSi_2 was as follows: (100) > (111) > (110). This dependence can be explained on the basis of the lattice mismatch between β-FeSi_2 and Si substrates, i.e., the lattice mismatch between β-FeSi_2(100) and Si (100), β-FeSi_2 (110) or (101) and Si (111), and β-FeSi_2(010) or (001) and Si (110) are 1.4-2.0%, 5.3-5.5%, and 9.2%, respectively. The substrate orientation dependence of solid-phase growth becomes relatively remarkable for very thin films.

DOI： 10.15017/1515849

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1016/S0921-5107(02)00620-7

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Effects of Ar⁺ ion-irradiation on solid-phase growth of β-FeSi₂ have been investigated. Fe (10 nm)/Si structures were irradiated with 20 keV Ar⁺ (5.0 × 10¹⁵ cm^-2) at room temperature (RT) or 400 °C, and subsequently annealed at 800 °C. The results of X-ray diffraction measurements suggested that the formation of β-FeSi₂ for the sample irradiated at RT was faster than that irradiated at 400 °C. However, Auger electron spectroscopy measurements showed that atomic mixing at the Fe/Si interface before annealing was larger for the sample irradiated at 400 °C. These results suggested that amorphization of the Si substrate, in addition to atomic mixing at the Fe/Si interface, enhanced formation of β-FeSi₂, which was attributed to atomic rearrangement induced during defect relaxation in annealing process.

DOI： 10.1016/S0168-583X(03)00750-X

Language：English   Publishing type：Research paper (scientific journal)