記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

出版者・発行元：Materials Science in Semiconductor Processing  

Germanium is an attractive material for advanced devices such as high speed transistors and high efficiency optical devices. To realize the high performance operation, low resistive contacts to Ge are required. However, the Fermi level in Ge at metal/Ge contacts is often pinned near the valance band edge. This Fermi level pinning generates high Schottky barrier heights at metal/Ge contacts regardless the work function of the metals, which results in low resistive contacts to p-type Ge but high resistive contacts to n-type Ge. Thus, a technique for modulating the Schottky barrier heights at metal/Ge contacts is desired. For this purpose, effects of surface treatments of Ge using phosphoric acid coating and excimer laser annealing (LA) were investigated. After LA without phosphoric acid coating, the reverse current of the Al/n-type Ge contacts is increased by an order of magnitude. On the other hand, the reverse current is significantly increased by three orders of magnitude after LA with phosphoric acid coating. Here, the Schottky barrier heights are decreased from 0.56 to 0.50 eV and from 0.59 to 0.49 eV after LA for samples without and with phosphoric acid coating, respectively. These phenomena are attributed to formation of very thin GeOx surface layers and very shallow doped layers having very high P concentrations, respectively. This technique is useful for modulation of the Fermi level pinning for metal/Ge contacts with the low thermal budget.

DOI： 10.1016/j.mssp.2023.107433

Web of Science

Scopus

出版者・発行元：Materials Science in Semiconductor Processing  

DOI： 10.1016/j.mssp.2023.107386

Web of Science

Scopus

出版者・発行元：30th International Workshop on Active-Matrix Flatpanel Displays and Devices: TFT Technologies and FPD Materials, AM-FPD 2023 - Proceedings  

Solid-phase crystallization of Sn-doped Si thin films (Sn concentration: 1%, thickness: ≤ 30 nm) on insulator has been investigated. After annealing of the Sn-doped Si thin films at temperatures below 600oC, domain structures were observed. The growth velocities of the domains decreased with decreasing film thickness. However, they are significantly higher compared with the reported values of the solid-phase epitaxy of Si. The crystal structures of the grown films also depended on the film thickness, and larger grain sizes are obtained for thicker films.

Scopus

出版者・発行元：30th International Workshop on Active-Matrix Flatpanel Displays and Devices: TFT Technologies and FPD Materials, AM-FPD 2023 - Proceedings  

A technique to obtain high carrier mobility of Sn-doped Ge thin-films (thickness: ≤20 nm) on insulators is proposed. In a conventional approach, the grain sizes of Sn-doped poly-Ge films grown by solid-phase crystallization decrease with decreasing thickness. This significantly deteriorates the carrier mobility. To solve this problem, thinning of thick Ge films having large grain sizes is investigated. Moreover, to eliminate the crystal defects, post-Annealing is examined. This achieves high carrier mobility (~200 cm2/Vs) even for thin-films (thickness: 20 nm). A good transistor operation is demonstrated using the thinned Ge films. This technique will be useful to realize advanced thin-film transistors for next-generation electronics.

Scopus

出版者・発行元：30th International Workshop on Active-Matrix Flatpanel Displays and Devices: TFT Technologies and FPD Materials, AM-FPD 2023 - Proceedings  

To achieve high performance of advanced devices, a doping process with low thermal budget is required. For this purpose, excimer laser doping into Si is investigated. By using ultra-thin Al films deposited on n-type Si substrates as diffusion source, p-type regions are formed on the surfaces of the n-type Si substrates after laser irradiation. The electrical properties and surface morphologies of the samples are investigated as a function of the laser fluence. PN junctions showing good rectifying characteristics without surface roughening are obtained by optimization of the laser fluence. This technique will be useful to realize next-generation high-performance devices with low thermal budget.

Scopus

DOI： 10.7567/ssdm.2023.ps-11-03

CiNii Research

DOI： 10.7567/ssdm.2023.ps-11-04

CiNii Research

DOI： 10.7567/ssdm.2023.ps-11-09

CiNii Research

出版者・発行元：Journal of Applied Physics  

Rapid-thermal annealing (RTA) of InSb precursor films, deposited by sputtering using an Ar plasma at room temperature, has been investigated to achieve high carrier mobility on low-cost glass substrates. Although InSb films containing residual Ar (∼1%) were partially lost by evaporation during RTA, such evaporation during RTA is suppressed by reducing the residual Ar to ∼0.3%. The crystallinity of the films is significantly increased by RTA at temperatures above 400 °C. The electron mobilities of the films increase with increasing RTA temperature up to 490 °C, showing the maximum values (9000-10 000 cm2 V-1 s-1) at 490 °C, and then, the mobilities decrease at RTA temperatures above 490 °C. The mobilities of 9000-10 000 cm2 V-1 s-1 are obtained for films with a wide range of thickness (300-1000 nm) grown at 490 °C. Detailed analysis indicated that the high carrier mobilities are realized by preferentially (111)-oriented large crystal domains (diameter: >100 μm), obtained by the regrowth of randomly oriented small grains, together with a low barrier height (16 meV) at the sub-domain boundaries (twin boundaries) in the large domains. The RTA after the sputtering technique will facilitate high-performance InSb-based devices with low production costs.

DOI： 10.1063/5.0105045

Web of Science

Scopus

記述言語：英語   出版者・発行元：AIP Publishing  

Rapid-thermal annealing (RTA) of InSb precursor films, deposited by sputtering using an Ar plasma at room temperature, has been investigated to achieve high carrier mobility on low-cost glass substrates. Although InSb films containing residual Ar (∼1%) were partially lost by evaporation during RTA, such evaporation during RTA is suppressed by reducing the residual Ar to ∼0.3%. The crystallinity of the films is significantly increased by RTA at temperatures above 400 °C. The electron mobilities of the films increase with increasing RTA temperature up to 490 °C, showing the maximum values (9000–10 000 cm^2 V^<−1> s^<−1>) at 490 °C, and then, the mobilities decrease at RTA temperatures above 490 °C. The mobilities of 9000–10 000 cm^2 V^<−1> s^<−1> are obtained for films with a wide range of thickness (300–1000 nm) grown at 490 °C. Detailed analysis indicated that the high carrier mobilities are realized by preferentially (111)-oriented large crystal domains (diameter: >100 μm), obtained by the regrowth of randomly oriented small grains, together with a low barrier height (16 meV) at the sub-domain boundaries (twin boundaries) in the large domains. The RTA after the sputtering technique will facilitate high-performance InSb-based devices with low production costs.

CiNii Research

出版者・発行元：Proceedings of the International Display Workshops  

High-speed fully-depleted thin-film transistors (TFTs) are required for next-generation electronics, such as three-dimensional large-scale integrated circuits and advanced system-in-displays. For this purpose, a novel growth technique, i.e., interface-modulated solid-phase crystallization, of Sn-doped Ge has been developed. This achieves high carrier mobility (~100 cm2/Vs) of ultrathin films (20 nm) on insulators.

Scopus

Web of Science

出版者・発行元：Proceedings of AM-FPD 2022 - 29th International Workshop on Active-Matrix Flatpanel Displays and Devices: TFT Technologies and FPD Materials  

Thin poly-Ge films (thickness: ≤ 50 nm) having high carrier mobility are required for advanced thin-film devices. However, carrier mobility of poly-Ge films obtained by conventional solid-phase crystallization (SPC) significantly decreases with decreasing thickness below 50 nm. To solve this problem, we develop an interface-modulated SPC of Sn-doped Ge combined with a-Si capping. In the present study, we investigate growth characteristics of a-Si capped Sn-doped Ge films on insulator. It is clarified that a-Si capping enhances SPC of Sn-doped Ge films and results in large crystal grains, which improves the carrier mobility of Sn-doped Ge thin films. This technique will be useful to realize advanced thin-film devices for next-generation electronics.

DOI： 10.23919/AM-FPD54920.2022.9851292

Scopus

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： https://doi.org/10.1109/JEDS.2019.2956991

その他リンク： https://doi.org/10.1109/JEDS.2019.2956991

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： http://dx.doi.org/10.1149/2.0281910jss

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

High-carrier-mobility thin (≤ ∼50 nm) films on insulator are needed to realize high-performance fully-depleted transistors. To achieve this, an advanced solid-phase crystallization technique of Sn-doped Ge (GeSn) on insulator has been developed. By introduction of a-Si under-layers between GeSn/substrate interfaces, energy barrier for carriers at grain-boundaries in grown films is significantly decreased. As a result, thin (∼50 nm) poly-GeSn films with high carrier mobility of ∼300 cm²/Vs are obtained by using a-Si under-layers. This mobility is the highest among ever reported data for Ge and GeSn thin-films (≤50 nm) on insulator grown at low-temperatures (≤500°C).

DOI： 10.23919/AM-FPD.2019.8830601

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： https://doi.org/10.1063/1.5087235

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

The electrical properties of poly-Si thin films doped using KrF excimer laser irradiation with a phosphoric-acid coating were investigated. After laser doping, the mobility, carrier concentration, activation ratio, and contact resistivity of the poly-Si were found to be 61 cm² /Vs, 1.5×10¹⁸ cm^-3, 18.1 %, and 8.5 × 10^-5Ω.cm², respectively. Additionally, the operation of a bottom gate transistor fabricated using laser doping was realized and is described herein.

DOI： 10.1117/12.2509141

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Low-temperature (≤250°C) formation of Sn-doped Ge (GeSn) (substitutional Sn concentration: 2-3%) on insulator is desired to realize flexible electronics, where high-speed thin-film transistors are integrated on flexible plastic-substrates (softening temperature: ∼300°C). To achieve this, gold-induced lateral crystallization of amorphous GeSn (a-GeSn) is investigated. Here, a-GeSn (Sn concentration: 0%-20%) on insulator structures, having Au-island patterns, were annealed. For initial Sn concentrations of 0%-5%, high-speed lateral crystallization proceeds around Au-patterns, and large grown regions (∼5-20 μm) are obtained by low-temperature short-time annealing (150°C-250°C, 10 min). However, bottom regions of GeSn are not crystallized at 150°C-200°C, while the whole films including bottom regions are crystallized at 250°C. These phenomena are caused by the following temperature-dependent growth mechanisms. At 150°C-200°C, Au atoms are supplied into surface-regions of a-GeSn films from Au-islands by surface-diffusion, resulting in crystallization of only surface-regions. On the other hand, at 250°C, layer-exchange of Au/GeSn occurs, which increases supply channel of Au for diffusion. This results in complete crystallization of GeSn to the bottom. Substitutional Sn concentrations in grown layers are increased with increasing annealing temperature. As a result, GeSn films (substitutional Sn concentration: ∼3%) are obtained at ∼250°C.

DOI： 10.1149/2.0281910jss

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

We characterize poly-Si thin films doped by KrF excimer laser irradiation with a phosphoric-acid coating. In this method, implantation and dopant activation can be performed simultaneously without damage of the poly-Si crystallization. After the laser doping, the mobility, carrier concentration, activation ratio, and resistivity of poly-Si were 61 cm²/Vs, 1.5×10¹⁸ cm^-3, 14.6 %, and 0.08 Ω.cm, respectively.

DOI： 10.23919/AM-FPD.2018.8437343

記述言語：英語   掲載種別：研究論文（学術雑誌）  

The authors wish to retract their publication.1 This action is taken because an error in film thicknesses used in determining the mobilities reported in the manuscript resulted in mobility overestimates by factors of two, three, and four for the films with thicknesses of 100, 150, and 200 nm, respectively. Since the high value of the mobility was the central result of the manuscript and drove much of the discussion, the authors are retracting the publication. The authors sincerely apologize for any inconvenience this mistake may have caused.

DOI： 10.1063/1.5046407

記述言語：英語   掲載種別：研究論文（学術雑誌）  

High-speed thin-film transistors (TFTs) are required to develop the next generation of electronics, such as three-dimensional large-scale integrated circuits and advanced system-in-displays. For this purpose, high-carrier-mobility semiconductor films on insulator structures should be fabricated with low-temperature processing conditions (≤500 °C). To achieve this, we investigate solid-phase crystallization of amorphous-GeSn (a-GeSn) films (Sn concentration: 2% and thickness: 50-200 nm) on insulating substrates, where thin a-Si under-layers (thickness: 0-20 nm) are introduced between a-GeSn films and insulating substrates. The GeSn films are polycrystallized by annealing (450 °C, 20 h) for all samples irrespective of a-GeSn and a-Si thickness conditions, while the Si films remain amorphous. Analysis of crystal structures of GeSn films (thickness: 50 nm) reveals that grain sizes decrease from ∼10 μm to 2-3 μm by the introduction of a-Si under-layers (thickness: 3-20 nm). This phenomenon is attributed to the change in dominant nucleation sites from the interface to the bulk, which significantly decreases grain-boundary scattering of carriers through a decrease in the barrier heights at grain boundaries. Bulk-nucleation further becomes dominant by increasing the GeSn film thickness. As a result, a high carrier mobility of ∼550 cm²/V s is realized for GeSn films (thickness: 100 nm) grown with a-Si under-layers. This mobility is the largest among ever reported data for Ge and GeSn grown on an insulator. This technique will facilitate realization of high-speed TFTs for use in the next generation of electronics.

DOI： 10.1063/1.5024307

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Low-Temperature (<500°C) formation of n-Type crystalline Ge on insulator is desired to merge optical devices onto large-scale integrated circuits. To achieve this, layer-exchange crystallization using a-Ge/Sb stacked structures is investigated. It is revealed that annealing of the stacked structures at 450°C enables formation of high-quality n-Type crystalline Ge on insulator through a layer-exchange process. The grown film shows large domain structures (0.6 mm). This technique will facilitate realization of the next-generation large-scale integrated circuits combined with optical functions.

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Effects of film-Thickness on substitutional Sn concentration in GeSn films on insulator grown by combination of laser irradiation and subsequent thermal annealing are investigated. Here, the laser fluence is chosen as weak, which is below the critical fluence for crystallization of GeSn. It is clarified that for samples irradiated with low fluence, complete crystallization of a-Ge0.8Sn0.2 films (thickness: 50200 nm) is achieved by subsequent thermal annealing at 180°C for 5 h without incubation time. The substitutional Sn concentrations increase with decreasing film thickness. As a result, very high substitutional Sn concentration of ∼15%, which corresponds to high-substitution fraction of ∼75% of total Sn atoms, is achieved for film thickness of 50 nm. This technique will be useful to realize next-generation high performance devices on flexible insulating substrates.

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Low temperature (≤500°C) formation of n-type crystalline Ge films on insulator is required to achieve the next-generation large-scale integrated circuits (LSI), where optical functions are merged. This is because n-type Ge shows high-efficiency optical functions owing to high electron population in the Γ band.

DOI： 10.23919/IWJT.2017.7966503

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Low-temperature (≤200°C) formation of GeSn (substitutional Sn concentration: >8%) films on insulator is desired to realize high-speed thin film transistors (TFTs) and high-efficiency optical devices on flexible plastic substrates (softening temperature: ∼200°C). This is because GeSn (substitutional Sn concentration: >8%) has higher carrier mobility than Si and Ge due to the direct-transition energy band structure with smaller effective mass of carriers.

DOI： 10.23919/IWJT.2017.7966502

記述言語：英語  

絶縁膜上におけるIV族系半導体の結晶成長に関する研究を総括。次世代エレクトロニクスの実現を加速する重要な成果である。

記述言語：英語   掲載種別：研究論文（学術雑誌）  

In this paper, we report on the characterization of Si thin films doped by wet-chemical laser processing. Using this method, implantation and dopant activation can be performed simultaneously. After laser doping, the mobility, carrier concentration, and resistivity of the films were 74 cm²/V·s, 5.5 × 10¹⁷ cm^-3, and 0.15 Ω·cm, respectively.

DOI： 10.1002/sdtp.11659

記述言語：英語   掲載種別：研究論文（学術雑誌）  

膜厚変調型固相成長法を創出し、高移動度を有するGeSn結晶の絶縁膜上における低温成長を実現。次世代フレキシブル・エレクトロニクスの実現を加速する重要な成果である。

DOI： 10.1063/1.4971825

記述言語：英語   掲載種別：研究論文（学術雑誌）  

To realize the advanced thin-film transistors (TFTs), high-carrier-mobility semiconductor films on insulator structures should be fabricated with low-temperature processing conditions (≤500 °C). To achieve this, we investigated the solid-phase crystallization of amorphous-GeSn films on insulating substrates under a wide range of Sn concentrations (0%-20%), film thicknesses (30-500 nm), and annealing temperatures (380-500 °C). Our results reveal that a Sn concentration close to the solid solubility of Sn in Ge (∼2%) is effective in increasing the grain-size of poly-GeSn. In addition, we discovered that the carrier mobility depends on the film thickness, where the mobilities are determined by the counterbalance between two different carrier scattering mechanisms. Here, vacancy-related defects dominate the carrier scattering near the insulating substrates (≤∼120 nm), and grain-size determined by bulk nucleation dominates the grain-boundary scattering of thick films (≥∼200 nm). Consequently, we obtained the maximum mobilities in samples with a Sn concentration of 2% and a film thickness of 200 nm. The effect of increasing the grain-size of poly-GeSn by lowering the annealing temperature was also clarified. By combining these results, a very high carrier mobility of 320 cm²/Vs was obtained at a low temperature of 380 °C. This mobility is about 2.5 times as high as previously reported data for Ge and GeSn films grown at low temperatures (≤500 °C). Our technique therefore opens up the possibility of high-speed TFTs for use in the next generation of electronics.

DOI： 10.1063/1.4971825

記述言語：英語  

記述言語：英語  

記述言語：英語  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

We demonstrate the crystallization of thermally deposited amorphous germanium (Ge) microstrips on single layer graphene (SLG) by rapid melting growth. Lateral growth of large grain crystalline Ge was successfully obtained over entire microstrip structure. SLG has shown its capability to suppress the spontaneous nucleation in the melting Ge, where no or less intermixing of C and Ge atoms has been detected. The interaction of C atoms from the graphene and Ge atoms at the interface is the possible reason for the observation of large compressive strain generated in the Ge strip grown on SLG. This technique provides an innovative breakthrough towards the realization of single-crystalline Ge-on-insulator (GOI) structure on SLG to facilitate the next-generation ultra-large-scale integrated circuits (ULSIs) with multifunctionalities.

DOI： 10.1016/j.matlet.2016.05.007

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

A low-temperature formation technique of Sn-doped Ge on insulator has been investigated by aluminum-induced crystallization using a-GeSn/Al stacked structures. For a-GeSn films (Sn concentration: 2%), the layer-exchange growth temperature is significantly decreased compared with a-Ge, which enables low temperature growth at 250°C. At such a low temperature, bulk nucleation of GeSn in Al layers is significantly suppressed, and (100)-oriented interface nucleation becomes dominant. On the other hand, growth rate becomes high by Sn-doping effects. As a result, formation of (100)-oriented large-grain (>10 μm) Sn-doped Ge (Sn concentration: 2%) crystals on insulating substrates becomes possible at a low temperature (250°C). This technique will be useful to realize advanced flexible electronics.

DOI： 10.1109/AM-FPD.2016.7543662

記述言語：英語   掲載種別：研究論文（学術雑誌）  

パルスレーザアニール法におけるパルス数を制御し、絶縁膜上におけるGeSn結晶の低温成長を実現。次世代フレキシブル・エレクトロニクスの実現を加速する重要な成果である。

DOI： dx.doi.org/10.1063/1.4955059

記述言語：英語   掲載種別：研究論文（学術雑誌）  

We demonstrate the crystallization of the microstrips of electrodeposited amorphous germanium (Ge) on graphene on insulator by rapid melting growth for the first time. Growth of single-crystalline Ge microstrips with (111) orientation was confirmed. The high level of compressive strain was found to be resulted from the intermixing of C atoms from multilayer graphene (MLG) and Ge. Probably the introduction of local C atom into Ge film enhances nucleation of Ge on MLG, which results in (111)-oriented Ge nuclei. Subsequent lateral growth enables crystallization of Ge with (111) orientation on the entire microstrip. The results also indicate that graphene is very useful to suppress the spontaneous nucleation in the melting Ge films and the lattice rotation or misorientation. This novel and innovative technique provides a breakthrough towards the realization of high quality Ge-on-insulator structures to facilitate the next-generation ultra-large-scale integrated circuits (ULSIs) with multifunctionalities.

DOI： 10.1016/j.matlet.2016.01.056

記述言語：英語  

DOI： dx.doi.org/10.1016/j.tsf.2015.10.057

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Orientation-controlled large-grain (≥10 μm) crystal, i.e., quasi-single crystal, Ge-rich (≥50%) SiGe on insulator grown at low temperatures (≤300 °C) are desired for realization of high-performance flexible electronics. To achieve this, the Au-induced crystallization technique using a-SiGe/Au stacked structures has been developed. This enables formation of (111)-oriented large-grain (≥10 μm) Si_1-xGe_x (x ≥ 0.5) crystals on insulating substrates at low temperatures (300 °C). The surface layers of the grown SiGe crystals have uniform lateral composition profiles. By using this technique, formation of quasi-single crystal Ge on flexible plastic sheets is demonstrated. This technique will be useful to realize highperformance flexible electronics.

DOI： 10.7567/JJAP.55.03CB01

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Low-temperature (≤ 300 °C) formation of orientation-controlled large-grain (≥ 10 μm) Ge-rich (≥ 50%) SiGe crystals on insulator are realized by the gold-induced layer-exchange technique. Stacked structures of a-Si_{1 - x}Ge_x (0 ≤ x ≤ 1)/Au/SiO₂ are employed as starting materials. Here, thin-Al₂O₃ layers are introduced as diffusion barrier at a-SiGe/Au interfaces to suppress random bulk-nucleation and make (111)-oriented interface-nucleation on SiO₂ dominant. For samples with Ge fraction of 80%-100%, (111)-oriented large-grains (≥ 10 μm) are obtained through layer-exchange during annealing at 250 °C. On the other hand, layer-exchange for Ge fraction of 50% does not proceed at 250 °C. This phenomenon is attributed to retardation of lateral growth by introduction of Si. To enhance lateral growth, increase of annealing temperature is examined. As a result, (111)-oriented large-grains (≥ 10 μm) are realized for SiGe with Ge fraction of 50%-100%, having uniform composition profiles, by annealing at 300 °C. This technique is very useful to realize high-performance flexible electronics, employing plastic substrates (softening temperature: ∼350 °C).

DOI： 10.1016/j.tsf.2015.10.057

記述言語：英語   掲載種別：研究論文（学術雑誌）  

GeSn with a high substitutional Sn concentration (> 7%) is an attractive direct band gap material for high-efficiency photodevices that can be merged with large-scale integrated circuits (LSIs). To achieve GeSn with high Sn concentration, low-temperature solid-phase epitaxy using amorphous-GeSn (a-GeSn) (Sn concentration: 10%-36%)/crystal-Ge (c-Ge) stacked structures was investigated. Solid-phase growth of GeSn was enhanced as Sn concentration was increased, which enabled epitaxial growth at very low temperature (150-200 °C). Interestingly, concentrations of substitutional Sn increased with decreasing growth temperature. As a result, epitaxial growth of GeSn with substitutional Sn concentrations of ~ 8% was achieved by decreasing the growth temperature to 150 °C using a-GeSn (Sn concentration: 36%)/c-Ge stacked structures. This technique is expected to be useful to realize multi-function LSIs, where high-efficiency photodevices are integrated with transistors.

DOI： 10.1016/j.tsf.2015.09.069

記述言語：英語  

DOI： 10.1016/j.tsf.2015.09.069

記述言語：英語  

触媒誘起成長法を用いて、絶縁膜上における方位制御された大面積SiGe結晶の低温成長を実現。次世代フレキシブル・エレクトロニクスの実現を加速する重要な成果である。

記述言語：その他   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

A technique for low-temperature (≤300°C) formation of largegrain (≥10 μm) Ge-rich SiGe crystals on insulator, whose orientation and position are controlled, should be developed to realize flexible electronics. To achieve this, the gold-induced layerexchange crystallization technique using a-SiGe/Au stacked structures has been investigated. By introduction of diffusion control layers into the a-SiGe/Au interface, (111)-oriented largegrain Ge-rich SiGe crystals are achieved on insulating substrates at low temperatures (≤300°C). Moreover, position control of largegrain crystals becomes possible by patterning the diffusion control layers. This low-temperature growth technique is expected to be useful to realize flexible electronics.

DOI： 10.1149/07510.0095ecst

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Formation of position-controlled large-grain (10 m) Ge crystals on insulator is realized at low-temperature (300C) by goldinduced-crystallization using a-Ge/Au stacked structures. By introduction of diffusion barriers, i.e., thin-Al2O3 layers (2 nm thickness), having open-windows (3-20 m diameter) into the a-Ge/Au interfaces, Ge crystals are selectively grown from the open windows. For open-windows with diameter of 20 m, the grown areas consist of several Ge (111) grains. This is attributed to that several nuclei acting as seed are generated around the perimeters of the open windows. The number of seeds is linearly decreased by decreasing of the open-window diameter. As a result, (111)-oriented large (10 m) Ge single-crystals, without any grain boundary, are obtained at controlled positions for open-windows with diameter of 3 m. This technique will facilitate realization of flexible electronics and 3-dimensional large-scale integrated circuits, where Ge-based functional high-performance thin-film devices are integrated on flexible plastic substrates and/or amorphous insulating layers.

DOI： 10.1149/2.0161603jss

記述言語：英語  

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Crystallization of Ge_1-xSn_x (0.1≤x≤0.2) on quartz substrate by pulsed laser annealing was investigated. Substitutional Sn concentration increase with decreasing pulse number. As a result, GeSn crystals with very high substitutional Sn concentration (∼12%) has been realized for the sample (initial Sn concentration: 15%) with a single shot. These results were attributed to the nonthermal equilibrium growth with higher cooling rate by decreasing pulse number. This technique is expected for application to highspeed thin-film-transistors and high-efficiency optical devices.

DOI： 10.1149/07510.0109ecst

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Low-temperature formation of Sn-doped Ge on insulator is desired to realize next generation flexible electronics. To achieve this, metal-induced crystallization (MIC) of a-GeSn layers on insulating substrates is investigated using Au as a catalyst metal. For a-GeSn with initial Sn concentration of 5%, Sn-doped Ge is laterally grown around Au patterns at low temperatures (≤250°C). The Sn concentration (0.5-2.0%) in the grown layers can be controlled by the annealing temperature in the range of 150-250°C.

DOI： 10.1149/07510.0105ecst

記述言語：英語  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

To realize next-generation flexible thin-film devices, solid-phase crystallization (SPC) of amorphous germanium tin (GeSn) films on insulating substrates combined with seeds formed by laser annealing (LA) has been investigated. This technique enables the crystallization of GeSn at controlled positions at low temperature (∼180°C) due to the determination of the starting points of crystallization by LA seeding and Sn-induced SPC enhancement. The GeSn crystals grown by SPC from LA seeds showed abnormal lateral profiles of substitutional Sn concentration. These lateral profiles are caused by the annealing time after crystallization being a function of distance from the LA seeds. This observation of a post-annealing effect also indicates that GeSn with a substitutional Sn concentration of up to ∼10% possesses high thermal stability. These results will facilitate the fabrication of next-generation thin-film devices on flexible plastic substrates with low softening temperatures (∼250°C).

DOI： 10.1063/1.4939109

記述言語：英語  

レーザアニール法によるSn溶融シード形成技術とGeSn固相成長技術を融合し、絶縁膜上における大面積GeSn結晶の低温成長を実現。次世代フレキシブル・エレクトロニクスの実現を加速する重要な成果である。

記述言語：英語  

GeSn相図における固液共存温度領域で、GeSn/Si積層構造を熱処理することでSiGe混晶の低温形成を実現。Ⅳ族混晶系の新しい低温成長プロセスの可能性を見いだした。次世代エレクトロニクスの実現を加速する重要な成果である。

DOI： 10.1063/1.4929878

記述言語：英語  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Ultra-low temperature (≤300 °C) growth of Ge-rich SiGe on Si substrates is strongly desired to realize advanced electronic and optical devices, which can be merged onto Si large-scale integrated circuits (LSI). To achieve this, annealing characteristics of a-GeSn/c-Si structures are investigated under wide ranges of the initial Sn concentrations (0%-26%) and annealing conditions (300-1000 °C, 1 s-48 h). Epitaxial growth triggered by SiGe mixing is observed after annealing, where the annealing temperatures necessary for epitaxial growth significantly decrease with increasing initial Sn concentration and/or annealing time. As a result, Ge-rich (∼80%) SiGe layers with Sn concentrations of ∼2% are realized by ultra-low temperature annealing (300 °C, 48 h) for a sample with the initial Sn concentration of 26%. The annealing temperature (300 °C) is in the solid-liquid coexisting temperature region of the phase diagram for Ge-Sn system. From detailed analysis of crystallization characteristics and composition profiles in grown layers, it is suggested that SiGe mixing is generated by a liquid-phase reaction even at ultra-low temperatures far below the melting temperature of a-GeSn. This ultra-low-temperature growth technique of Ge-rich SiGe on Si substrates is expected to be useful to realize next-generation LSI, where various multi-functional devices are integrated on Si substrates.

DOI： 10.1063/1.4929878

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Low-temperature (≤300°C) formation of orientation-controlled large-grain (≥10 μm) SiGe crystals on insulator is desired for realization of advanced flexible electronics. To achieve this, the Au-induced crystallization technique using a-SiGe/Au stacked structures has been developed. Consequently, (111)-oriented large-grain (>10 μm) SiGe crystals are achieved on insulating substrates at low temperatures (∼300°C). The grown SiGe crystals have uniform composition profiles. This technique will be useful to realize advanced flexible electronics.

DOI： 10.1109/AM-FPD.2015.7173225

記述言語：英語  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Formation of large-grain (≥30 μm) Ge crystals on insulating substrates is strongly desired to achieve high-speed thin-film transistors. For this purpose, we propose the methods of Sn-doping into amorphous-Ge combined with rapid-thermal-annealing (RTA) in the solid-liquid coexisting temperature region for the Ge-Sn alloy system. The densities of micro-crystal-nuclei formed in this temperature region become low by tuning the RTA temperature close to the liquidus curve, which enhances the lateral growth of GeSn. Thanks to the very small segregation coefficient of Sn, almost all Sn atoms segregate toward edges of the stripes during growth. Agglomeration of GeSn degrades the surface morphologies; however, it is significantly improved by lowering the initial Sn concentration. As a result, pure Ge with large crystal grains (∼40 μm) with smooth surface are obtained by optimizing the initial Sn concentration as low as 3 ∼ 5%. Lateral growth lengths are further increased through decreasing the number of nuclei in stripes by narrowing stripe width. In this way, high-crystallinity giant Ge crystals (∼200 μm) are obtained for the stripe width of 3 μm. This "Si-seed free" technique for formation of large-grain pure Ge crystals is very useful to realize high-performance thin-film devices on insulator.

DOI： 10.1063/1.4922266

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

A low-temperature (≤300°C) growth technique of quasi-single crystal, i.e., orientation-controlled large-grain (≥10 μm), Ge-related semiconductors, on insulator is desired for realization of advanced flexible electronics. To achieve this, we have developed the gold-induced layer-exchange crystallization technique using a-SiGe/Au stacked structures. By introduction of a diffusion barrier with appropriate thickness into the a-SiGe/Au interface, (111)-oriented quasi-single crystal SiGe is achieved on insulating substrates at low temperatures (∼300°C). Based on these results, this technique is developed to form quasi-single crystal Ge on flexible plastic sheets. The grown layers have high carrier mobility, because residual Au hardly deteriorates the electrical properties of grown layers due to the low solubility of Au in Ge. This technique will facilitate the realization of advanced flexible electronics.

DOI： 10.1149/06910.0021ecst

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Solid-phase crystallization (SPC) of amorphous-GeSn (a-GeSn) films on insulating substrates has been developed combining with laser-anneal seeding, to realize next generation thin-film devices. By this technique, we have realized crystallization of GeSn (>10%) at low temperatures (∼180°C), which is applicable to flexible thin-film devices on low cost plastic substrates with low softening temperatures (∼200°C). In addition, the starting point of crystallization can be controlled by seeding, which is a big advantage in circuit designing.

DOI： 10.1149/06905.0301ecst

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

To realize high-speed thin film transistors, we investigated formation of Ge_1-xSn_x (0蠆x蠆0.2) crystals on quartz by pulsed laser annealing. The process-window necessary for crystallization was found to be significantly expanded by introducing Sn, i.e., 16 mJ/cm² for Ge, ∼130 mJ/cm² for GeSn. Moreover, Ge_0.8Sn_0.2 samples had high substitutional Sn concentration (∼7%) after the growth. These results are expected to be useful to realize highspeed thin film transistors and multi-functional devices.

DOI： 10.1149/06905.0297ecst

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Low-temperature (≤250°C) solid-phase crystallization of amorphous-GeSn films (Sn-concentration: 20%-30%, thickness: 30-100 nm) on insulating-substrates are investigated. As a result, we have realized high growth-rate (∼13 μm/h) for samples (film-thickness: 100 nm, initial Sn-concentration: 30%) at surprisingly low-temperature (150°C), which is very useful to realize flexible thin-film transistors. During this study, we encountered interesting phenomena that growth rates significantly decrease with decreasing filmthickness. In addition, substitutional Sn-concentrations in grown layers increased with decreasing film thickness. These phenomena are attributed to change in bond arrangement processes caused by interface. This technique is expected to facilitate next generation flexible thin-film transistors.

DOI： 10.1149/2.0021512ssl

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Sn溶融シード形成技術とGeSn固相成長技術を融合し、絶縁膜上における大面積GeSn結晶の低温成長を実現。次世代フレキシブル・エレクトロニクスの実現を加速する重要な成果である。

DOI： doi.org/10.1063/1.4902344

記述言語：英語   掲載種別：研究論文（学術雑誌）  

To produce high-performance devices on flexible plastic substrates, it is essential to form Ge-based group IV semiconductors on insulating substrates at low temperatures (≤250°C). We have developed a technique for solid phase crystallization of amorphous GeSn (≤220°C) enhanced by Sn doping, and combined with a seeding technique induced by Sn melting (∼250°C). This combination produces lateral crystallization of amorphous GeSn from seed arrays with no incubation time. As a result, extremely high growth velocities at 220°C, depending on Sn concentration, e.g., 0.13μm/h (14% Sn) and 1100μm/h (23% Sn), are achieved. These velocities are 10⁴-10⁸ times higher than that of pure Ge. This technique enables growth of crystalline GeSn island arrays (diameters: 50-150μm) at low temperatures (≤250°C) at controlled positions on insulating substrates.

DOI： 10.1063/1.4902344

記述言語：英語   掲載種別：研究論文（学術雑誌）  

アルミニウム誘起成長法を用い、ガラス基板上における結晶方位の制御されたSi多結晶薄膜の低温形成を実現。次世代薄膜デバイスの実現を加速する重要な成果である。

DOI： doi.org/10.1063/1.4901262

記述言語：英語   掲載種別：研究論文（学術雑誌）  

種結晶を用いない溶融成長法を高度化し、絶縁膜上に均一組成を有する大粒径SiGe結晶を実現。Si-LSIと混載可能な高性能SiGeデバイスの基盤技術の創出であり、次世代エレクトロニクスの実現を加速する重要な成果である。

DOI： doi: 10.1063/1.4895512

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Large-grain SiGe-crystal-on-insulator is essential for fabrication of devices such as advanced thin film transistors and/or photosensors. For these purposes, rapid-melting growth of amorphous SiGe stripes (7%-20% Si concentration) on insulating substrates is investigated over a wide range of cooling rates (from 2 to 17 °C/s). The growth features of SiGe change dynamically, depending on the cooling rate. A low cooling rate produces large crystals with laterally graded Si concentration profiles caused by significant Si segregation during solidification. In contrast, a high cooling rate suppresses the Si segregation, but small grains form because of high spontaneous nucleation under super-cooling conditions. By tuning of the cooling rate, moderate super-cooling conditions are obtained as a function of the Si concentration. This controls both the Si segregation and the spontaneous nucleation, and produces large SiGe crystals (∼400μm length, 7%-20% Si concentration) with three-dimensionally uniform Si profiles.

DOI： 10.1063/1.4895512

記述言語：英語  

DOI： 10.1149/2.0011411jss

記述言語：英語   掲載種別：研究論文（学術雑誌）  

フレキシブルなプラスチックシート上に、方位制御された大粒径Ge結晶を実現。電気特性を評価し、高いキャリヤ移動度を実証。プラスチック上に多機能を有する異種デバイスを混載する基盤技術の創出であり、次世代エレクトロニクスの実現を加速する重要な成果である。

DOI： http://dx.doi.org/10.1063/1.4885716

記述言語：英語   掲載種別：研究論文（学術雑誌）  

High-carrier-mobility semiconductors on flexible-plastic are essential to realize flexible electronics, for this purpose, electrical properties of orientation-controlled large-grain Cie crystals on flexible-plastic dircctly formed by nucleation-controlled gold-induced-crystallization (GIC) are examined, and compared with those obtained by aluminum-induced-crystallization (AIC). The Ge crystals show p- Type conductions. Here, hole concentrations are 2.2 x10¹⁷ and 5.8 x 10²⁰cm ³ for GIC-Ge and AIC-Ge, respectively, which are explained on the basis of the solubility of Au and AL in Ge. Thanks to the low hole concentration, GIC-Ge shows high hole mobility (160cm²V^-1 'S^-1') compared with AIC-Ge (37cm²V^-1 'S^-1'). These demonstrate significant advantage of GIC to realize high-performance flexible-electronics.

DOI： 10.1063/1.4885716

記述言語：英語  

DOI： 10.1016/j.tsf.2013.08.123

記述言語：日本語   掲載種別：研究論文（学術雑誌）  

Low-temperature (≤250℃) formation technique of orientation-controlled large-grain Ge thin films on insulator is desirable for realization of advanced flexible electronics. To achieve this, the Au-induced crystallization technique combined with inter-diffusion-control and interface-energy-modulation techniques has been investigated. Consequently, selective formation of (100) or (111)-oriented large-grain (>20 μm) Ge crystals on insulator have been realized. Moreover, formation of (111)-oriented large-grain Ge crystals directly on plastic substrates is demonstrated. This technique facilitates realization of future flexible electronics.

記述言語：日本語   掲載種別：研究論文（学術雑誌）  

Low-temperature (≤250℃) formation technique of orientation-controlled large-grain Ge thin films on insulator is desirable for realization of advanced flexible electronics. To achieve this, the Au-induced crystallization technique combined with inter-diffusion-control and interface-energy-modulation techniques has been investigated. Consequently, selective formation of (100) or (111)-oriented large-grain (>20 μm) Ge crystals on insulator have been realized. Moreover, formation of (111)-oriented large-grain Ge crystals directly on plastic substrates is demonstrated. This technique facilitates realization of future flexible electronics.

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Low-temperature formation (∼ 150 °C) of Ge films on insulator is investigated for realization of advanced flexible devices. We propose utilization of Sn as catalyst to enhance the crystallization at low-temperatures. By annealing (150-200 °C) of a-Ge/Sn stacked structures formed on insulators, the composition distributions of Ge/Sn layers are inverted, and Sn/poly-Ge stacked structures are obtained. The results demonstrate that the crystallization occurs at 150 °C, which is slightly below the eutectic temperatures. This Sn-induced crystallization technique is useful to obtain poly-Ge on low-cost flexible substrates (softening temperature: ∼ 200 °C).

DOI： 10.1016/j.tsf.2013.08.123

記述言語：英語   掲載種別：研究論文（学術雑誌）  

High-quality Ge-on-insulator (GOI) structures are essential to realize next-generation large-scale integrated circuits, where GOI is employed as active layers of functional devices, as well as buffer layers for epitaxial growth of functional materials. In line with this, in-depth analysis of crystallinity of rapid-melting-grown GOI is performed. Structural and electrical measurements combined with a thinning technique reveal that the crystallinity of GOI (500 nm thickness) is very high and uniform in-depth direction, where high hole mobility (∼ 1000 cm²/V s) is achieved throughout the grown layers. These findings open up a possibility of application of rapid-melting-grown GOI to various advanced functional devices.

DOI： 10.1016/j.tsf.2013.08.035

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Dynamics in rapid-melting growth are analyzed by using Si-segregation phenomena in SiGe-on-insulator (SGOI). To clarify growth-stream and growth-velocity, SiGe profiles in SGOI network and stripe structures are investigated. Based on 2-dimensional Si-concentration mapping for SGOI network, visualization of routes of growth fronts becomes possible. In addition, analysis of Si concentration profiles in SGOI stripes enables evaluation of growth velocity. It is clarified that growth velocity increases by 15 times with increasing growth distance for SGOI stripe with 500 μm length. These techniques are useful to understand detailed kinetics in rapid-melting growth.

DOI： 10.1016/j.tsf.2013.08.129

記述言語：英語   掲載種別：研究論文（学術雑誌）  

In rapid-melting-crystallization of network Ge-on-insulator (GOI), coalescence of growth-fronts inevitably occurs. To clarify crystallinity of the coalesced regions of two growth-fronts in GOI stripes, scanning electron microscopy and transmission electron microscopy analyses are performed. These analyses reveal that lattice planes of two growth-fronts coherently align without strains for short growth-distance (≤ 5 μm). The lattice planes at growth-fronts start to tilt gradually for growth-distance above 5 μm. For intermediate growth-distance (5-150 μm), slightly-tilting lattice-planes coherently align without generating any defects, where locally-distributed strains are induced in the coalesced regions. On the other hand, for long growth-distance (≥ 150 μm), grain-boundaries are generated in coalesced regions, and the locally-distributed strains are relaxed. The coherent lattice-alignment for growth-distance below 150 μm is attributed to atomic reordering in the coalesced regions, where coalescence occurs at high temperatures around the solidification point of Ge.

DOI： 10.1016/j.tsf.2013.08.127

記述言語：英語  

DOI： 10.1016/j.tsf.2013.08.035

記述言語：英語  

DOI： 10.1016/j.tsf.2013.08.127

記述言語：英語  

DOI： 10.1016/j.tsf.2013.08.129

記述言語：英語  

DOI： 10.1149/2.003405ssl

記述言語：英語  

記述言語：英語  

記述言語：英語  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Orientation-controlled large-grain Ge crystals grown on plastic substrates (softening temperature: 300 °C) are desired to realize advanced flexible electronics, where various functional devices are integrated on flexible substrates. To achieve this, gold-induced crystallization (annealing temperature: 250 °C) using a-Ge/Au stacked structures is developed on plastic substrates, where thin-Al2O3 layers (thickness: 7 nm) are introduced at a-Ge/Au interfaces. Interestingly, (111)-oriented nucleation at the Au/plastic interface dominates over random bulk nucleation in Au layers. As a result, the formation of (111)-oriented large-grain (;50 um) Ge crystals directly on flexible plastic substrates is realized. This technique will pave the way for advanced flexible electronics.

DOI： 10.7567/JJAP.53.020302

記述言語：英語   掲載種別：研究論文（学術雑誌）  

不定型なプラスチック基板上における方位制御された大粒径Ge結晶の低温成長を実現。フレキシブルなプラスチック上に多機能を有する異種デバイスを混載する基盤技術の創出であり、次世代エレクトロニクスの実現を加速する重要な成果である。

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Development of a low-temperature (≤250°C) formation technique of orientation-controlled large-grain (<10 μm) SiGe on insulator is essential to realize flexible electronics, where various advanced devices are integrated on flexible plastic substrates (softening temperature: ~300°C). This is because SiGe provides higher carrier mobility and superior optical properties compared with Si, as well as epitaxial template of various functional materials. In line with this, we have been developing metal-induced crystallization of SiGe. This achieves selectively (100)- or (111)-oriented large-grain (≥20 μm) SiGe at low temperatures (~250°C) [1-4]. Present paper reviews our recent progress in this novel growth technique.

DOI： 10.1109/ISTDM.2014.6874633

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

To develop a new low-temperature crystallization technique, annealing characteristics of a-GeSn/Si(100) structures are investigated. It is revealed that epitaxial growth accompanying Si-Ge mixing is generated at temperatures in the liquid-solid coexisting region of the Ge-Sn system. The annealing temperature necessary for epitaxial growth is significantly decreased by increasing annealing time and/or Sn concentration. Consequently, epitaxial growth at 300°C becomes possible. These findings are expected to be useful to realize next-generation large-scale integrated circuits, where various multi-functional devices are integrated.

DOI： 10.4028/www.scientific.net/AMM.481.137

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Formation of SiGe crystals with large-grain on insulating-substrates is desired to achieve high-speed thin-film-transistors (TFT). We examine rapid-thermal annealing (950-1100°C) of a-Si_0.15Ge_0.85-stripe (2-15-μm-stripe-width) on insulator structures in solid-liquid-coexisting temperature-region. Formation of Si-rich micro-crystal-nuclei during annealing is clearly evidenced, where Si concentration and areal-density of micro-crystals are uniquely determined by annealing-temperature. Such self-organized-seeding enables lateral rapid-melting-growth from micro-crystals during cooling. The micro-crystals density per-unit-length is proportional to stripe-width, which results in enlargement of lateral-growth-length by narrowing stripe-width. Consequently, giant-lateral-growth of SiGe grains (∼300-μm-length, 0-40%-Si-concentration) are achieved for narrow-stripe-width of 2 μm at 1050°C. This technique facilitates advanced TFT for high-performance system-in-displays.

DOI： 10.1149/2.003405ssl

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

A low-temperature (≤250^oC) formation technique of orientation-controlled large-grain Ge thin films on insulator is desirable for realization of advanced flexible electronics. To achieve this, the Au-induced crystallization technique combined with inter-diffusion-control and interface-energy-modulation techniques has been investigated. Consequently, selective formation of (111)-or (100)-oriented large-grain (>20 μm) Ge crystals on insulator have been realized. Moreover, formation of (111)-oriented large-grain Ge crystals directly on plastic substrates is demonstrated. This technique facilitates realization of future flexible electronics.

DOI： 10.1109/AM-FPD.2014.6867200

記述言語：英語   掲載種別：研究論文（学術雑誌）  

To realize next generation thin-film-transistors (TFTs), seedless rapidmelting growth of Ge on insulator is investigated. By rapid-thermal annealing (RTA) of amorphous GeSn (a-GeSn) layers on insulating substrates at a temperature between the solidification point and the melting point, GeSn layers melt incompletely, which generates a limited number of solid nuclei as residue. Once cooling starts, liquid-phase epitaxial growth occurs from these nuclei, which results in growth of large-grain crystals. Since segregation coefficient of Sn in Ge is very small (∼0.02), almost all Sn atoms segregate at edges of the grown regions. As a result, almost Snfree (≤1%) large Ge crystal grains are achieved on insulating substrates by a self-organizing process.

DOI： 10.1149/06103.0097ecst

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Rapid-melting growth of SiGe stripes on insulator without crystal-seed has been investigated. After rapid-thermal annealing (RTA) of amorphous SiGe stripes (~5 μm) at a temperature between melting-point and solidification-point, SiGe crystals with large lateral sizes (~20 μm) are formed. The Si concentrations in the grains show peaks at the center of the grains and gradually decrease toward the grain boundaries. These phenomena are explained based on the self-organized formation of Si-rich micro-crystals and subsequent Si-segregating lateral-growth during RTA.

DOI： 10.4028/www.scientific.net/AMM.481.27

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

By an insertion of a Ge(Sn) layer and its CMP treatments, we have improved the crystalline and magnetic characteristics of one of the Heusler-compounds, Fe₃Si, on (111)-oriented Ge on a flexible substrate. This work is a first step of high-performance flexible spintronics for flexible system-in-display devices.

DOI： 10.1109/ISTDM.2014.6874683

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Orientation-controlled crystalline Si films on insulating substrates are strongly required to achieve high-performance thin-film devices for next-generation electronics. We have comprehensively investigated the layer-exchange kinetics of Al-induced crystallization (AIC) in stacked structures, i.e., amorphous-Si/Al-oxide/Al/SiO
₂
-substrates, as a function of the air-exposure time of Al surfaces (t
_air
: 0-24 h) to form Al-oxide interface-layers, the thickness of Al and Si layers (d
_Al
, d
_Si
: 50-200 nm), the annealing temperature (450-500°C), and the annealing time (0-50 h). It has been clarified that longer t
_air
(>60 min) and/or thinner d
_Al
and d
_Si
(<50 nm) lead to the (111) oriented growth; in contrast, shorter t
_air
(<60 min) and/or thicker d
_Al
and d
_Si
(>100 nm) lead to the (100) oriented growth. No correlation between the annealing temperature and the crystal orientation is observed. Detailed analysis reveals that the layer-exchange kinetics are dominated by "supply-limited" processing, i.e., diffusion of Si atoms into Al layers through Al-oxide layer. Based on the growth rate dependent Si concentration profiles in Al layers, and the free-energy of Si at Al-oxide/Al or Al/SiO
₂
interfaces, a comprehensive model for layer-exchange growth is proposed. This well explains the experimental results of not only Si-AIC but also another material system such as gold-induced crystallization of Ge. In this way, a growth technique achieving the orientation-controlled Si crystals on insulating substrates is established from both technological and scientific points of view.

DOI： 10.1063/1.4901262

記述言語：その他   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Low-temperature annealing (450-700°C) of a-Ge/Sn/c-Ge stacked-structures is examined to achieve high-quality GeSn singlecrystals on Ge substrates. Abnormal phenomena, where a GeSn-layer travels toward the surface during annealing, were found. In-depth analyses of Sn distribution together with epitaxial-growth clarify the mechanisms, i.e., diffusion of Ge atoms from a-Ge into molten-Sn, and subsequent release of GeSn atoms into c-Ge substrates cause the traveling-zone-melting-growth in self-organizingmanner. Transmission- electron-microscopy observation reveals the defect-free GeSn layers on Ge substrates. High thermal-stability of non-equilibrium Sn concentration in GeSn is guaranteed by post-annealing (~600°C) experiments. This method provides the unique tool to achieve multi-functional-devices based on GeSn-related hetero-structures.

DOI： 10.1149/2.0011411jss

記述言語：英語   掲載種別：研究論文（学術雑誌）  

The effects of annealing temperatures on composition and strain in Si_xGe_1-x, obtained by rapid melting growth of electrodeposited Ge on Si (100) substrate were investigated. Here, a rapid melting process was performed at temperatures of 1000, 1050 and 1100 °C for 1 s. All annealed samples show single crystalline structure in (100) orientation. A significant appearance of Si-Ge vibration mode peak at ~400 cm-1 confirms the existence of Si-Ge intermixing due to out-diffusion of Si into Ge region. On a rapid melting process, Ge melts and reaches the thermal equilibrium in short time. Si at Ge/Si interface begins to dissolve once in contact with the molten Ge to produce Si-Ge intermixing. The Si fraction in Si-Ge intermixing was calculated by taking into account the intensity ratio of Ge-Ge and Si-Ge vibration mode peaks and was found to increase with the annealing temperatures. It is found that the strain turns from tensile to compressive as the annealing temperature increases. The Si fraction dependent thermal expansion coefficient of Si_xGe_1-x is a possible cause to generate such strain behavior. The understanding of compositional and strain characteristics is important in Ge/Si heterostructure as these properties seem to give significant effects in device performance.

DOI： 10.3390/ma7021409

記述言語：英語  

DOI： 10.1149/2.005303jss

記述言語：英語  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

High-quality Ge-on-insulator (GOI) is a key structure for integrating high-speed transistors and optical- and spintronic-devices on Si-platform. Effects of coalescence of two growth-fronts on crystallinity of GOI-stripes during rapid-melting lateral-crystallization are investigated as a function of growth-distance. For long growth-distance (≥150 μm), grain-boundaries are generated in coalesced regions due to tilting growth-fronts (1-3°). On the other hand, for short distance (≤5 μm), lattice-structures coherently align without strains. Moreover, for intermediate distance (5-150 μm), lattice-structures of growth-fronts coherently align without any defects, though heterogeneous lattice-strains are locally induced due to slightly tilting growth-fronts (∼0.5°). Such atomically-coherentcoalescence for growth-distance <150 μm shows significant advantage of rapid-melting-crystallization over vapor and solid-phase techniques.

DOI： 10.1149/2.005303jss

記述言語：英語   掲載種別：研究論文（学術雑誌）  

不定型な絶縁基板上における方位制御された大粒径Ge結晶の低温成長を実現。プラスチック上に多機能を有する異種デバイスを混載する基盤技術の創出であり、次世代エレクトロニクスの実現を加速する重要な成果である。

DOI： http://dx.doi.org/10.1063/1.4819015

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Selective formation of Ge(100) and (111) on amorphous-insulator at low-temperatures (∼250 °C) is realized through gold-induced- crystallization using a-Ge/Au/SiO₂ stacked-structures by combining interface-energy-modulation of substrates. Introduction of thin-Al ₂O₃ layers (∼7 nm thickness) at a-Ge/Au interfaces enables large-grain (≥20 μm) Ge(111) formation, which is speculated to be due to suppression of random bulk-nucleation and domination of (111)-oriented interface-nucleation on SiO₂. To examine this speculation, Al ₂O₃-covered substrates are employed. This results in formation of Ge(100), due to energetically favorable (100)-oriented interface-nucleation on Al₂O₃. Consequently, large-grain (≥20 μm) Ge(100) and (111) are achieved on amorphous-insulators at 250 °C. This technique is very useful to realize flexible-electronics.

DOI： 10.1063/1.4819015

記述言語：英語   掲載種別：研究論文（学術雑誌）  

(111)-oriented Ge-on-insulator (GOI) is the key material structure for next generation multifunctional large scale integrated circuits. The (111) GOI structure can be implemented for high-speed transistor channels, as well as templates for the integration of optoelectronic and spintronic materials on the Si platform. The rapid melting growth technique is an effective way to obtain high-quality GOI structures on Si substrates. However, in formation of GOI strips (width: ∼3 μm, thickness: 100 nm) from Si(111) seed, rotation of crystal orientation occurs along <112> growth direction. In this study, we investigate the effects of GOI pattern-dimensions on orientation stability and demonstrate the suppression of crystal rotation by narrowing the strip width. This enables the formation of (111) GOI strips with any growth direction.

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Orientation-controlled (111)Ge-on-insulator (GOI) is essential to achieve high-carrier-mobility channel of transistors and epitaxialtemplate of functional materials. To achieve (111)-oriented GOI stripes with any stripe-directions by rapid-melting growth from (111)-oriented Si-seed, effects of stripe-width on crystal-orientations of grown layers are investigated. For ∼2-μm-stripe- width, (111)-oriented GOI stripes are achieved for growth direction along (011). However, crystal-rotation is observed for (112) direction. Such rotational-growth along (112) is suppressed by decreasing stripe-width. Consequently, (111)-oriented GOI with any stripedirections are obtained for ∼0.5-μm-stripe-width, which is attributed to strain-relaxation by narrowing. This orientation-control technique facilitates next-generation large-scale-integrated-circuits, where various functional devices are integrated on Si-platform.

DOI： 10.1149/2.008309ssl

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Ge-on-insulator (GOI) having laterally-graded doping-profiles is essential to formation of functional-devices such as high-efficiency thermo-electric devices. To achieve this, rapid-melting growth of a-Ge strips implanted with P ions is investigated under a dose range of 1 × 10¹²-2 × 10¹⁵ cm-2. For dose over 1 × 1014 cm-2, grown-Ge layers show n-type conduction. Moreover, for dose of 2 × 10¹⁵ cm-2, a laterally-graded doping-profile (∼8 × 1015 cm^-3/μm) is achieved in the grown region (growth-distance: 0-300 μm) by P segregation during the melt-back process. The graded doping-profile generates electric-fields of -0.6 V/cm, which can be increased by decreasing strip-length. This technique is expected to facilitate integration of functional-devices on Si-platform.

DOI： 10.1149/2.002307ssl

記述言語：英語  

DOI： 10.1149/2.008309ssl

記述言語：英語   掲載種別：研究論文（学術雑誌）  

The low-temperature-crystallization effects of soft X-ray irradiation on the structural properties of amorphous Si and amorphous Ge films were investigated. From the differences in crystallization between Si and Ge, it was found that the effects of soft X-ray irradiation on the crystallization strongly depended on the energy band gap and energy level. The crystallization temperatures of the amorphous Si and amorphous Ge films decreased from 953 K to 853 K and 773 K to 663 K, respectively. The decrease in crystallization temperature was also related to atoms transitioning into a quasi-nucleic phase in the films. The ratio of electron excitation and migration effects to thermal effects was controlled using the storage-ring current (photon flux density). Therefore, we believe that low-temperature crystallization can be realized by controlling atomic migration through electron excitation.

DOI： 10.1016/j.tsf.2013.02.129

記述言語：英語  

DOI： 10.1149/2.002307ssl

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Laterally-graded SiGe-on-insulator is the key-structure for next-generation Si-technology, which enables advanced device-arrays with various energy-band-gaps as well as 2-dimensional integration of functional-materials with various lattice-constants. Segregation kinetics in rapid-melting growth of SiGe stripes are investigated in wide ranges of stripe-lengths (10-500μm) and cooling-rates (10-19℃/s). Universal laterally-graded SiGe-profiles obeying Scheil-equation are obtained for all samples with low cooling-rate (10℃/s), which enables robust designing of lateral-SiGe-profiles. For samples with high cooling-rates and long stripe-lengths, anomalous two-step-falling profiles are obtained. Dynamical analysis considering the growth-rate-effects enables comprehensive understanding of such phenomena. This provides the unique tool to achieve modulated lateral-SiGe-profiles beyond Scheil-equation.

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Laterally-graded SiGe-on-insulator is the key-structure for next-generation Si-technology, which enables advanced device-arrays with various energy-band-gaps as well as 2-dimensional integration of functional-materials with various lattice-constants. Segregation kinetics in rapid-melting growth of SiGe stripes are investigated in wide ranges of stripe-lengths (10-500μm) and cooling-rates (10-19℃/s). Universal laterally-graded SiGe-profiles obeying Scheil-equation are obtained for all samples with low cooling-rate (10℃/s), which enables robust designing of lateral-SiGe-profiles. For samples with high cooling-rates and long stripe-lengths, anomalous two-step-falling profiles are obtained. Dynamical analysis considering the growth-rate-effects enables comprehensive understanding of such phenomena. This provides the unique tool to achieve modulated lateral-SiGe-profiles beyond Scheil-equation.

記述言語：日本語  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

絶縁膜上における横方向組成傾斜型SiGe薄膜の積層構造の高品位形成を実現。Siプラットフォーム上に多機能を有する異種デバイスを混載する基盤技術の創出であり、次世代LSIの実現を加速する重要な成果である。

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Laterally and vertically modulated SiGe-on-insulator (SGOI) structures are essential to integrate functional device-arrays with various energy-band-gaps and/or lattice-constants. We develop the temperature-modulated successive rapid-melting-growth (RMG) method, where Si-concentration dependent RMG processing is combined with non-destructive crystallinity-analysis. First, SGOI is formed by segregation-controlled RMG of SiGe by using Si-substrate as crystalline-seed. Polarized-Raman-scattering measurements non-destructively reveal the lateral-epitaxial-growth of SGOI with graded SiGe-concentration profiles. Second, Ge-on-insulator (GOI) is stacked on SGOI by using SGOI as crystalline-seed, where RMG temperature is selected between the melting-points of Ge and underlying SGOI. This achieves defect-free, multiply-stacked GOI on graded-SGOI structure, which demonstrates 3-dimensionally modulated SiGe-concentration profiles on Si-platform.

DOI： 10.1063/1.4794409

記述言語：英語   掲載種別：研究論文（学術雑誌）  

GeSn alloys are attractive materials, with a potentially major impact on next-generation device applications due to the superior electrical properties and transition to direct band gap. We investigate growth of GeSn by annealing of a-Ge/Sn/c-Ge stacked structures. This achieves liquid-phase epitaxial growth of defectfree GeSn with non-equilibrium Sn concentration (∼2%) on Ge substrates by a low-temperature annealing (∼600°C). The nonequilibrium Sn concentration in this GeSn layers is guaranteed thermal stability for post-annealing at 600°C for 30 min.

DOI： 10.1149/05809.0179ecst

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Integration of Ge on the Si platforms is essential for the development of next generation large-scale integrated circuits. The Ge-on-insulator (GOI) structure is suited for the realization of high-mobility transistors channels and as epitaxial templates for optoelectronic and spintronic materials. In this work, the fabrication of thin (∼50 nm) (100) GOI by the rapid melting growth process has been investigated. Growth with unstable crystal orientation has been observed in wide (≥1 μm) GOI strips. However, orientation stabilized growth was achieved in narrow strips (∼0.5 μm). Further stabilization of growth orientation was observed in mesh patterned growth with GOI width of 1 μm. Epitaxial growth of Ge was performed on the above structures and the formation of uniform epitaxial layer was demonstrated.

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Low-temperature (≤250°C) formation of orientation-controlled large-grain (>10 μm) poly-SiGe on amorphous insulator is essential to realize flexible electronics. In line with this, metalinduced crystallization of SiGe is investigated. By employing Au and Sn as catalysts, SiGe crystallization at 250°C and 150°C, respectively, becomes possible. Moreover, a technique for formation of orientation-controlled large-grain crystals is examined by modulation of nucleation in gold-induced crystallization. This achieves selectively (100)-or (111)-oriented large-grain (≥20 μm) crystals on amorphous insulators. This technique is expected to facilitate integration of advanced functional devices onto flexible substrates.

DOI： 10.1149/05809.0213ecst

記述言語：英語   掲載種別：研究論文（学術雑誌）  

To develop a new low-temperature crystallization technique, annealing characteristics of a-GeSn/Si(100) structures are investigated. It is revealed that epitaxial growth accompanying Si-Ge mixing is generated at temperatures in the liquid-solid coexisting region of the Ge-Sn system. The annealing temperature necessary for epitaxial growth is significantly decreased by increasing annealing time and/or Sn concentration. Consequently, epitaxial growth at 300°C becomes possible. These findings are expected to be useful to realize next-generation large-scale integrated circuits, where various multi-functional devices are integrated.

DOI： 10.1149/05809.0257ecst

記述言語：英語   掲載種別：研究論文（学術雑誌）  

We report the crystallization of electrodeposited germanium (Ge) thin films on n-silicon (Si) (100) by rapid melting process. The electrodeposition was carried out in germanium (IV) chloride: propylene glycol (GeCl4:C3H8O2) electrolyte with constant current of 50 mA for 30 min. The measured Raman spectra and electron backscattering diffraction (EBSD) images show that the as-deposited Ge thin film was amorphous. The crystallization of deposited Ge was achieved by rapid thermal annealing (RTA) at 980 °C for 1 s. The EBSD images confirm that the orientations of the annealed Ge are similar to that of the Si substrate. The highly intense peak of Raman spectra at 300 cm-1 corresponding to Ge-Ge vibration mode was observed, indicating good crystal quality of Ge. An additional sub peak near to 390 cm-1 corresponding to the Si-Ge vibration mode was also observed, indicating the Ge-Si mixing at Ge/Si interface. Auger electron spectroscopy (AES) reveals that the intermixing depth was around 60 nm. The calculated Si fraction from Raman spectra was found to be in good agreement with the value estimated from Ge-Si equilibrium phase diagram. The proposed technique is expected to be an effective way to crystallize Ge films for various device applications as well as to create strain at the Ge-Si interface for enhancement of mobility.

DOI： 10.3390/ma6115047

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/IWJT.2013.6644498

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Orientation-controlled Si_1-xGe_x (0≤ x≤1) films on insulating substrates are essential to achieve high-efficiency solar-cells and highspeed thin-film-transistors. We investigate Al-induced crystallization of amorphous-Si_1-xGe_x/Al-oxide/Al/quartz stacked-structures as a function of Ge-fraction, air-exposure time of Al surfaces, and thicknesses of Al and SiGe films. By tuning interfacial Al-oxide layer thickness, which is controlled by air-exposure time, (100) or (111) Si_1-xGe_x (x < 0.2) layers are selectively formed. However, increase of Ge-fraction significantly enhances the random bulk-nucleation, which results in poly-crystalline Si_1-xGe _x (x ≥ 0.2) with random-orientations. To enhance interfacial-nucleation at Al/quartz over bulk-nucleation, film-thickness of Al and SiGe are thinned to 50 nm. This achieves (111)-oriented Si _1-xGe_x films with the whole Ge fractions. This oriented-growth can be explained by the theoretical calculation that (111) SiGe has the minimum surface energy on quartz substrates.

DOI： 10.1149/2.010203jss

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Single-crystal Ge layers on insulating films (GOI) are desired to achieve advanced 3-dimensional large-scale integrated circuits and high-performance thin-film transistors. We have developed the rapid-melting Ge growth seeded from Si substrates, which achieves chip-size (∼cm length) GOI structures with (100), (110), and (111) orientations. Driving force to initiate the lateral growth over insulating films is clarified as the solidification temperature gradient originating from melting-induced Si-Ge mixing. Combination with the artificial Si micro-seed techniques and the rapid melting growth enables the formation of hybrid-orientation GOI arrays, i.e., (100), (110), and (111) stripes, on (100) Si platform. High hole mobility (∼1000 cm²/Vs) in hybrid-orientation GOI is also demonstrated.

DOI： 10.1149/05005.0059ecst

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Laterally graded SiGe-on-insulator is the key-structure for next-generation Si-technology, which enables advanced device-arrays with various energy-band-gaps as well as 2-dimensional integration of functional-materials with various lattice-constants. Segregation kinetics in rapid-melting growth of SiGe stripes are investigated in wide ranges of stripe-lengths (10-500μm) and cooling-rates (10-19°C/s). Universal laterally graded SiGe-profiles obeying Scheil-equation are obtained for all samples with low cooling-rate (10°C/s), which enables robust designing of lateral-SiGe-profiles. For samples with high cooling-rates and long stripe-lengths, anomalous two-step-falling profiles are obtained. Dynamical analysis considering the growth-rate-effects enables comprehensive understanding of such phenomena. This provides the unique tool to achieve modulated lateral-SiGe-profiles beyond Scheil equation.

DOI： 10.1063/1.4769998

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Rapid-melting growth of SiGe stripes on insulator without any crystal-seed has been investigated. After rapid-thermal annealing (RTA) of amorphous SiGe stripes (~5 μm) at a temperature between melting-point and solidification-point, SiGe crystals with large lateral sizes (~20 μm) are formed. The Si concentrations in the grains show peaks at the center of the grains and gradually decrease toward the grain boundaries. These phenomena are explained based on the formation of Si-rich micro-crystals and subsequent Si-segregating lateral-growth during RTA.

DOI： 10.1149/05009.0431ecst

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Formation of laterally-graded single-crystal SiGe-on-insulator structures by rapid-melting-growth of a-SiGe is investigated. From micro-probe Raman scattering spectroscopy measurements, it is revealed that the Si concentration profiles in grown SiGe layers are significantly affected by the growth conditions and sample sizes. Based on the systematical analysis of the phenomena, effects of the growth rate on Si segregation kinetics in rapid-melting growth are clarified. These findings are expected to be useful to obtain epitaxial templates with laterally-variable lattice constants for 2-dimensional integration of various functional devices on an Si-platform.

DOI： 10.1149/05009.0747ecst

記述言語：英語   掲載種別：研究論文（学術雑誌）  

液相成長法による絶縁膜上における横方向組成傾斜型SiGe薄膜の高品位形成を実現。Siプラットフォーム上に多機能を有する異種デバイスを混載する基盤技術の創出であり、次世代LSIの実現を加速する重要な成果である。

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Single-crystal germanium-on-insulator (GOI) structures are essential to integrate high-speed transistors, high-efficiency solar cells, and non-volatile spintronic memories on a panel, because GOI structures can be used as templates for epitaxial growth of multi-functional materials, as well as channel layers with high-carrier mobility. We investigate formation of high-density nanostructured single crystalline GOI templates by SiGe-mixing-triggered rapid melting growth. The GOI structures consisting of dense strip-arrays and mesh-networks are examined. For strip-array patterns, rotation in crystal orientation along the growth direction is observed. However, such crystal rotation has been completely suppressed by employing mesh-network patterns. This enables high-density single-crystal GOI templates with narrow spacing (<500nm). Moreover, epitaxial growth of Ge on the GOI templates is examined by a molecular beam technique.

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

We investigated a low-temperature crystallization of a- Si and a-Ge films by the synchrotron radiation soft X-ray irradiation at storage-ring current of 25-220 mA. It is found that the crystallization temperatures of a-Si and a-Ge were decreased from 680 to 580°C and from 500 to 390°C. These decreasements relate effects of enhancement atomic migration via electron excitation at valence band and core level.

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Low-temperature (≤ 350°C) formation of orientation-controlled large-grain Ge on insulating substrates is essential to achieve advanced flexible devices employing plastic substrates. To achieve this, effects of interfacial-oxide layer insertion on gold-induced crystallization (GIC) of amorphous Ge films on insulating substrates have been investigated. Consequently, (111)-oriented large-grain (20-50 μm) Ge crystals are obtained at 350°C by inserting interfacial oxide layers. It is speculated that this phenomena is attributed to suppression of random bulk nucleation of Ge in Au films.

記述言語：英語  

DOI： 10.1149/05005.0059ecst

記述言語：英語  

DOI： 10.1149/05009.0431ecst

記述言語：英語  

DOI： 10.1149/05009.0747ecst

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Single-crystalline laterally graded GeSn-on-insulator (GeSnOI) structures are essential to achieve novel device-arrays with various direct-energy-band gaps, which can be merged with high-density Si large-scale-integrated-circuits. We investigate the seeding rapid-melting-growth of narrow stripes with a-Ge/Sn/a-Ge stacked-structures. This achieves laterally graded GeSn crystalline layers on Si substrates covered with SiO ₂ films. Stripe-length dependent GeSn lateral-profiles are quantitatively explained by Scheil equation, which enables precise designing of GeSn lateral-profiles. High-crystallinity GeSn stripes without dislocations or stacking faults are also demonstrated.

DOI： 10.1063/1.4748328

記述言語：英語  

DOI： 10.1149/2.010203jss

記述言語：英語   掲載種別：研究論文（学術雑誌）  

溶融成長時の偏析現象を利用し、絶縁膜上に組成傾斜を有するGeSn単結晶薄膜を実現した。成長と共に生じるSn偏析の挙動を明らかにすると共に、組成傾斜を制御する指針を明確化した。絶縁膜上における次世代半導体GeSn単結晶薄膜の高品位形成を実現する手法の確立であり、次世代LSIの実現を加速する重要な成果である。

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

We investigated crystallization mechanism of a-Si _0.5Ge _0.5 film by excimer-laser annealing (ELA) at energy density of 50-70mJ/cm ² in comparison with a method of synchrotron radiation soft X-ray irradiation at storage ring current of 50-220 mA. The nucleation mechanism of Si _0.5Ge _0.5 via ELA will be discussed by considering the soft X-ray method.

DOI： 10.1109/IMFEDK.2012.6218600

記述言語：英語  

DOI： 10.1143/JJAP.51.06FF04

記述言語：英語   掲載種別：研究論文（学術雑誌）  

A possible Ge-on-insulator (GOI) structure, namely, stripe arrays with nanospacing, was proposed as a promising epitaxial template structure for the Ge epitaxial layer. Agglomeration-free single-crystalline GOI stripe arrays with thickness of 50nm and spacing down to 0.5 μm were successfully grown by the Si-seeded rapid-melting growth technique. The growth of GOI stripe arrays with a spacing of 0.1 μm was not achieved owing due to the severe agglomeration of Ge during the heat treatment. This may be due to the small adhesion area of the capping layer between the stripes where it could not withstand the force caused by Ge agglomeration. From the electron backscattering diffraction (EBSD) measurement, the rotational growth was confirmed by the observation of various orientations when the thickness of the Ge layer was reduced to 20 nm. This is probably due to the decrease in the bulk effects that basically act to prevent the slip of lattice planes. These preliminary results provide a breakthrough towards the realization of heterogeneous integration on Si platforms with multifunctionalities.

DOI： 10.1143/JJAP.51.06FF04

記述言語：日本語   掲載種別：研究論文（学術雑誌）  

SiGe-mixing-triggered rapid-melting growth for Ge-on-insulator formation

記述言語：日本語   掲載種別：研究論文（学術雑誌）  

The development of high-quality Ge-on-insulator (GOI) structures is essential for making a breakthrough into the scaling limit of Si large-scale integrated circuits. In the present paper, we review a new GOI growth technique, i.e., the SiGe-mixing-triggered rapid-melting growth technique, which enables chip-sized and mesh-shaped GOI structures. In addition, the integration of GOI(111) on Si(100) substrates becomes possible by combining this method with the Si-microseeding technique. These progresses pave the way for the artificial single-crystal technology.

DOI： 10.11470/oubutsu.81.5_410

記述言語：日本語   掲載種別：研究論文（学術雑誌）  

Melting growth of Si-doped Ge films, i.e., Ge(Si) films, on insulator has been investigated. After rapid-thermal annealing of Ge(Si) films in the temperatures region surrounded with the liquidus curve and solidus curve of the phase diagram of the SiGe system, SiGe crystals with large-grains (15-30μm) were formed. The Si concentration profiles in the grains showed peaks at the center of grains. The peak Si concentrations were almost the same as the Si concentrations along the solidus curve at the annealing temperature. These phenomena were explained based on the formation of Si-rich micro-crystals during annealing and subsequent Si-segregated lateral-growth during cooling.

記述言語：日本語   掲載種別：研究論文（学術雑誌）  

A technique for low-temperature(<〜350℃) formation of orientation-controlled large-grain Ge films on insulating layers is desirable for realization of flexible high-speed thin film transistors. In line with this, we have investigated Au-induced layer-exchange crystallization using a-Ge/Au/insulator stacked structures where Al_2O_3 layers were inserted at a-Ge/Au interfaces. Consequently, (111)-oriented large-grain (20-50 μm) films are obtained by inserting the interfacial layers (〜3 μm). These phenomena are explained based on the retardation of random bulk nucleation in Au films and thus domination of(111)-oriented nucleation on insulators, caused by suppression of Ge/Au interdiffusion.

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Hybrid-integration of (111), (110), and (100) Ge-on-insulator (GOI) on an Si chip is essential to merge III-V semiconductor optical-devices as well as high-speed Ge transistors onto Si-large-scale integrated-circuits. We clarify important-parameters to control Ni-metal-induced lateral crystallization and Al-induced layer-exchange crystallization. This achieves artificial (110) and (111) Si micro-seed on insulating-film. Together with Si substrate as (100) Si seed, multi-crystal-seeds with different orientations are aligned on a Si chip. Then, SiGe-mixing triggered rapid-melting-growth of amorphous-Ge is examined from these multi-crystal-seeds. This enables simultaneous Ge lateral-crystallization with (111), (110), and (100) orientations. High-quality, hybrid-orientation GOIs without defects are demonstrated on Si platform.

DOI： 10.1063/1.4705733

記述言語：英語   掲載種別：研究論文（学術雑誌）  

金属誘起成長における界面エネルギー最小化効果を利用し、(110),(111)面方位を有するSi単結晶粒を非晶質の絶縁膜上に形成するとともに、これらと基板(Si(100))をシードとしたGe溶融成長を誘起するプロセス手法を構築した。その結果、多面方位（(100),(110),(111)）を有する単結晶Ge薄膜を同一基板上に混載する事に成功した。人工単結晶技術の創成であり、次世代LSIの実現を加速する重要な成果である。

記述言語：英語   掲載種別：研究論文（学術雑誌）  

絶縁膜上におけるGe薄膜の自己組織化現象を利用し、リソグラフィー技術を用いることなく、絶縁膜上に微細メッシュ構造を有するGe単結晶薄膜を形成するとともに、これをテンプレートとして大面積かつ平坦な単結晶Ge薄膜をエピタキシャル成長するプロセスを創成した。絶縁膜上に多機能を有する異種デバイスを混載する基盤技術の創出であり、次世代LSIの実現を加速する重要な成果である。

記述言語：英語  

DOI： 10.1016/j.tsf.2011.10.076

記述言語：英語   掲載種別：研究論文（学術雑誌）  

High-quality Ge-on-insulator (GOI) structures are essential for integrating multi-functional devices onto the Si-platform. We develop the nano-lithography free method for single-crystalline GOI networks by combining partial Ge evaporation and rapid-melting growth techniques. This realizes chip size GOI with high Ge coverage fractions (>75), which is crisscrossed with nano-spacing (∼100 nm width). Over-epitaxy of Ge on the GOI network is also examined, which achieves single-crystalline GOI uniform-plane by covering the nano-spacing. This proves the validity of high-density GOI networks as the epitaxial template. This method will facilitate the heterogeneous integration of Ge, III-V semiconductors, and magnetic materials on the Si-platform.

DOI： 10.1063/1.3691258

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Low-temperature (∼250°C) layer exchange crystallization of poly-Si _{1 - x}Ge _x (x = 1-0) films on insulators has been investigated for realization of advanced flexible devices. We propose utilization of Au as catalyst to enhance the crystallization at low temperatures. By annealing (∼250°C, 20 h) of the a-Si _{1 - x}Ge _x (x = 1-0)/Au stacked structures formed on insulating substrates, the SiGe and Au layers exchange their positions, and Au/poly-SiGe stacked structures are obtained. The Ge fractions of the obtained poly-SiGe layers are identical to that of the initial a-SiGe layers, and there is no Si or Ge segregation. This low temperature crystallization technique enables poly-SiGe films on plastic substrates, which are essential to realize advanced flexible devices.

DOI： 10.1016/j.tsf.2011.10.087

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Strain-induced enhancement of carrier mobility is essential for achieving high-speed transistors. The effects of thermal-annealing (temperature: 400-1150°C) and ultraviolet (UV) laser-annealing (wavelength: 248 nm, temperature: 30-400°C) on strain-enhancement in Si-pillars covered with Si ₃N ₄ stress-liners by plasma-enhanced chemical vapor deposition are investigated. Before annealing, the Si ₃N ₄ stress-liners induce a tensile strain (∼0.5%) in Si. After thermal-annealing (> 800°C), the strain becomes highly compressive (> ∼0.4%), because of dehydrogenation-induced structural relaxation in Si ₃N ₄ films. On the other hand, the tensile strain becomes large (>~0.7%) after UV laser-annealing at 400°C, due to non-equilibrium dehydrogenation in Si ₃N ₄ films. This strain-enhancement technique is useful for the realization of advanced high-speed three-dimensional transistors.

DOI： 10.1016/j.tsf.2011.10.088

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Ion-implantation characteristics and dopant activation behavior of P in Ge have been investigated. A Monte Carlo simulation indicates a smaller projected range and consequently a smaller critical dose of amorphization for Ge compared to Si. The solid-phase epitaxial (SPE) regrowth characteristics of damaged layers for Ge clearly depend on crystal orientation of the substrate in completely amorphized samples, while no orientation dependent regrowth is observed in the partially amorphized samples. These phenomena were explained on the basis of the damage cluster model. In addition, maximum carrier activation coincides with the complete regrowth at annealing temperatures of 300-400°C in completely amorphized samples. However, higher temperature annealing (500-550°C) is necessary for maximum carrier activation in partially amorphized samples, although SPE regrowth completes around 250-300°C. Analysis of the temperature dependence of carrier activation ratio in partially amorphized samples suggests that carrier-activation should be mediated by vacancy-migration.

DOI： 10.1016/j.tsf.2011.10.076

記述言語：英語  

記述言語：英語  

DOI： 10.1016/j.tsf.2011.10.088

記述言語：英語   掲載種別：研究論文（学術雑誌）  

We have investigated self organization of novel FeGe/FeSi/FeGe layered structures on Ge(111) and their electrical conduction properties. From analyses of compositional change, diffusion dynamics analyses and microstructure observations, it was revealed that the self organization of the layered structures was enhanced by spinodal decomposition which may be induced by pronounced compositional changes associating to inhomogeneous interdiffusion. The electrical conduction showed singular temperature dependence which obviously reflected natureof Kondo insulator FeSi.

DOI： 10.1016/j.phpro.2012.01.006

記述言語：日本語   掲載種別：研究論文（学術雑誌）  

It is necessary two processes (crystal-nucleus formation and crystal grain growth) for crystallization. In general, the activation energy of crystal-nucleus formation is higher than that of grain growth. To realize low-temperature crystallization, we tried to form the quasi-nucleus by soft X-ray irradiation. In this study, the effects of soft X-ray irradiation on crystallization of a-Si and a-Ge films were investigated. The crystallization temperatures of a-Si film and a-Ge film were decreased from 680℃ to 580℃ and 500℃ to 420℃ by soft X-ray irradiation, respectively. The decrease in crystallization temperature is also related to enhancement of atomic migration and atoms transitioning into a quasi-nuclei phase in the films.

記述言語：英語   掲載種別：研究論文（学術雑誌）  

We have investigated perfection of atomic rows on iron-based Heusler alloy films on Ge(111) planes by using ion channeling technique in order to find the dominant factors for the perfection. Fe₃Si/Ge(111) and Fe ₂CoSi/Ge(111) have a high quality of atomic rows at the heterointerface like that of perfect crystals. Fe_3-xMn _xSi/Ge(111) (x = 0.84, 0.72 and 0.36) interfaces have imperfection of atomic rows which may be controlled by both the lattice mismatch with the Ge substrate and the Mn-Si pairs due to the site disorder in the film with the Mn content x > 0.75. Analysis of axial channeling parameters employed in this study is very useful for quantitative evaluation of perfection of atomic rows at the heterointerface.

DOI： 10.1016/j.tsf.2011.05.024

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1016/j.tsf.2011.05.018

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

The gold-induced crystallization technique has been investigated to achieve poly-SiGe films on insulators at low temperatures (≤ 300°C). By annealing of the amorphous SiGe (Ge concentration: 0-100%)/Au stacked structures formed on insulating substrates, positions of the SiGe and Au layers are inverted, and the Au/SiGe stacked structures are obtained. Crystallization of the SiGe layers in the inverted samples is confirmed by the Raman scattering spectroscopy analysis. Moreover, the Raman measurements reveal that the Ge fractions in the crystallized SiGe layers are almost the same as those of the initial amorphous SiGe layers. This gold-induced layer-exchange crystallization technique of SiGe layers at a low temperature (∼250°C) will be very useful to obtain poly-SiGe layers on plastic substrates, which are essential to realize flexible high-speed thin-films transistors and high-efficiency solar cells.

DOI： 10.1149/1.3570774

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

We investigate metal-induced lateral crystallization (MILC) of Si on insulator to achieve (101) oriented Si films. Moreover, we demonstrate the lateral liquid phase epitaxy of high quality Ge(101) layers by using the MILC-Si films as crystal seed. This technique will be employed to realize high-speed thin-film transistors with Ge channel.

DOI： 10.1149/1.3570776

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Single crystal Ge-on-insulator (GOI) structures with various crystal orientations are necessary for realization of advanced high-speed and multi-functional devices. SiGe mixing triggered rapid-melting-growth of GOI is investigated as a function of seed-orientations and growth-directions. Single crystal growth of (100)-Ge strips is possible for all growth directions using (100)-oriented Si-seeds. However, rotational-growth is observed for some directions when Si-seeds with (110) and (111) orientations are employed. Such rotational-growth is completely suppressed by selecting the growth-directions deviating from the 〈111〉 direction by more than 35°. Based on this finding, growth of large mesh-patterned Ge layers with (100), (110), and (111) orientations are demonstrated.

DOI： 10.1149/1.3570777

記述言語：英語   掲載種別：研究論文（学術雑誌）  

絶縁膜上におけるGe薄膜の溶融成長を総合的に検討し、チップサイズ(1cm)に匹敵する巨大な単結晶Ge薄膜を実現した。さらに、高いキャリヤ移動度を有することを実証した。Geをチャネルとした超高速トランジスタの基盤技術の創出であり、次世代LSIの実現を加速する重要な成果である。

記述言語：英語   掲載種別：研究論文（学術雑誌）  

High-quality Ge-on-insulators (GOIs) are essential structures for high-performance transistors on an Si platform. We developed a rapid-melting-growth process for amorphous Ge (a-Ge) by optimizing the cooling rate and the underlying insulating materials. The effects of the solidification process for molten Ge on hole generation and spontaneous nucleation in Ge were determined. In addition, nucleation in the a-Ge matrix was found to be drastically suppressed by substituting SiO₂ underlayers with SiN underlayers. By combining high cooling rates (10.5-11.5 °Cs^-1) and SiN underlayers, we obtained ultra-long single crystal GOI strips (1 cm) with high hole mobilities (> 1000 cm²V^-1s ^-1). This chip-size formation of high-quality GOI will facilitate the development of advanced high-speed Ge-based devices.

DOI： 10.1063/1.3611904

記述言語：英語  

DOI： 10.1016/j.sse.2011.01.037

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Liquid-phase epitaxial growth of Ge islands on insulator (GOI) using Ni-imprint-induced Si (1 1 1) micro-crystal seeds (∼1 μmφ) is proposed. As a result, single-crystalline GOI (1 1 1) structures with large area (∼10 μmφ) are realized. The transmission electron microscopy observations reveal no dislocation or stacking fault in the laterally grown regions. Moreover, the Raman measurements show that the tensile strain (∼0.2%) which enhances the carrier mobility is induced in the growth regions. This new method can be employed to realize the multi-functional SiGe large scale integrated circuits.

DOI： 10.1016/j.sse.2011.01.037

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Metal-induced lateral crystallization (MILC) of amorphous Ge has been investigated to realize low temperature formation of poly-Ge films on insulating substrates. From a comparative study of MILC with various catalysis metals (Ni, Co, Pd, and Cu), it was found that Cu enhanced both nucleation and subsequent nucleus growth the most significantly among the species. Consequently, low temperature (∼ 250°C) growth with a high velocity (∼1 m/h) of poly-Ge films becomes possible by employing Cu as the catalyst. This technique will accelerate the realization of advanced high-speed TFT on flexible substrates.

DOI： 10.1149/1.3582794

記述言語：英語   掲載種別：研究論文（学術雑誌）  

The lateral liquid-phase epitaxy of Ge-on-insulator (GOI) using Si seeds has been investigated as a function of the Si-seed orientation and the growth direction. Giant single-crystalline GOI structures with ∼200 μm length are obtained using Si(1 0 0), (1 1 0), and (1 1 1) seeds. The very long growth is explained on the basis of the solidification temperature gradient due to Si-Ge mixing around the seeding area and the thermal gradient due to the latent heat around the solid/liquid interface at the growth front. In addition, growth with rotating crystal orientations is observed for samples with several growth directions. The rotating growth is explained on the basis of the bonding strength between lattice planes at the growth front. This rotating growth does not occur in any direction for (1 0 0) orientated seeds. Based on this finding the mesh-patterned GOI growth with a large area (250 μm × 500 μm) is demonstrated.

DOI： 10.1016/j.sse.2011.01.039

記述言語：英語   掲載種別：研究論文（学術雑誌）  

We comprehensively investigate Al-induced crystallization (AIC) of Si to achieve (0 0 1) and (1 1 1)-oriented Si films on quartz substrates. These phenomena are systematically explained by 'preferential interfacial-nucleation model' considering the nucleation sites and the phase transition of the interfacial Al oxide layers. Moreover, we demonstrate the lateral liquid phase epitaxy of Ge by using the orientation-controlled AIC-Si films as crystal seed. This technique enables high quality hetero-epitaxy of SiGe and Ge on transparent insulating substrates.

DOI： 10.1016/j.sse.2011.01.033

記述言語：英語  

DOI： 10.1016/j.sse.2011.01.033

記述言語：英語  

DOI： 10.1016/j.sse.2011.01.039

記述言語：英語  

DOI： 10.1016/j.sse.2011.01.039

記述言語：英語   掲載種別：研究論文（学術雑誌）  

絶縁膜上にメッシュ形状を有するGe単結晶薄膜を形成するプロセス技術を開発した。熱力学的な考察を元に試料構造とプロセス条件を適正化し、Si(100),(110),(111)基板からの溶融成長を誘起することにより、大面積にわたるメッシュ状Ge(100),(110),(111)単結晶薄膜の高品位成長を実現した。デバイスレイアウトの自由度が飛躍的に向上できる。超高速Geトランジスタを用いた次世代LSIの創出にを加速する成果である。

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Single-crystalline-Ge (c-Ge) networks with various crystal orientations on insulators formed on Si substrates are essential for integrating high-speed and multifunctional devices onto the Si platform. c-Ge networks are realized by rapid-melting growth of mesh-patterned amorphous-Ge over large areas (500×250 μm m²) on (110) and (111) as well as (100) Si substrates by optimizing the shape and the size of the mesh. It is revealed that latent-heat generated at the growth front can be controlled by selecting mesh-shape-and-size, which suppresses the spontaneous nucleation. In addition, essential role of the growth-direction on preventing the rotational growth is clarified.

DOI： 10.1063/1.3586259

記述言語：英語  

DOI： 10.1149/1.3570777

記述言語：英語  

DOI： 10.1149/1.3570776

記述言語：英語  

DOI： 10.1149/1.3570774

記述言語：英語  

DOI： 10.1149/1.3570777

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Due to the scaling limit faced by Si CMOS technology, much interest is being given on Ge. However, development of the Ge device technology requires more research into the fabrication processes. In this study, we have investigated the doping characteristics of P in Ge as a function of the dopant dose and substrate orientation. It is found that recovery characteristics of damaged layers depends on crystal orientation of the Ge substrates for samples having completely amorphized surface-layers produced by high-dose (1x10^<15> cm^<-2>) implantation. This is due to orientation-dependent regrowth velocity of Ge. On the other hand, no orientation dependence is observed for samples implanted with low dose (5x10^<13>-1x10^<14> cm^<-2>), whose surface layers are partially amorphized. For high-dose samples, the complete carrier-activation coincides with the damage-recovery at 350-400℃. However, higher temperature annealing (500-550℃) is necessary for carrier activation in low-dose samples, though crystallinity recovers at 250-300℃. The temperature-dependence of the carrier-activation ratio suggests that carrier-activation in low-dose samples is mediated by vacancy-migration.

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Due to the scaling limit faced by Si CMOS technology, much interest is being given on Ge. However, development of the Ge device technology requires more research into the fabrication processes. In this study, we have investigated the doping characteristics of P in Ge as a function of the dopant dose and substrate orientation. It is found that recovery characteristics of damaged layers depends on crystal orientation of the Ge substrates for samples having completely amorphized surface-layers produced by high-dose (1x10^<15> cm^<-2>) implantation. This is due to orientation-dependent regrowth velocity of Ge. On the other hand, no orientation dependence is observed for samples implanted with low dose (5x10^<13>-1x10^<14> cm^<-2>), whose surface layers are partially amorphized. For high-dose samples, the complete carrier-activation coincides with the damage-recovery at 350-400℃. However, higher temperature annealing (500-550℃) is necessary for carrier activation in low-dose samples, though crystallinity recovers at 250-300℃. The temperature-dependence of the carrier-activation ratio suggests that carrier-activation in low-dose samples is mediated by vacancy-migration.

記述言語：英語  

DOI： 10.1149/1.3562275

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

We have investigated the Si-seeding rapid-melting process and demonstrated the formation of giant Ge stripes with (100), (110), and (111) orientations on Si (100), (110), and (111) substrates, respectively, covered with SiO ₂ films. We revealed that crystallization is triggered by Si-Ge mixing in the seeding regions in this process. Based on this mechanism, we have proposed a novel technique to realize orientation-controlled Ge layers on transparent insulating substrates by using Si artificial micro-seeds with (100) and (111)-orientations. This achieved epitaxial growth of single crystalline (100) and (111)-oriented Ge stripes on quartz substrates. The Ge layers showed a high hole mobility exceeding 1100 cm²/Vs owing to the high crystallinity.

DOI： 10.4028/www.scientific.net/KEM.470.8

記述言語：英語   掲載種別：研究論文（学術雑誌）  

The sensing responses in aqueous solution of an open-gated pH sensor fabricated on an AlGaN/GaN high-electron-mobility-transistor (HEMT) structure are investigated. Under air-exposed ambient conditions, the open-gated undoped AlGaN/GaN HEMT only shows the presence of a linear current region. This seems to show that very low Fermi level pinning by surface states exists in the undoped AlGaN/GaN sample. In aqueous solution, typical current-voltage (I-V) characteristics with reasonably good gate controllability are observed, showing that the potential of the AlGaN surface at the open-gated area is effectively controlled via aqueous solution by the Ag/AgCl gate electrode. The open-gated undoped AlGaN/GaN HEMT structure is capable of distinguishing pH level in aqueous electrolytes and exhibits linear sensitivity, where high sensitivity of 1.9 mA/pH or 3.88 mA/mm/pH at drain-source voltage, VDS = 5 V is obtained. Due to the large leakage current where it increases with the negative gate voltage, Nernstian like sensitivity cannot be determined as commonly reported in the literature. This large leakage current may be caused by the technical factors rather than any characteristics of the devices. Surprisingly, although there are some imperfections in the device preparation and measurement, the fabricated devices work very well in distinguishing the pH levels. Suppression of current leakage by improving the device preparation is likely needed to improve the device performance. The fabricated device is expected to be suitable for pH sensing applications.

DOI： 10.3390/s110303067

記述言語：英語  

DOI： 10.1149/1.3551465

記述言語：英語   掲載種別：研究論文（学術雑誌）  

偏光ラマン分光法を用い、Si結晶薄膜に導入されている歪みが１軸性か２軸性かを判別する手法を開発した。さらに２次元マッピングにより、薄膜中に存在する１軸歪みおよび２軸歪みの分布を可視化することに成功した。次世代トランジスタ構築に有用な新評価手法の創成である。

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Using low-temperature molecular-beam epitaxy techniques on the (111) plane of Si or Ge, we can realize an atomically controlled Fe₃Si/Si or Fe₃Si/Ge heterojunction and simultaneously obtain DO3-ordered crystal structures of Fe3Si films. First, high-quality Fe₃Si/Si(111) Schottky tunnel contacts enable us to inject and detect spin-polarized electrons in Si conduction channels at 180 K, where Fe₃Si is a ferromagnetic spin injector and detector. This may lead to the accelerated development of next-generation Si-based spin metal-oxide-semiconductor field-effect transistors (MOSFETs). Next, for the atomically controlled Fe₃Si/Ge(111) Schottky contacts, we find the unexpected suppression of the Fermi level pinning (FLP) effect. This indicates that there is an influence of extrinsic contributions such as dangling bonds and disorder on the strong FLP effect at metal/Ge interfaces. We expect that the Fe3Si/Ge(111) contacts can be used to control the Schottky barrier height of future ultra scaled Ge-channel MOSFETs. These two novel and interesting results are expected to form the basis of a key technology toward developing nextgeneration SiGe transistors.

DOI： 10.1143/JJAP.50.010101

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Single-crystalline-Ge (c-Ge) networks on insulator films formed on Si substrates are essential for integrating high-speed and multifunctional devices onto the Si-platform. Rapid-melting-growth of mesh-patterned amorphous-Ge is examined over large areas (500×250 μ m²). For squared-mesh-pattern, polycrystalline-Ge forms throughout most of the mesh, though c-Ge is obtained near (<100 μm) Si-seed. Based on the consideration of geometric-effects, mesh-patterns are changed to hexagonal. This realizes c-Ge networks over the entire insulator area. These results indicate that Ge growth initiated from Si-seed propagates laterally over the hexagonal-mesh- pattern though bending and branching. These unique c-Ge-networks on insulators facilitate Ge-based advanced-devices on the Si-platform.

DOI： 10.1063/1.3544057

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Nondestructive evaluation of uni- and biaxial strain-distributions in Si-on-insulator (SOI) structures is essential to accelerate research and development of next-generation-strained-Si-transistors. We investigate polarized Raman scattering from (001) SOI-microstructures with SiN-stress-liners. Raman intensities are analyzed as a function of the angle between [100]-axis and polarization-directions of scattered-light. Interestingly, inactive Raman peaks in strain-free Si for scattered-light polarized along [100] and [010] directions become active in strained-Si, which is quantitatively explained by crystal-symmetry-change from cubic to orthorhombic or tetragonal structures. These findings enable precise evaluation of strain-distributions. Based on these results, selective-mapping of uni- and biaxial-strains in SOI-microstructures is demonstrated.

DOI： 10.1063/1.3535606

記述言語：英語   掲載種別：研究論文（学術雑誌）  

We have examined the LMOKE of some Heusler alloy films Fe₄Si, Fe₃Si, Fe₂CoSi, Fe₂MnSi (21at and 9at%Mn), Co₂FeSi epitaxially grown on Ge(111) and found that Fe₃Si, Fe₄Si and Fe₂CoSi films have larger Kerr rotation and smaller coercive fields than the amorphous Fe film and that they may be promising materials for magnetophotonic applications.

DOI： 10.1016/j.phpro.2011.01.004

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

絶縁膜上にメッシュ状Ge単結晶薄膜を形成するプロセス技術を開発した。熱力学的な考察を元に試料構造とプロセス条件を適正化し、大面積にわたるメッシュ状Ge単結晶薄膜の高品位成長を実現した。デバイスレイアウトの自由度が飛躍的に向上でき、高速Geトランジスタを用いた次世代LSIの創出につながる成果である。

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

We investigated a low-temperature crystallization of a- Si, a-Ge and a-Si_1-xGe_x films by the synchrotron radiation (SR) soft X-ray irradiation at storage ring current of 25-220 mA. Crystallization of SiGe caused by the atomic migration during soft X-ray irradiation is effective as compared with the thermal annealing.

記述言語：英語   掲載種別：研究論文（学術雑誌）  

High-strain Si-pillars are desirable for achieving high-speed three-dimensional transistors. The effects of postannealing (400-1150C) on strain-enhancement in Si-pillars covered with Si₃N₄ stress-liners are investigated. Before annealing, the Si₃N ₄ stress-liners induce strain in Si, where the direction of strain, which can be compressive or tensile, depends on the Si₃N₄ deposition parameters. After postannealing (800C), the strain becomes highly compressive, because of dehydrogenation-induced structural relaxation in Si ₃N₄ films. Consequently, compressive strains (1.6) are induced in the 200-nm-thick Si-pillars covered in 200-nm-thick Si ₃N₄ films after high temperature postannealing (1000-1150C). This strain-enhancement technique is useful for the realization of advanced high-speed three-dimensional transistors.

DOI： 10.1149/1.3551465

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Au-induced crystallization of Si through a layer-exchange process has been investigated to achieve poly-Si films on insulators at low-temperatures (∼250°C). By annealing (250-350°C) of amorphous Si (a-Si)/Au stacked structures formed on insulators, the positions of Si/Au layers are inverted, and Au/poly-Si stacked structures are obtained. This Au-induced layer-exchange growth technique at low-temperatures (∼250°C) should be very useful to obtain poly-Si films on flexible substrates, which are employed as template layers for growth of high quality Si_1-xGe_x (x: 0-1) films to realize flexible high-speed thin-film transistors and flexible high-efficiency solar cells.

DOI： 10.1149/1.3562275

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

High-quality orientation-controlled Ge on insulator (GOI) structures are essential to realize high-performance thin-film transistors (TFTs) and epitaxial templates for multifunctional 3-dimensional large-scale integrated circuits (3D-LSIs). We have investigated the Si-seeding rapid-melting process and demonstrated formation of giant Ge stripes with (100), (110), and (111) orientations on Si (100), (110), and (111) substrates, respectively, covered with SiO₂ films. We revealed that crystallization is triggered by Si-Ge mixing in the seeding regions in this process. Based on this mechanism, we have proposed a novel technique to realize orientation-controlled Ge layers on transparent insulating substrates by using Si artificial micro-seeds with (100) and (111)-orientations. This achieved epitaxial growth of single crystalline (100) and (111)-oriented Ge stripes on quartz substrates. The transmission electron microscopy observations revealed no-defects in the laterally grown Ge regions. The Ge layers showed a high hole mobility exceeding 1100 cm ².Vs owing to the high crystallinity. This novel SiGe mixing-triggered growth technique opens up the possibility of the next-generation TFTs and multifunctional 3D-LSIs.

DOI： 10.1149/1.3487571

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Single-crystal Ge films on insulating substrates are desired to achieve advanced 3-dimensional large-scale integrated circuits (3D-LSIs) and thin-film transistors (TFTs). We have developed the rapid-melting Ge growth seeded from Si substrates, which achieves giant Ge on insulator (GOI) structures with (100), (110), and (111) orientations. Driving force to initiate the lateral growth is clarified as the solidification temperature gradient originating from melting induced Si-Ge mixing. Combination with the artificial Si micro-seed technique and the rapid melting growth enables the single-crystal defect-free Ge on transparent insulating substrates. High hole mobility exceeding 1000 cm ²/Vs is also demonstrated.

DOI： 10.1109/ICSICT.2010.5667440

記述言語：英語  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

絶縁膜上に溶融法で形成したGe単結晶薄膜の結晶性に与えるSiシードの結晶方位の効果を系統的に解明した。成長と共にGe薄膜の結晶方位が回転する現象を明らかにすると共に、成長方向を適正化することにより回転を抑制する指針を明確化した。絶縁膜上におけるGe単結晶薄膜の高品位形成を実現する手法の確立であり、次世代LSIや次世代システムインディスプレイの実現を加速する重要な成果である。

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Stress-relaxation phenomena in SiGe-on-insulator (SGOI) layers during the oxidation-induced Ge condensation process have been comprehensively investigated as a function of several parameters (SiGe thickness, Ge fraction, oxidation temperature, and oxidation time). Final SiGe thickness-dependent relaxation ratio was found, i.e., complete relaxation for thick (<100 nm) SGOI layers, and abrupt decrease in relaxation ratio with decreasing SiGe thickness below 100 nm, e.g., the relaxation ratio of 30% for the SiGe thickness of 30 nm. An improved method combined with H+ irradiation (5× 10¹⁵ cm ^-2) and postannealing (1200°C) has been examined to enhance the stress-relaxation. This achieved a high relaxation ratio (70%) and a low defect density (1× 10⁶ cm^-2) in the ultrathin (28 nm) SGOI with a Ge fraction of 30%. A local-area slipping model was proposed, where SiGe/ SiO₂ interface slipping occurred during postannealing in local areas surrounded by cross hatches. This model quantitatively explained the enhanced relaxation ratio of the SGOI layers obtained by the Ge condensation method combined with H+ irradiation and postannealing.

DOI： 10.1149/1.3486089

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Defect-free Ge-on-insulator (GOI) with various crystal orientations is essential to realize high-speed and multifunctional devices. Seeded rapid-melting growth of GOI is investigated as a function of seed-orientations and growth-directions. From (100)-oriented Si seeds, Ge growth with a (100) orientation propagates for all growth-directions, however, rotational-growth is observed for some directions when Si seeds with (110) and (111) orientations are used. Such rotational-growth can be completely suppressed by selecting the growth-directions deviating from 〈 111 〉 by more than 35°. Transmission-electron-microscopy observation shows no-stacking fault and no-dislocations. Consequently, defect-free GOI with (100), (110), and (111) orientation is achieved, which demonstrates high-hole mobility (∼1100 cm²/V s).

DOI： 10.1063/1.3493184

記述言語：英語  

DOI： 10.1149/1.3486089

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1142/S0217979210056657

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Orientation-controlled single-crystal Ge stripes on insulating substrates are desired to achieve high-performance thin-film transistors. The rapidmelting growth process of amorphous Ge has been examined by using polycrystalline Si islands as the growth seed. Rotational growth is found for Ge stripes initiated from (110) and (111) orientations, however, the lateral-growth initiated from the (100) orientation propagates continuously keeping its orientation. Based on these findings, an advanced rapid-melting growth method is developed by combining with the Si(100) micro-seed technique. This enables single-crystal Ge(100) giant-stripes with 400 μm length on insulating substrates. High hole mobility exceeding 1000 cm² V^-1 s^-1 is also demonstrated.

DOI： 10.1143/APEX.3.075603

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Single phase M₂Si (M = Mg, Ca, Sr) silicides were grown using Si substrates, by thermal treatment of the substrates in the vapors of the metallic sources, M, and the electronic structures and optical property of the silicides were investigated. The electronic band structures of the silicides were calculated using the first-principles total-energy calculation program in pseudopotential schemes with plane-wave basis functions. The calculated optical reflectance spectra were also deduced from the theoretical band structures, and roughly agreed with the experimental results except for the low reflectance intensity around 2 eV. This suggests that the energy band gap of the silicides roughly agree with the calculated values of 0.15, 0.31 and 0.35 eV for Mg ₂Si, Ca₂Si and Sr₂Si, respectively, within the underestimation of the band gap by the density functional calculation. The optical property of the silicides is also discussed in relation to the morphological structures of the silicides.

DOI： 10.1142/S0217979210056050

記述言語：英語   掲載種別：研究論文（学術雑誌）  

非晶質Geの溶融成長法に金属誘起成長法によるSi結晶形成技術を重畳し、無定型な絶縁性基板上に結晶方位の制御されたGe単結晶薄膜を実現した。人工単結晶技術の創成であり、次世代システムインディスプレイの実現を可能とする重要な成果である。

記述言語：英語   掲載種別：研究論文（学術雑誌）  

金属誘起横方向成長法により絶縁膜上に形成したSiGe多結晶薄膜の微細構造を電子顕微鏡法により解明した。成長を駆動する金属化合物がGe濃度に依存して変化する事、その結果、結晶成長の様態もGe濃度に応じて変化する事を明らかにした。システムインディスプレイや高効率薄膜太陽電池の作製プロセスを確立する上で有用な知見である。

記述言語：英語   掲載種別：研究論文（学術雑誌）  

金属/Geショットキー障壁のフェルミ準位ピニングに与える界面原子配列の効果を検討した。界面構造を原子層レベルで制御すると、フェルミ準位ピニングが弱化することを明らかにした。Geをチャネルを用いた次世代トランジスタの実現を加速する有用な成果である。

記述言語：日本語   掲載種別：研究論文（学術雑誌）  

Large grain polycrystalline silicon-germanium (poly-SiGe) with controlled crystal orientation on glass substrates is required to achieve high speed thin-film transistors and high-efficiency thin-film solar cells. For this purpose, we have developed an advanced Al-induced crystallization (AIC) technique by controlling the interfacial oxide layers. As a results, homogeneous and large-grained (>10 μm) AIC growth was achieved for samples with the whole Ge fractions (0-100%). In addition, we evaluated crystal orientation of the poly-SiGe and discuss the growth mechanism.

記述言語：日本語   掲載種別：研究論文（学術雑誌）  

We proposed SiGe mixing triggered melting growth, and realized (100)-oriented Ge on insulator (GOI) stripes (〜400μm) by using Si(100) substrates as crystal seed. To expand the application fields of such GOI structures, GOI stripes with various crystal orientations should be achieved. In the present study, growth-direction-dependent characteristics of GOI from Si(100), (110), (111) seeding substrates are investigated. During the study, we encountered a phenomenon of rotating growth of Ge layers. The detail of the rotation growth is investigated, and a guideline to prevent this phenomenon is clarified. As a results, GOI(110) and (111) stripes without the rotation are realized, together with GOI(100) stripes. Moreover, a large mesh (500μm × 250μm) of GOI stripe is realized based on these findings.

記述言語：英語   掲載種別：研究論文（学術雑誌）  

The development of high-carrier-mobility Ge-channel thin-film transistors (TFTs) is desired to realize advanced system-in-displays. To achieve the development of single-crystalline Ge films on insulating substrates, we have developed the directional melting growth process of amorphous Ge by using polycrystalline Si islands as growth seeds. Defect-free single-crystalline Ge stripes of 400 mm length are realized, and high-holemobilities of more than 1000 cm2 V^-1 s^-1 are demonstrated in the entire lateral growth region. This method opens up the possibility of fabricating high-speed Ge-channel TFTs for system-in-displays.

DOI： 10.1143/JJAP.49.04DA08

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Liquid-phase epitaxial growth of Ge islands on insulator (GOI) using Ni-imprint-induced Si (111) micro-crystal seeds (〜1μmφ) is proposed. As a result, single-crystalline GOI (111) structures with large area (〜10μmφ) are realized. The Raman measurements show that the tensile strain (-0.2 %) which enhances carrier mobility is induced in the growth regions. Moreover, the transmission electron microscopy observations reveal no defects in the grown regions. This new method is can be employed to realize the multi-functional SiGe-LSI.

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Liquid-phase epitaxial growth of Ge islands on insulator (GOI) using Ni-imprint-induced Si (111) micro-crystal seeds (〜1 μmφ) is proposed. As a result, single-crystalline GOI (111) structures with large area (〜10 μmφ) are realized. The Raman measurements show that the tensile strain (〜0.2 %) which enhances carrier mobility is induced in the growth regions. Moreover, the transmission electron microscopy observations reveal no defects in the grown regions. This new method is can be employed to realize the multi-functional SiGe-LSI.

記述言語：英語   掲載種別：研究論文（学術雑誌）  

We study electrical properties of metal/Ge contacts with an atomically controlled interface, and compare them with those with a disordered one, where atomically controlled interfaces can be demonstrated by using Fe₃ Si/Ge (111) contacts. We find that the Schottky barrier height of Fe₃ Si/n-Ge (111) contacts is unexpectedly lower than those induced by the strong Fermi-level pinning at other metal/n-Ge contacts. For Fe₃ Si/p-Ge (111) contacts, we identify clear rectifying behavior in I-V characteristics at low temperatures, which is also different from I-V features due to the strong Fermi-level pinning at other metal/p-Ge contacts. These results indicate that there is an extrinsic contribution such as dangling bonds to the Fermi-level pinning effect at the directly connected metal/Ge contacts.

DOI： 10.1063/1.3368701

記述言語：日本語  

記述言語：日本語  

記述言語：日本語  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

絶縁膜上における非晶質SiGeの溶融成長を検討し、高Ge濃度を有する高品質SiGe単結晶薄膜を実現した。顕微ラマン分光法を用いてSiGe膜中のSi濃度分布を評価し、固化時のGe偏析が生じていることを明らかにした。更に、純Ge膜の溶融成長で問題となるGe凝集が、Si添加により抑制できることを明らかにした。次世代LSIプロセスとして有用な成果である。

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Ge-rich SiGe-on-insulator (SGOI) is required for high speed transistors. We investigated the effects of Si doping on the growth characteristics of SGOI produced by rapid melting growth. The aggregation of Ge, observed for pure Ge wide stripes (>5 μm), can be suppressed by Si doping. Si doping causes rotational growth of SiGe stripes, but this can be controlled using lower Si doping concentrations and growth temperatures. Singlecrystalline Ge-rich SGOI (Ge concentration > 96%) that is wide enough (15 μm) for device fabrication is thus produced. Transmission electron microscopy reveals that the Ge-rich SGOI does not contain dislocations or stacking faults.

DOI： 10.1143/APEX.3.031301

記述言語：英語  

DOI： 10.1016/j.tsf.2009.10.106

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Our recent progress in low-temperature molecular beam epitaxy of ferromagnetic Heusler alloys on group-IV-semiconductor is reviewed. By optimizing beam flux ratio (Fe:Si = 3:1) and growth temperature (130 °C), a high-quality hybrid structure, i.e., DO₃-type Fe₃Si on Ge with an atomically flat interface, was achieved. Excellent magnetic properties with a small coercivity (0.9 Oe) and electrical properties with Schottky barrier height of 0.52 eV were obtained. The ratio of the on-current to the off-current of Schottky diode was on the order of 10⁴. In addition, heteroepitaxy of half-metallic alloys (Fe_{3 - X}Mn_xSi(X = 0.6-1.4)) on Ge substrates was demonstrated. These results will be a powerful tool to open up group-IV-semiconductor spin-transistors, consisting of Ge channel with high mobility and ferromagnetic source/drain for spin-injection.

DOI： 10.1016/j.tsf.2009.10.106

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Liquid-phase epitaxial growth (LPE) of Ge islands on insulator (GOI) using Ni-imprint-induced Si (111) crystal seeds (~ 1 μmφ{symbol}) is investigated. By optimizing cap and bottom SiO₂ layer thickness, single-crystalline GOI (111) structures (~ 10 μmφ{symbol}) are realized. The Raman peaks due to Ge-Ge bonds of the growth regions reveal that the full width at half maximum (FWHM) is equal to that of single-crystalline Ge bulk wafers (3.2 cm^{- 1}). This result demonstrates the very high crystal quality of the growth regions.

DOI： 10.1016/j.tsf.2009.10.084

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Giant growth (~ 400 μm length) of single crystalline Ge on insulator (GOI) with (100), (110), and (111) orientations is demonstrated by lateral liquid-phase epitaxy (L-LPE) using Si(100), (110), and (111) substrates, respectively, as the seeds. The micro-probe Raman measurements and transmission electron microscopy observations showed that the growth regions were of very high crystal quality and were defect free. In addition, lateral diffusion of Si atoms was observed only in the regions near the seeding edges (~ 100 μm). Based on these findings, the trigger for the giant growth of the high-quality GOI was discussed considering the solidification temperature gradient due to Si-Ge mixing and the thermal gradient due to the latent heat at the growth front.

DOI： 10.1016/j.tsf.2009.10.081

記述言語：英語   掲載種別：研究論文（学術雑誌）  

A rapid melting growth technique of amorphous Ge has been developed by using polycrystalline Si islands as growth-seed. High quality single-crystal Ge stripes with 400 μm length, dominantly (100) oriented, are obtained on quartz substrate, which provides a high carrier mobility of 1040 cm²/Vs. This technique is expected to be useful to realize Ge-channel thin film transistors with high carrier mobility.

DOI： 10.1016/j.tsf.2009.10.083

記述言語：英語   掲載種別：研究論文（学術雑誌）  

For electrical spin injection and detection of spin-polarized electrons in silicon, we explore highly epitaxial growth of ferromagnetic full-Heusler-alloy Co₂FeSi on silicon substrates using low-temperature molecular beam epitaxy (LT-MBE). Although in-situ reflection high energy electron diffraction images clearly show two-dimensional epitaxial growth for growth temperatures (T_G) of 60, 130, and 200 °C, cross-sectional transmission electron microscopy experiments reveal that there are single-crystal phases other than Heusler alloys near the interface between Co₂FeSi and Si for T_G = 130 and 200 °C. On the other hand, almost perfect heterointerfaces are achieved for T_G = 60 °C. These results and magnetic measurements indicate that highly epitaxial growth of Co₂FeSi thin films on Si is demonstrated only for T_G = 60 °C.

DOI： 10.1016/j.tsf.2009.10.107

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Low-temperature (< 450 °C) Al-induced crystallization (AIC) of a-Si_{1 - x}Ge_x (0 < x < 1) films on an insulator has been investigated using a-Si_{1 - x}Ge_x/Al/quartz stacked structures. It was found that the crystal growth features drastically depends on the Ge fraction. Change of the stacked structures to Al/poly-SiGe/quartz uniformly occurred by annealing for low Ge fractions (< 50%). However, the layer exchange and crystallization occurred locally and heterogeneously for high Ge fractions (> 50%). To realize uniform crystallization for high Ge fractions, effects of interfacial Al oxide layer thickness on layer exchange were investigated. By optimizing the oxide layer thickness, the layer exchange process could be controlled, and thus, homogeneous crystallization with large grain sizes (> 20 μm) was achieved for samples with the whole Ge fractions. These findings will be a powerful tool for realizing large poly-SiGe on insulating films for high-efficiency thin-film solar cells and system-in-displays.

DOI： 10.1016/j.tsf.2009.10.082

記述言語：英語  

DOI： 10.1016/j.tsf.2009.10.107

記述言語：英語  

DOI： 10.1016/j.tsf.2009.10.084

記述言語：英語  

DOI： 10.1016/j.tsf.2009.10.082

記述言語：英語  

DOI： 10.1016/j.tsf.2009.10.081

記述言語：英語  

DOI： 10.1016/j.tsf.2009.10.083

記述言語：その他   掲載種別：研究論文（学術雑誌）  

フレキシブルな高速薄膜トランジスタ(TFT)の実現には，高移動度を有する半導体薄膜をプラスチックの軟化温度(∼300^oC)以下の極低温で高品質形成する必要がある．我々は，共晶温度の低いAu/Ge系（共晶点: 361^oC）に着目し，高移動度半導体(Ge)の低温成長を検討した．非晶質Ge（100 nm）/ Au（100 nm）の積層構造を石英基板上に作製した．熱処理（200∼400^oC）後の試料の組成分布の変化と結晶性を評価した処，低温(250^oC)で，Ge/Auが層交換すると共に，Geが結晶化することが明らかとなった．フレキシブルな高速TFTの実現を加速する画期的な成果である．

DOI： 10.11527/jceeek.2010.0.584.0

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Metal-induced lateral crystallization (MILC) in amorphous SiGe films on insulating substrates is an important technique for future thin-film-transistor fabrication. Growth features of low and/or high temperature MILC have been investigated based on the microscopic crystal observation. In the initial stage of MILC, precipitation of hemispherical Ni(Si,Ge) with orthorhombic structure is found at the growth front. This leads to the formation of long needlelike SiGe crystallites. And then, the spontaneous nucleation and growth of SiGe take place around the needlelike crystals, resulting in long rod-shaped SiGe crystals. In this way, the role of Ge atoms on MILC is clarified.

DOI： 10.1063/1.3422477

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

The gold-induced crystallization technique has been investigated to achieve poly-Si films on insulators at low temperatures (≤250°C). By annealing (∼250°C) the amorphous Si (a-Si)/Au stacked structures formed on insulating substrates, the positions of Si/Au layers are inverted, and Au/poly-Si stacked structures are obtained. On the other hand, by annealing (>400°C) the structures, mixed layers of c-Si and Au are obtained. These growth phenomena are explained on the basis of the eutectic reaction. This gold-induced layer-exchange growth technique at low-temperatures (∼250°C) is very useful to obtain poly-Si on flexible substrates, which are essential to realize flexible high-speed thin-films transistors and high-efficiency solar cells.

DOI： 10.1109/TENCON.2010.5686705

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Tensile-strained Si pillars are desired to achieve three-dimensional (3D) transistors with high speed. Effects of ultraviolet (UV) light irradiation on tensile strains in Si pillars covered with SiN:H stress-liners are investigated as a function of the wavelength (172-436 nm). Tensile-stress enhancement is found at specific wavelengths (200-330 nm) under low-temperature heating (400 °C), where dehydrogenation in SiN:H is clearly detected by infrared absorption measurements. On the other hand, equilibrium dehydrogenation by high-temperature heating (>700 °C) without UV-irradiation does not cause tensile-stress enhancement. This nonequilibrium dehydrogenation at low temperatures opens up possibility of 3D transistors with high carrier mobility.

DOI： 10.1063/1.3278596

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Single-crystal Ge island arrays on SiO₂ /Si structures are desired to merge advanced Ge devices into Si large scale integrated circuit (LSI). We have developed the rapid-melting-growth process of amorphous Ge by using Ni-imprint-induced Si (111) fine crystals (∼1 ^μmφ) as the growth seed. Arrays of (111) oriented single-crystal Ge islands with device size (∼10 mu;m φ) are uniformly fabricated on SiO₂ /Si substrates. The cross-sectional transmission electron microscopy observation reveals that Ge islands include no dislocation or stacking fault. This method opens up a possibility to achieve hybrid SiGe-LSI with multifunctions.

DOI： 10.1063/1.3231925

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Orientation-controlled Si films on transparent insulating substrates are strongly desired to achieve high-efficiency thin-film solar cells. We have developed the interfacial-oxide layer modulated Al-induced low temperature (<450 °C) crystallization technique, which enables dominantly (001) or (111)-oriented Si films with large grains (20-100 μm). These results are qualitatively explained on the basis of a model considering the phase transition of the interfacial Al oxide layers. This process provides the orientation-controlled Si templates on insulating substrates, which enables successive high quality epitaxial growth necessary for advanced Si thin-film solar cells.

DOI： 10.1063/1.3241076

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Single-crystal Ge on a transparent insulating substrate is desired to achieve advanced thin-film transistors (TFTs) with high speed operation. We have developed the rapid-melting-growth process of amorphous Ge by using polycrystalline Si islands as the growth seed. High-quality and dominantly (100)-oriented single-crystal Ge stripes with 400 μm length are demonstrated on quartz substrates. The temperature dependence of the electrical conductivity shows a high hole mobility of 1040 cm² /V s. This method opens up a possibility of Ge-channel TFT with the high carrier mobility.

DOI： 10.1063/1.3182795

記述言語：英語   掲載種別：研究論文（学術雑誌）  

The carrier concentration and mobility of intrinsic holes in poly-Ge films grown by solid-phase crystallization (SPC) were investigated. The two-step SPC method, consisting of low-temperature annealing (425 °C) to obtain large grains and subsequent high-temperature annealing (500 °C) to decrease defects, is proposed. The hole concentration remarkably decreased from 1 × 10¹⁸ to 5 × 10¹⁷cm^-3 with keeping a high-mobility (140 cm²/Vs) after post-annealing.

DOI： 10.1016/j.sse.2009.08.002

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Recent our progress in the lateral liquid-phase epitaxy of Ge-on-insulator (GOI) using Si seeds has been reviewed. Giant single-crystalline GOI(100) structures with 〜400μm length are obtained using Si(100), (110), and (111) seeds. The very long growth is explained on the basis of the solidification temperature gradient due to Si-Ge mixing around the seeding area and the thermal gradient due to the latent heat around the solid/liquid interface at the growth front. In addition, growth with rotating crystal orientations observed for samples with Si(111) seeds is investigated. The rotation angle depends on the growth direction in plane to the surface. The rotation angle changes with a 60° period and becomes 0° and about 30° for <011> and <121> directions, respectively. The rotating growth is explained on the basis of the bonding strength between lattice planes at the growth front.

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Indentation-induced solid-phase crystallization (SPC) was proposed to achieve low-temperature growth of Si_1-xGe_x (x=0-1) on insulator. Crystal nucleation was enhanced at the indented positions due to the stress effect, which triggered the lateral SPC. As a result, large Si _1-xGe_x (x=0-1) crystal regions (>2 μm) were achieved on insulator at low temperatures (<590 °C). The growth kinetics for this catalyst metal-free process, i.e., activation energies for nucleation and lateral growth, are presented as a function of the Ge fraction (x).

DOI： 10.1063/1.3136857

記述言語：英語   掲載種別：研究論文（学術雑誌）  

We demonstrate electrical injection and detection of spin-polarized electrons in silicon (Si) using epitaxially grown Fe₃ Si/Si Schottky-tunnel-barrier contacts. By an insertion of a δ -doped n ⁺ -Si layer (∼ 10¹⁹ cm^-3) near the interface between a ferromagnetic Fe₃ Si contact and a Si channel (∼ 10¹⁵ cm^-3), we achieve a marked enhancement in the tunnel conductance for reverse-bias characteristics of the Fe₃ Si/Si Schottky diodes. Using laterally fabricated four-probe geometries with the modified Fe₃ Si/Si contacts, we detect nonlocal output signals that originate from the spin accumulation in a Si channel at low temperatures.

DOI： 10.1063/1.3130211

記述言語：英語   掲載種別：研究論文（学術雑誌）  

We study magnetic properties of epitaxial Fe3 Si layers grown on Ge(111) with atomically flat interfaces. An unexpected uniaxial magnetic anisotropy is observed in the film plane for all as-grown samples, and the direction of the uniaxial easy axis is different for each of these samples. By postgrowth annealing, surprisingly, the random orientation of the uniaxial easy axis is aligned to a direction along about [0 1- 1], together with a reduction in the saturation magnetization. We discuss a possible mechanism of the variation in the magnetic properties after the annealing.

DOI： 10.1063/1.3065985

記述言語：日本語   掲載種別：研究論文（学術雑誌）  

Low-temperature (<550℃) Al-induced crystallization (AIC) of amorphous Si_<1-x>Ge_x (x=0-1) on glass substrate has been investigated to achieve high-speed thin-film transistors and high-efficiency thin-film solar cells. Crystal growth morphology drastically changed with Ge fraction, and layer exchange occurred heterogeneously for high Ge fractions (>50%). To solve this problem, the effects of interfacial oxide thickness on AIC growth were investigated. As a result, homogeneous layer exchange was achieved for samples with the whole Ge fractions (x=0-1) by controlling the air exposure time. These new findings will be a powerful tool to obtain high quality poly-SiGe films on glass substrates.

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Indentation-induced solid-phase crystallization (SPC) was proposed to achieve position-controlled crystal growth of Si_1-xGe_x (x: 0-1) on insulating substrates. The results demonstrated that large SiGe grains (>2 μm) over the entire range of Ge fractions were grown at controlled positions without using catalyst metals. In addition, crystal regions were predominantly oriented in the (111) direction for samples with low Ge fractions (<30%), while crystal regions became randomly oriented with increasing Ge fraction (>30%). Although the incubation times of indentation-induced SPC are longer than those of Ni-imprint-induced SPC, indentation-induced SPC is attractive because the crystal grains do not include metals which would degrade the transistor performance.

DOI： 10.1143/JJAP.48.03B007

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

The effects of interfacial oxide layers on the Al-induced crystallization (AIC) of amorphous Si_1-xGe_x (x: 0-1) films on an insulator at a low temperature (<500 °C) have been investigated. In the case of Si, the inversion of the Si/Al layers was achieved for samples with and without interfacial oxide layers between the Si and Al layers. In addition, it was found that the existence of interfacial oxide layers was required to obtain large grain (×100 μm) polycrystalline Si with a (111) orientation. However, in the case of SiGe, the interfacial oxide layers significantly retarded AIC growth. Consequently, layer exchange occurred inhomogenously, which resulted in inhomogenous crystallization even after a long annealing time (410 °C, 100 h). To solve this problem, the effects of interfacial oxide thickness on AIC growth were investigated. As a result, complete layer exchange was achieved for samples with the whole Ge fractions (x: 0-1) by controlling the air exposure time. A qualitative model is presented.

DOI： 10.1143/JJAP.48.03B002

記述言語：その他   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

The effects of amorphous-Si (a-Si) layer (thickness: 0-20 nm) insertion on low-temperature (<450 °C) solid-phase crystallization of a-Ge films (50 nm) were investigated. Upon the insertion of an ultrathin (<3 μm) a-Si layer, incubation time increased and saturated crystallinity slightly increased. On the other hand, upon the insertion of a thick (>10 μm) a-Si layer, incubation time significantly decreased and saturated crystallinity decreased. Grain sizes obtained at 425 °C were ̃200 and ̃50nm upon the insertion of a-Si layers of 3 and 20 nm, respectively, which agrees with the results for saturated crystallinity. Moreover, upon the insertion of an intermediate-thickness (5-7 nm) a- Si layer, the nucleation rate and saturated crystallinity increased. These phenomena were explained on the basis of the Si-concentration profiles at interfaces. Thus, interface modulation is effective for realizing large-grain polycrystalline Ge.

DOI： 10.1143/JJAP.48.03B004

記述言語：その他   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Al-induced crystallization of Si_1-xGe_x films (x=0-0.5) has been investigated by using amorphous SiGe (a-SiGe)/Al structures to realize polycrystalline SiGe (poly-Si) layers on in-sulating films at low temperatures. For the Si sample, poly-Si oriented to the (111) direction was formed after annealing (450 °C, 20 h) and inversion of Si/Al layers occurred completely. For Si_1-xGe_x samples (x > 0), the layer exchange occurred in partial areas and poly-SiGe with the (111) orientation was grown only in the exchanged areas. The Ge fractions of the crystallized SiGe were almost the same as those of the initial a-SiGe layers. The diameters of the crystallized areas decreased from ∼100 (x = 0) to ∼30 μm (x = 0.5) with increasing Ge fraction. This technique can be utilized for the formation of high-quality poly-SiGe at low temperatures.

DOI： 10.3938/jkps.54.451

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Recent our progress in low temperature molecular beam epitaxy of magnetic silicide (Fe₃Si) on group-IV-semiconductor (Ge) was reviewed. By optimizing beam flux ratio (Fe:Si=3:l) and growth temperature (130 °C), a high quality hybrid structure, i.e., DO₃-type Fe₃Si on Ge with an atomically flat interface, was achieved. Excellent magnetic properties with a small coercivity (0.8 Oe) and electrical properties with Schottky barrier height of 0.56 eV were obtained. The ratio of the on-current to the off-current of Schottky diode was the order of 10⁴. These results will be a powerful tool to open up group-IV-semiconductor spin-transistors, consisting of Ge channel with high mobility and Fe₃Si source/drain for spin-injection.

DOI： 10.1109/ICSICT.2008.4734647

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Low temperature epitaxial growth of the full Heusler alloy Fe ₂MnSi layers on Ge(l 11) substrates has been investigated. RBS measurements revealed that good crystallinity of Fe₂MnSi layers was realized at 200°C. In addition, a TEM image of a Fe₂MnSi layer grown at 200°C demonstrated a very sharp interface. Moreover, identical symmetrical structures of electron diffraction patterns were obtained from the Fe₂MnSi layer and the Ge substrate, which confirmed formation of a single crystalline epitaxial Fe₂MnSi layer on Ge. These results will be very attractive for Si-based spintronics applications.

DOI： 10.1149/1.2986782

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Formation of SiGe quasi-single crystal grains on insulator by the indentation-induced solid-phase crystallization has been investigated. The incubation time for nucleation was significantly reduced by the indentation. As a result, large (∼2 (.irn) crystal grains were realized at controlled positions for samples with all Ge fractions. This method is expected to be useful for realization of the 3D-ULSIs and system-in-displays.

DOI： 10.1149/1.2986773

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Effects of oxidation induced Ge condensation on local strains in Si microstructures induced by the SiGe stressor were investigated. The strain ratio in the Si microstructures increased by the Ge condensation, due to piled-up Ge atoms at SiO₂/SiGe interfaces. However, the strains were relaxed by defect generation, if the concentration of piled-up Ge exceeded a critical value (∼40%). Thus, a possibility to enhance local strains by oxidation induced Ge condensation was demonstrated.

DOI： 10.1149/1.2986768

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

The electrical characteristics of epitaxially grown Fe₃Si/Si structures were investigated. From the I-V and C-V measurements, excellent Shottky barrier characteristics (n=1.0, φ))n=0.62eV) were demonstrated. Moreover, the electrical characteristics did not deteriorate after post-annealing (400°C, 1 h), which guaranteed the thermal stability of Fe₃Si/Si structures up to 400°C.

DOI： 10.1149/1.2986783

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Influences of growth temperature on low-temperature (60-400 °C) molecular beam epitaxy of the ferromagnetic silicide Fe₃Si layer on Ge substrates were investigated. X-ray diffraction and reflective high-energy electron diffraction measurements suggested that Fe₃Si layers were epitaxially grown on Ge at a temperature between 60 and 300 °C, while another phase layer was epitaxially grown at 400 °C. Rutherford backscattering spectroscopy measurements revealed that Ge atoms began to diffuse into the Fe₃Si layers above 300 °C, and the FeSiGe layer was formed at 400 °C. As a result, very low value (4.0%) of the minimum scattering yield (χ_min) of the Fe₃Si layers was obtained at 130 °C. Transmission electron microscopy measurements indicated that the interface of Fe₃Si and Ge was atomically flat. In addition, analysis of the electron diffraction patterns of epitaxial Fe₃Si layers confirmed the formation of DO3-type Fe₃Si.

DOI： 10.1016/j.tsf.2008.08.110

記述言語：英語   掲載種別：研究論文（学術雑誌）  

The mechanism for the stress-relaxation in the Ge condensation induced by H⁺ irradiation-assisted oxidation method was investigated. Relaxation ratio of Si_0.7Ge_0.3 (thickness: 28 nm) formed by medium dose H⁺ irradiation (5 × 10¹⁵ cm^{- 2}) and oxidation at 1100 °C was limited to 35%. Post-annealing (1200 °C) improved this value significantly (70%), though defect density was found to be kept at low density (< 10⁶ cm^{- 2}). However, the height of cross hatches was increased (from 0.6 nm to 4.1 nm) after post-annealing. Based on these results, local-area slipping model was proposed, where slipping at SiGe/SiO₂ interface of local areas surrounded by cross hatches enhanced stress-relaxation. This model could quantitatively explain the stress-relaxation enhanced by combination of H⁺ irradiation, oxidation-induced Ge condensation, and post-annealing.

DOI： 10.1016/j.tsf.2008.08.030

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Oriented-crystal growth of CoPt and MgO layers in the [CoPt/MgO]
_n
stacked structures at low-temperatures (< 650 °C) was investigated. For the CoPt (thickness: 40 nm)/MgO (50 nm) structures formed on Si(100) substrates, X-ray diffraction measurements revealed formation of poly-CoPt with random orientations and amorphous MgO. On the other hand, CoPt(111) and MgO(111) layers were dominantly obtained for the [CoPt (4 nm)/MgO (5 nm)]
₁₀
/Si(100) and [CoPt (2 nm)/MgO (2.5 nm)]
₂₀
/Si(100) structures. The (111) oriented growth of CoPt layers was found to be due to the template effect of MgO layers, which were crystallized to the (111) orientation if the layers were thin (< 5 nm).

DOI： 10.1016/j.tsf.2008.08.057

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Growth of ferromagnetic silicide Fe₃Si on SiO₂ was investigated by using the molecular beam deposition technique. Measurements combined with X-ray diffraction and reflective high-energy electron diffraction clearly indicated that poly-crystal Fe₃Si layers were formed on Si(111) substrates covered with thick (> 2.7 nm) SiO₂ films. On the other hand, it is suggested that Fe₃Si layers were epitaxially grown on Si(111) substrates covered with ultra-thin (1.3 nm) SiO₂ films. Transmission electron microscopy and electron diffraction measurements confirmed that single crystalline Fe₃Si layers with (111) orientation were formed on Si(111) substrates with ultra-thin (1.3 nm) SiO₂ films. These results were considered to originate from heteroepitaxy on crystalline ultra-thin SiO₂ layer or lateral epitaxial growth over SiO₂ through pinholes.

DOI： 10.1016/j.tsf.2008.08.121

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Local strain evaluation was performed for single crystal Si pillar (SCSP) by micro Raman spectroscopy and photoluminescence (PL). SCSPs were fabricated by the mesa etching of Si-on-insulator followed by the etching of the buried oxide. The compressive strain was induced to SCSPs by SiN deposition using low-pressure chemical vapor deposition. The strain distribution was clearly observed in the plane of a certain pattern of SCSP. Strain ratio comparison was also performed for SCSPs with different shapes and sizes. Defect-related PL signals were also observed.

DOI： 10.1016/j.tsf.2008.08.021

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Oxidation of SiGe/SOI (Ge fraction: 0-50%) structures was investigated in a wide temperature range. Different oxidation features were observed for samples oxidized in low (< 680 °C), middle (700-800 °C), and high (> 800 °C) temperature regions. Very thin SiO₂ layers (< 150 nm) were formed during low (< 680 °C) temperature oxidation. Thus, the Ge fractions at the SiO₂/SiGe interfaces were almost the same as the initial Ge fractions (< 50%). Therefore, the initial Ge fraction dependent enhanced oxidation was observed. On the other hand, very thick SiO₂ (> 200 nm) was formed during high (> 800 °C) temperature oxidation. Thus, the oxidation rate was limited by the diffusion process of O in SiO₂. Therefore, the oxidation rate did not depend on the Ge fraction. At middle temperatures, the oxidation rate does not depend on the temperature for samples with high initial Ge fractions (> 20%). This is due to that increase in oxidation rate by increasing temperature was cancelled by the retardation of oxidation due to high Ge fractions (> 50%) piled-up at the SiO₂/SiGe interfaces.

DOI： 10.1016/j.tsf.2008.08.025

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Molecular beam epitaxy of the ferromagnetic silicide Fe₃Si on Ge and Si substrates was investigated in a wide temperature range (60-400 °C). Epitaxial growth of Fe₃Si layers was achieved on Ge (110), Ge (111), and Si (111) substrates. Especially, very low value (2.2%) of the minimum scattering yield in RBS measurements was obtained from Fe₃Si layers, which were grown on Ge (111) at low temperature (60-130 °C) under the stoichiometric condition (Fe:Si = 3:1). Transmission electron microscopy measurements confirmed the formation of DO3-type Fe₃Si and atomically flat interface between Fe₃Si and Ge (111). In addition, thermal stability of Fe₃Si was guaranteed up to 300 °C. Such high quality Fe₃Si on Ge (111) substrates can be employed to realize Ge channel spin transistors, which can be integrated with Si large-scale integrated circuits.

DOI： 10.1016/j.tsf.2008.08.055

記述言語：英語  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

To develop silicon-based spintronic devices, we have explored high-quality ferromagnetic _Fe3 Si /silicon (Si) structures. Using low-temperature molecular beam epitaxy at 130 °C, we realize the epitaxial growth of ferromagnetic _Fe3 Si layers on Si(111) with an abrupt interface, and the grown _Fe3 Si layer has the ordered D _O3 phase. Measurements of magnetic and electrical properties for the _Fe3 SiSi (111) yield a magnetic moment of ∼3.16 _μB f.u. at room temperature and a rectifying Schottky-diode behavior with the ideality factor of ∼1.08, respectively.

DOI： 10.1063/1.2996581

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語  

掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：日本語   掲載種別：研究論文（学術雑誌）  

Indentation-Induced Solid-Phase Crystallization of SiGe on Insulator

記述言語：英語   掲載種別：研究論文（学術雑誌）  

We demonstrate the epitaxial growth of ferromagnetic full-Heusler alloy Fe₂MnSi layers on group-IV semiconductor Ge(111) using molecular beam epitaxy at the growth temperatures of 130 and 200 °C. The Fe ₂MnSi/Ge (111) layers have an atomic-scale abrupt interface and include the ordered L2₁ phase. We also show ferromagnetic features with a saturation magnetization of ∼2.2 μB /f.u. and a Curie temperature of ∼210 K, which are nearly comparable to those of bulk Fe₂MnSi.

DOI： 10.1063/1.2977866

記述言語：日本語  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Low-temperature (<500 °C) solid-phase crystallization (SPC) of amorphous Si_1-xGe_x (x: 0-0.7) films was examined on insulating substrates by using Ni-imprint technique. Incubation time for SPC was remarkably reduced by catalytic effects without changing growth velocity. As a result, Ni-free large SiGe grains (∼4 μm) were obtained at controlled positions. The crystallinity of the grown regions was almost the same as that of poly-SiGe formed by the conventional high temperature SPC at 600 °C.

DOI： 10.1016/j.sse.2008.05.009

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Low-temperature (<300 °C) molecular beam epitaxy of Fe ₃ Si/Ge was investigated. By optimizing growth conditions, Fe ₃ Si layers with a flat interface and good crystallinity were epitaxially grown on Ge(1 1 1) substrates. In addition, double heteroepitaxial growth of Fe ₃ Si/Ge on high quality Fe ₃ Si/Ge substrates was investigated. Reflective high-energy electron diffraction measurements suggested Fe ₃ Si and Ge layers were epitaxially grown on Fe ₃ Si/Ge substrates. However, transmission electron microscopy measurements indicated stacking faults formed in the intermediate Ge and top Fe ₃ Si layers. Improved crystallinity of the intermediate Ge layer is essential to realize high quality [Fe ₃ Si/Ge] ₂ multi-layered structures.

DOI： 10.1016/j.apsusc.2008.02.139

記述言語：英語   掲載種別：研究論文（学術雑誌）  

The local strains in Si pillars induced by SiN stressors were quantitatively investigated as a function of geometry by micro-Raman scattering spectroscopy. Raman shifts of a cantilever microstructure were twice as large as those of a bridge microstructure. This difference was due to the different dimensions of the strains, i.e., biaxial strains in the cantilever type and uniaxial strains in bridge type. The thermal stability of the SiN stressor was also investigated. The results showed induced strains were stable after post-annealing at high temperature (∼1000 °C).

DOI： 10.1016/j.apsusc.2008.02.146

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Effects of Fe/Si ratio and growth temperatore were investigated in order to realize high quality Fe₃Si/Ge structures. It was found that very small Xmin values (2-3%) were achieved in a wide temperature range of 60-200°C under the stoichiometrie condition. From TEM nhservation, it was rvealed that the Fe₃Si/Ge structures with atomically flat interfaces were realized. In addition, thermal stability of the Fe₃Si/Ge stmctures was guaranteed up to 400° C. These results suggested that growth at a low temperature (< 200° C) under the stoichiometric condition was essential to obtain high quality Fe₃Si/Ge structures with sharp interfaces.

DOI： 10.1093/ietele/e91-c.5.708

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Effects of Fe/Si ratio and growth temperature were investigated in order to realize high quality Fe₃Si/Ge structures. It was found that very small Xmin values (2-3%) were achieved in a wide temperature range of 60-200°C under the stoichiometric condition. From TEM observation, it was rvealed that the Fe₃Si/Ge structures with atomically flat interfaces were realized. In addition, thermal stability of the Fe₃Si/Ge structures was guaranteed up to 400°C. These results suggested that growth at a low temperature (<200°C) under the stoichiometric condition was essential to obtain high quality Fe₃Si/Ge structures with sharp interfaces.

DOI： 10.1093/ietele/e91-c.5.708

記述言語：日本語  

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Development of new semiconductors with high mobility is strongly needed to realize future system-in-displays. To achieve this, we have been investigating electric field assisted metal-induced lateral crystallization (MILC) of a-Si_1-XGe_X (0<X<1) on insulating substrates. This realizes uniform crystal growth of SiGe with all Ge fractions. In addition, thin-film transistors (TFTs) with Schottky source and drain structures were fabricated, which showed good ambipolar operation characteristics. Present paper reviews such our recent progress of electric field assisted low temperature SiGe growth and discusses the possible application to TFTs with high speed operation.

DOI： 10.1117/12.792280

記述言語：日本語  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

The effects of Ge fraction and annealing temperature on the metal-induced lateral crystallization (MILC) of amorphous SiGe films on an insulator have been investigated. It was shown that the progress of the MILC of amorphous SiGe was suppressed by spontaneous nucleation, which was accelerated with increases in Ge fraction and annealing temperature. Thus, MILC could not proceed for amorphous SiGe with high Ge fractions (>70%) at high temperatures (>500 °C). Spontaneous nucleation was significantly suppressed by lowering the annealing temperature (<400°C). As a result, the MILC of amorphous SiGe was achieved for samples with whole Ge fractions (0-100%), and large polycrystalline silicon-germanium (poly-SiGe) regions (>20μm) could be realized for even high Ge fractions (>70%). Transmission electron microscopy suggested that the mechanism of MILC of amorphous SiGe (a-SiGe) with medium and high Ge fractions (>40%) is different from that of a-Si.

DOI： 10.1143/JJAP.47.1876

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Oxidation characteristics of SiGe (Ge fraction of 0%-50%) layers grown on Si-on-insulator structures were investigated in a wide temperature range, for which different oxidation features were observed in low (<680 °C), middle (700-800 °C), and high (>800 °C) temperature regions. In the low temperature region, enhanced oxidation dependent on the initial Ge fraction of the SiGe layers was observed. This is because the Ge fractions at the Si O2 SiGe interfaces did not change from the initial Ge fractions in this region. In the high temperature region, the oxidation rates did not depend on the Ge fraction. This is because thick Si O2 (>200 nm) formed in this region and, thus, oxidation rates were limited by the diffusion process of O atoms through the Si O2 layer. In the middle temperature region, an abnormal phenomenon was found; i.e., the oxidation rates did not depend on temperature for samples with high initial Ge fractions (>20%). Quantitative relations between the oxidation rate and fraction of Ge atoms piled up at the Si O2 SiGe interfaces were obtained. Based on these findings, a model for temperature independent oxidation was proposed and it explains the contradicting oxidation rates, i.e. Ge enhanced oxidation and Ge retarded oxidation, in the literature.

DOI： 10.1063/1.2894583

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Wc have examined quality of axial oricntation along thc Ge<111> direction in order to find dominant factors for epitaxy control of Fe or Fe layers on Ge(111) by 2.0MeV- ⁴He⁺ ion channeling measurements. The axial channeling along thc Gc<111> orientation reveled that the axial orientation at thc interface betwccn the Heusler alloy layer and Ge dcgraded as thc Mn content increased. This dcgradation may be causcd by increasing of a lattice misfit bctween Fe^3-xMn_xSi and Ge. We discusscd on atomic displacements consisting of thermal vibration and static displaccment due to disorders in the lattice using results obtained from low tcmperature channeling measurements.

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Al-induced crystallization (AIC) of Si and Ge has been comparatively investigated to realize poly-Si and poly-Ge layers on insulating films. For amorphous-Si (a-Si)/Al stacked structures, poly-Si oriented to the (111) direction was formed after annealing (450°C, 40h), and inversion of Si/Al layers occurred completely. On the other hand, poly-Ge with random orientations was formed in the local areas (diameter: 20 μm) of the Al layers after annealing (350°C, 150h) for a-Ge/Al stacked structures. In addition, inversion of Ge/Al layers did not occur. Understanding of AIC of Ge is necessary to establish a new technique for formation of high-quality poly-SiGe at low temperatures.

DOI： 10.1149/1.2778396

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Our recent progresses in epitaxial growth of Fe₃Si on Ge substrates are reviewed. Single crystalline Fe₃Si layers with atomically flat interfaces were achieved on Ge(111) substrates by optimizing growth conditions at low temperatires (60-200°C), Thermal stability of it was guaranteed up to 400°C In addition, epitaxial growth of mixed layers composed of Fs₃Si, FeGe, and FeSi on Ge substrates at 400°C is reported. Finally, epitaxial growth of Fe₃Si/Ge/Fe₃Si/Ge structures is discussed. These results will be a powerful tool to open up SiGe related spintronics.

DOI： 10.1149/1.2778404

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

High-performance poly-Ge thin-film transistors (TFTs) were fabricated using NiGe Schottky contacts as source/drain (S/D). First, formation of NiGe layers by annealing of Ni/n-Ge structures was investigated as a function of annealing temperature, and NiGe/n-Ge Schottky contacts (φ_Bn=0.51 eV) with a low reverse leakage current (∼10^-2A/cm²) were realized at 200-300°C On the basis of the results, NiGe Schottky S/D contacts were fabricated using poly-Ge/quartz s.ubstrates. The TFTs showed good operation characteristics with a hole mobility of ∼140 cm²V ¹s¹. This is a great advantage for the realization of high-performance TFTs for future system-in-displays.

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Double heteroepitaxial growth of Fe₃Si/Ge on high quality Fe₃Si/Ge substrates has been investigated by low-temperature (<300°C) molecular beam epitaxy. Reflective high-energy electron diffraction measurements suggested that Fe₃Si and Ge layers were epitaxially grown on Fe₃Si/Ge substrates, though the surface morphology became rough. X-ray diffraction measurements revealed that a small amount of Fe₃Si(110) was included in the top Fe₃Si layers. Transmission electron microscopy measurements indicated that stacking faults were formed in the intermediate Ge and the top Fe₃Si layers. Improvement of crystal quality of the intermediate Ge layer is essential to realize high quality Fe₃Si/Ge/Fe₃Si multi-layers.

DOI： 10.1149/1.2778406

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

The effects of the Fe/Si ratios on molecular beam epitaxy (MBE) of Fe ₃Si on Ge substrate have been investigated in a wide range of growth temperatures (60-300°C), From XRD measurements, it was found that Fe ₃Si layers were epitaxially grown on Ge(111) substrates at 60-200°C under the stoichiometric (Fe/Si ratio of Fe:Si=3:1) and non-stoichiometric (Fe/Si ratio of Fe:Si=4:1) conditions. From RBS measurement, it was found that atomic mixing of Fe and Ge at Fe₃Si/Ge interfaces began at a growth temperature of 300°C. In the case of MBE under the stoichiometric condition (Fe:Si=3:1), the crystallinity of Fe₃Si is significantly improved compared to the non-stoichiometric condition (Fe:Si=4:1). As a result, very low χ_min was obtained in a wide temperature (60-200°C) under the stoichiometric condition. From the transmission electron microscopy measurements, it was shown that high-quality DO3-type Fe₃Si/Ge structures with atomically flat interfaces were realized at a low temperature (∼200°C) under the stoichiometric condition.

DOI： 10.1149/1.2778405

記述言語：英語   掲載種別：研究論文（学術雑誌）  

The axial orientation of molecular-beam-epitaxy (MBE)-grown Fe3 Si (111) Ge (111) hybrid structures was investigated by Rutherford backscattering spectroscopy. We confirmed that during MBE above 300 °C, the interdiffusion of Fe and Ge atoms results in a composition change and the epitaxial growth of FeGe in Fe3 Si. Low-temperature (<200 °C) MBE can realize fully ordered D O3 - Fe3 Si with highly axial orientation [minimum yield (min) =2.2%]. Postannealing above 400 °C results in a composition change and the degradation of axial orientation in the off-stoichiometric Fe3 Si. The significance of stoichiometry with regard to thermal stability and the interfacial quality of Fe3 Si (111) Ge (111) hybrid structures was also discussed.

DOI： 10.1063/1.2801705

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1016/j.tsf.2007.02.019

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Position control of solid-phase crystallization in the amorphous Si1-x Gex (x: 0-1) films on insulating substrates was investigated by using Ni-imprint technique. Crystal nucleation at the imprinted positions proceeded approximately 2-20 times, depending on Ge fraction, faster than the conventional solid-phase crystallization, which was due to the catalytic effect of Ni. As a result, large SiGe crystal regions (∼2 μm) were obtained at controlled positions. On the other hand, the growth velocity did not changed, which suggested that grown regions contained few residual Ni atoms.

DOI： 10.1063/1.2764447

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Influence of substrate orientation on epitaxial growth of the ferromagnetic silicide Fe₃Si on Si was investigated using low temperature (60-300 °C) molecular beam epitaxy. Transmission electron microscopy (TEM) measurements revealed that Fe₃Si layers were epitaxially grown on Si(110) and Si(111), while random poly-crystal Fe₃Si layers were formed on Si(100). From the Rutherford backscattering spectroscopy measurements, the values of the χ_min of the Fe₃Si layers grown at 60 °C on Si(100), Si(110), and Si(111) were evaluated to be 100%, 97%, and 41%, respectively. This dependence on the substrate orientation was explained on the basis of the atomic alignments at the Fe₃Si/Si interfaces.

DOI： 10.1016/j.tsf.2007.02.052

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

The fabrication of Ge-channel thin-film transistors (TFTs) with Schottky source/drain (S/D) contacts was investigated. First, the annealing characteristics of Ni/c-Ge stacked structures were examined. NiGe/n-Ge Schottky contacts (Φ_Bn = 0.51 eV, n = 1) with a low reverse leakage current [(2-5) × 10^-2 A/cm²] were obtained at 200-300 °C. Second, the electrical characteristics of Al/SiO ₂/c-Ge metal-oxide-semiconductor (MOS) structures were investigated, in which SiO₂ films were formed by plasma-enhanced chemical vapor deposition at 250 °C. The MOS structures were proven acceptable for device operation. On the basis of the obtained results, TFTs with NiGe Schottky S/D contacts were fabricated using poly-Ge/quartz substrates. The maximum processing temperature was 500 °C in the solid-phase crystallization of a-Ge films. The TFTs showed good p-channel operation characteristics with a mobility of ∼ 100cm² V^-1 s^-1 without showing kink effects. This is a great advantage for the realization of high-performance TFTs for system-in-displays.

DOI： 10.1143/JJAP.46.1250

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Development of high-mobility semiconductors is strongly needed to realize high-performance thin-film transistors. To achieve this, we have been investigating low temperature solid-phase crystallization and metal-induced lateral crystallization of a-SiGe on insulating substrates. These realize uniform crystal growth of SiGe with all Ge fractions. In addition, thin-film transistors with Schottky source and drain structures were fabricated, which showed good ambipolar operation characteristics. Present paper reviews such our recent progress of low temperature SiGe growth and discusses the possible application to thin-film transistors with high speed operation. copyright The Electrochemical Society.

DOI： 10.1149/1.2355858

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Low-temperature (60 °C) molecular beam epitaxy (MBE) of Fe3 Si layers on Ge substrates was investigated. From x-ray diffraction and transmission electron microscopy measurements, it was shown that Fe3 Si layers including the DO3 type were epitaxially grown on Ge(110) and Ge(111), while polycrystal Fe3 Si was formed on Ge(100). Although the Fe3 SiGe (110) interface was slightly rough (∼1 nm), the Fe3 SiGe (111) interface was atomically flat. Such atomically controlled MBE of Fe3 Si on the Ge(111) substrate can be employed to realize Ge channel spin transistors, which can be integrated with Si large-scale integrated circuits.

DOI： 10.1063/1.2378399

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Metal-induced lateral crystallization (MILC) of amorphous SiGe films on Si O2 has been investigated as a function of Ge fraction (0%-100%) and annealing temperature (320-550 °C). High temperature annealing (>500 °C) caused spontaneous nucleation in amorphous SiGe with a high Ge fraction (>70%). This suppressed the progress of MILC. Spontaneous nucleation was significantly suppressed by lowering the annealing temperature (<400 °C). As a result, large poly-SiGe regions (>20 μm) were observed around Ni patterns even for high Ge fractions (>70%). In this way, MILC of amorphous SiGe was achieved for samples with whole Ge fractions (0%-100%).

DOI： 10.1063/1.2374849

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Poly-Ge thin-film transistors (TFTs) with Schottky source/drain (S/D) contacts were fabricated on glass by low-temperature (<500 °C) processing. First, the annealing characteristics of Ni/crystal-Ge stacked structures were examined. The results indicated that NiGen-Ge Schottky contacts (φ Bn =0.51 eV, n=1) with flat interfaces and low reverse leakage current [(2-5) × 10-2 A cm2] could be obtained by choosing an appropriate annealing temperature (200-300 °C). Based on this result, p -channel TFTs were fabricated with poly-Ge formed on glass by solid-phase crystallization at 500 °C. TFTs showed relatively high hole mobility (about 140 cm2 V s) with very low S/D parasitic resistance and no kink effect. The potential capability of the proposed devices for high-performance TFTs was demonstrated.

DOI： 10.1063/1.2387136

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

Metal-induced lateral crystallization of amorphous Si has been investigated under a wide range of electric fields (0-4000 V/cm). In the low field region (<100 V/cm), lateral growth velocity at the cathode side was enhanced by applying an electric field. This achieved formation of poly-Si with a large area (∼50 μm) during low-temperature annealing (525°C, 25 h). When the electric field exceeded 100 V/cm, the lateral growth velocity decreased with increasing the electric field strength. Under the extremely high electric field (>2000 V/cm), directional growth aligned to the electric field was observed. This new findings will be a powerful tool to achieve new poly-Si with highly controlled structures.

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

The recent progress of SiGe hetrostructure technologies is reviewed by using the authors' results. Low temperature (<550°C) methods to achieve SiGe crystals on insulating films are developed by the combination of metal induced lateral crystallization and electric field application. In addition, epitaxial growth of ferromagnetic silicide on Si and Ge substrates becomes possible at 60-300°C. These results will be the key techniques to open new era of SiGe-based thin film transistors and spintronics devices. Copyright The Electrochemical Society.

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

The oxidation-induced Ge condensation process of SiGe/Si on insulator structures has been investigated. The relaxation rate obtained in the SiGe layers on insulator (SGOI) abruptly decreased with decreasing SGOI thickness below 50 nm. In order to enhance the relaxation rate in the ultra-thin SGOI, the new technique combined with H⁺ irradiation with a medium dose (5 × 10¹⁵ cm^{- 2}) and post-annealing (1200 °C) has been developed. It was demonstrated that the highly relaxed (70%) ultra-thin SGOI with a low defect density (8 × 10⁶ cm^{- 2}) has been realized by this technique.

DOI： 10.1016/j.tsf.2005.07.316

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Morphological changes of Co nanodots on SiO₂ layers by thermal treatment have been investigated. Co nanodots were formed by molecular beam deposition of Co on SiO₂ layers with substrate temperatures (30-600 °C) and subsequent post-annealing (500-800 °C). For samples deposited at low temperatures (30-280 °C), the diameter and the density of nanodots increased and decreased, respectively, with increasing post-annealing temperature. On the other hand, the diameter and the density of nanodots scarcely changed by post-annealing for samples deposited at high temperatures (430-600 °C). These morphological changes by the post-annealing can be explained on the basis of the stress relaxation in the deposited Co films.

DOI： 10.1016/j.tsf.2005.10.005

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Ni-mediated lateral crystallization of amorphous Si has been investigated under a wide range of electric fields (0-4000 V/cm). In the low field region (< 100 V/cm), lateral growth velocity at the cathode side was enhanced by applying an electric field. This achieved formation of poly-Si with a large area (∼ 50 μm) during low-temperature annealing (525 °C, 25 h). When the electric field exceeded 100 V/cm, the lateral growth velocity decreased with increasing the electric field strength. Under the extremely high electric field (> 2000 V/cm), directional growth aligned to the electric field was observed. These new findings will be a powerful tool to achieve new poly-Si with highly controlled structures.

DOI： 10.1016/j.tsf.2005.07.315

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Ni metal-induced lateral crystallization (Ni-MILC) of amorphous Si_0.6Ge_0.4 thin films has been investigated by means of scanning electron microscopy and transmission electron microscopy. A pattern of Ni about 5 nm thick was fabricated to cover selective areas of the a-Si_0.6Ge_0.4 film. Subsequently, the thin film was annealed at 550 °C for various lengths of time. In the area covered with Ni, Ni atoms diffuse into the SiGe film and react with Ge to produce precipitates of Ni₂Ge, leaving amorphous Si. In the area outside of the Ni-covered one, on the other hand, crystallization occurs to form aggregates of small Si_0.6Ge_0.4 grains without Ni incorporation. In the MILC process, the kind of Ni compound phase changes with the amount of diffusing Ni and the lateral crystallization should be induced by the formation of NiSi₂.

DOI： 10.1016/j.tsf.2005.06.102

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Au-induced lateral crystallization of amorphous Si_1-xGe_x (x: 0-1) on SiO₂ at a low temperature (400 °C) has been investigated. Although the growth velocity decreased with increasing Ge fraction, growth velocity exceeding 20 μm/h was obtained for all Ge fractions. As a result, poly-Si_1-xGe_x with large areas (> 20 μm) was obtained at a low temperature (400 °C). This is a great advantage of Au-induced lateral crystallization compared with Ni. However, the concentrations in the surface regions (depth: 0-20 nm) of the lateral growth regions were high (10-30%), though those in the deeper regions (depth: 20-50 nm) were as small as 1-2%. Removing of the surface regions with the high Au concentrations and gettering of Au atoms in the deeper regions are necessary to apply the grown layers to the device fabrication.

DOI： 10.1016/j.tsf.2005.07.317

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Thin-film transistors (TFTs) with Schottky source/drain (S/D) structures were fabricated using NiSi and laser-annealed polycrystalline silicon (poly-Si) as Schottky barrier metals and active layers, respectively. The whole fabrication process was performed at low temperatures (<500°C). The TFTs showed good ambipolar operation characteristics with I_on/I _off of ∼10⁵ for both the p-channel and n-channel modes. Moreover, the kink effects due to floating body effects, which were observed in conventionally doped S/D TFTs, were successfully suppressed.

DOI： 10.1143/JJAP.45.4370

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

The low-temperature (<550°C) metal-induced lateral crystallization of amorphous Si_1-xGe_x. (x: 0-1) on SiO₂ has been investigated under a wide range of electric fields (0-4000 V/cm). The increase in the lateral growth velocity with electric field was observed on the cathode side. However, when electric field exceeded a certain value, lateral growth velocity decreased. With increasing Ge fraction, critical field at which lateral growth velocity showed maximum decreased, and the maximum growth velocity increased. In addition, the directional growth of needlelike crystals aligned to the electric field was observed under an extremely high electric field (>2000 V/cm). These new findings will be a powerful tool for achieving new poly-SiGe with highly controlled crystal structures.

DOI： 10.1143/JJAP.45.4351

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

The oxidation-induced Ge condensation of SiGe/Si-on-insulator structures was investigated. The relaxation rate of SiGe on insulator (SGOI) abruptly decreased with SiGe thickness below 50nm. To enhance the relaxation rate in ultra thin SGOI, a new technique combined with intermediate-dose H⁺ implantation (5 × 10¹⁵ cm^-2) and post annealing (1200°C) was developed. It was demonstrated that highly relaxed (70%) ultra thin SGOI with a low defect density (<10⁶ cm^-2) is realized by this technique.

DOI： 10.1143/JJAP.45.3147

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Strain-relaxation process of SiGe-on-insulator (SGOI) structures in the oxidation induced Ge condensation method has been investigated as a function of the SiGe thickness. Complete relaxation was obtained for thick SGOI layers (>100 nm). However, the relaxation rates abruptly decreased with decreasing SiGe thickness below 50 nm, i.e., the relaxation rate of 30% at 30 nm SiGe thickness. In order to improve this phenomenon, a method combined with H+ irradiation with a medium dose (5× 1015 cm-2) and postannealing (1200 °C) has been developed. This successfully achieved the high relaxation rate (70%) in the ultrathin SGOI (30 nm).

DOI： 10.1063/1.2192644

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Epitaxial growth of the ferromagnetic suicide Fe₃Si on Si substrates was investigated using molecular beam epitaxy. X-ray diffraction (XRD) measurements revealed that the Fe₃Si phase was formed at 60-300°C, and the FeSi phase was formed at 400°C. From the results of XRD and transmission electron microscopy measurements, it was found that the Fe₃Si(111) layers were epitaxially grown on Si(111) substrates, while random poly-crystal Fe₃Si layers were formed on Si(100) substrates. Detailed XRD measurements showed that a small amount of DO3-type Fe ₃Si was formed together with the B2-type Fe₃Si. Vibrating sample magnetometer measurements revealed that Fe₃Si(111) layers on Si(111) substrates have in-plane magnetic anisotropy with a period of 180°.

DOI： 10.1143/JJAP.45.3598

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Development of new semiconductors with high carrier mobility is strongly needed to realize future system-in-displays. To achieve this, we have been investigating low-temperature crystallization of a-Si1-xGex (0 ≦x≦1) on insulating films. Present paper focuses our recent progress of the Ni-induced lateral crystallization of a-Si1-xGex (0≦x≦1). Effects of the Ge fraction and the electric field on the growth characteristics are discussed.

DOI： 10.1541/ieejeiss.126.1073

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Pulsed-XeCl excimer laser crystallization of germanium (Ge) and silicon-germanium (SiGe) alloy films formed on quartz glass substrates was investigated. The transient conductance measurements reveled that germanium films were rapidly melted and solidified because of low latent heat compared to silicon films. Formation of silicon-germanium alloy was also observed in the case of laser annealing the Ge/Si layered structure. The crystalline volume ratio was estimated almost 1.0 for Si_0.4Ge_0.6 films because of small disordered electronic states at grain boundaries, while it was 0.85 for Si films.

DOI： 10.1016/j.tsf.2005.01.037

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Postannealing characteristics of in situ doped B atoms in poly- Si1-x Gex (x≤0.5) films on SiON have been investigated. Supersaturated electrically active B (2× 1020 cm-3) is obtained for as-chemical vapor deposition samples, and their thermal stability is significantly improved by increasing Ge fraction, e.g., the stability for poly- Si0.6 Ge0.4 is ten times as high as that for poly-Si at 700-800°C. Such a Ge induced improvement will be a powerful tool to achieve poly-SiGe gate electrode for the next generation ultralarge scale integrated circuits. In addition, the deactivation process of electrically active B has been analyzed. Results indicated that deactivation processes consist of fast and slow processes. The former is due to movement of B atoms from substitutional to interstitial sites, which is enhanced by a local strain induced by the difference in atomic radii between Si and B atoms. The slow process was due to trapping of B at grain boundaries during grain growth. The two-state model based on the local strain compensation by Ge doping is proposed, which can well explain the Ge dependent thermal stability of electrically active B atoms.

DOI： 10.1063/1.1854731

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Effects of H+ implantation (≤5× 1016 cm-2) on stress relaxation in an oxidation-induced Ge condensation method have been investigated to form stress-relaxed ultrathin (~30 nm) SiGe-on-insulator (SGOI) virtual substrates. High-dose (≤ 1015 cm-2) implantation enhanced stress relaxation, which was attributed to bond breaking at the SiGeburied SiO2 interface. However, oxidation velocity was also enhanced due to irradiation defects. Two-step annealing (500 °C for 30 min and 850 °C for 60 min) before oxidation was proposed to remove irradiation defects. This achieved enhanced stress relaxation in ultrathin SGOI without changing oxidation velocity.

DOI： 10.1063/1.1935028

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

The Au-mediated low-temperature (400°C) crystallization of amorphous-Si_1-xGe_x (x: 0-1) on SiO₂ has been investigated. A growth velocity exceeding 20μm/h was obtained for samples in the entire range of Ge fractions (x: 0-1), although it decreased with increasing Ge fraction. These values are much higher than those obtained by conventional Ni-mediated crystallization. As a result, strain-free poly-S _1-xGe_x (x: 0-1) with large areas (>20μm) were obtained at a low temperature (400°C). This newly developed method has a high potential for fabricating poly-Si_1-xGe_x (x: 0-1) on a glass substrate.

DOI： 10.1143/JJAP.44.2405

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

The effects of the H^- implantation (8.1 keV and 0-5 × 10¹⁶ cm^-2) and two-step annealing (1st: 500°C for 30 min, 2nd: 850°C for 60 min) on the stress relaxation of c-Si _1-xGe_x buffer layers on insulator (SGOI) formed by the oxidation-induced Ge condensation process have been investigated. The stress relaxation of SGOI during oxidation (1100°C) was significantly improved by high-dose (>10¹⁵ cm^-2) H⁺ implantation. However, the oxidation was also enhanced by the implantation. The enhanced oxidation was completely suppressed by the two-step annealing before oxidation. The enhanced stress relaxation was attributed to the enhanced gliding of the c-Si_1-xGe_x layers on SiO₂. This newly developed combination method of H^- implantation, the two-step annealing, and the oxidation-induced Ge condensation will be a powerful tool in the fabrication of highly relaxed SGOI for growth of strained Si layers.

DOI： 10.1143/JJAP.44.2357

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Au-induced low-temperature (400 °C) crystallization of amorphous-Si_1-xGe_x (x: 0-1) thin films on SiO₂ has been investigated. Although the growth velocity decreased with increasing Ge fraction, growth velocity exceeding 20 μm/h was obtained in all Ge fractions. As a result, strain-free poly-Si_1-xGe_x with large areas (>20 μm) were obtained at a low temperature (400 °C). These new polycrystalline SiGe films on insulator could be used for advanced system in display and three-dimensional ULSI.

DOI： 10.1016/j.mssp.2004.09.060

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Enhancement effects of H⁺ implantation on stress relaxation of c-Si_1-xGe_x layers on SiO₂ during oxidation-induced Ge condensation process have been investigated. Stress relaxation of c-Si_1-xGe_x layers during oxidation (1100 °C) was significantly improved by high-dose (>10¹⁵ cm ^-2) H⁺ implantation. However, oxidation was also enhanced by implantation. Enhanced oxidation was completely suppressed by the two-step annealing (1st: 500 °C for 30 min, 2nd: 850 °C for 60 min) before oxidation. The enhanced stress relaxation was tentatively assigned to enhanced gliding of c-Si_1-xGe_x layers on SiO₂. This newly developed combination method of H⁺ implantation, two-step annealing, and oxidation-induced Ge condensation will be a powerful tool to fabricate highly relaxed c-Si_1-xGe_x buffer layers for growing strained Si layers.

DOI： 10.1016/j.mssp.2004.09.043

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Ni-mediated low-temperature solid-phase crystallization in a-Ge/a-Si/SiO₂ layered structure has been investigated. Crystal nucleation was initiated in the a-Ge layer, which stimulated the bond rearrangement in a-Si. This enhanced lateral crystallization velocity of a-Si three times greater than that of a-Si/SiO₂ single structure. As a result, poly-Si films with large areas (∼10 μm for 5 h and ∼30 μm for 15 h) were obtained after 550 °C annealing. This will be a powerful tool for realizing large poly-Si areas on insulating films for system-in-displays and three-dimensional ultra-large-scale integrated circuits.

DOI： 10.1016/j.mssp.2004.09.036

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

The Ge condensation by oxidation of SiGe/Si-on-insulator (SOI) structures enabled highly stress relaxed SGOI. However, the relaxation rate obtained in the SiGe layers on insulator (SGOI) abruptly decreased with decreasing SiGe thickness below 50 nm. In order to enhance the relaxation rate in ultra-thin SGOI, the technique combined with H⁺ irradiation with medium dose (5×10¹⁵ cm^-2) and post-annealing (1200 °C) has been developed. It was demonstrated that highly relaxed (70 %) ultra-thin SGOI with low defect density (<10⁶ cm^-2) has been realized by this technique.

DOI： 10.1557/proc-0908-oo05-21

記述言語：英語   掲載種別：研究論文（学術雑誌）  

The effects of the H⁺ implantation (8.1 keV and 0–5×10¹⁶ cm⁻²) and two-step annealing (1st: 500°C for 30 min, 2nd: 850°C for 60 min) on the stress relaxation of c-Si_1−xGe_x buffer layers on insulator (SGOI) formed by the oxidation-induced Ge condensation process have been investigated. The stress relaxation of SGOI during oxidation (1100°C) was significantly improved by high-dose (>10¹⁵ cm⁻²) H⁺ implantation. However, the oxidation was also enhanced by the implantation. The enhanced oxidation was completely suppressed by the two-step annealing before oxidation. The enhanced stress relaxation was attributed to the enhanced gliding of the c-Si_1−xGe_x layers on SiO₂. This newly developed combination method of H⁺ implantation, the two-step annealing, and the oxidation-induced Ge condensation will be a powerful tool in the fabrication of highly relaxed SGOI for growth of strained Si layers.

DOI： 10.1143/JJAP.44.2357

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Pulsed laser rapid annealing of silicon-germanium (SiGe) films on quartz glass substrate was investigated. Laser-induced melt-regrowth properties were analyzed by the transient conductance measurements. The maximum electrical conductivity of the germanium films associated with the maximum melt depth was increased from 370 to 4420 S/cm as laser energy density increased from 130 to 200 mJ/cm². The complete melting of the films was observed at laser energy density above 200 mJ/cm². The electrical conductivity of the silicon films was increased from 340 to 4480 S/cm as laser energy density increased from 280 to 530 mJ/cm². The melt duration of germanium films slightly increased from 73 to 81 ns as the laser energy density increased from 130 to 180 mJ/cm². On the other hand, the melt duration of the silicon films was increased from 56 to 120 ns as laser energy density increased from 330 to 500 mJ/cm². In the complete melting condition, they were furthermore increased to 117 and 145 ns for germanium and silicon, receptivity. The average size of crystalline grain was increased from 66 to 120 nm as germanium concentration increased from 20 to 60 %. The crystallization to the lateral direction induced by the deep melting and rapid solidification increased the grain size.

DOI： 10.1117/12.596398

記述言語：英語   掲載種別：研究論文（学術雑誌）  

The effects of local Ge doping on the crystal nucleation in the solid-phase crystallization (SPC) of a-Si films on SiO₂ films were investigated. Three types of sample structures, (a) a-Si/a-Ge/a-Si/SiO₂, (b) a-Si/a-Ge/SiO₂, and (c) SiO₂/a-Ge/a-Si/SiO₂, were prepared and annealed at 600 °C. For the structure (a) with a thin (∼5 nm) Ge film, Ge atoms completely diffused into a-Si films, and SPC was not enhanced. On the other hand, for the structure (a) with Ge films thicker than 10 nm, Ge atoms were localized at the initial position. Such abnormal retardation of Ge diffusion was remarkable for the structures (b) and (c) even for samples with thin Ge films. For samples with Ge localization, significant enhancement of SPC of a-Si was observed. These results indicated that crystal nucleation was initiated in the localized Ge films, and then propagated into a-Si films. The local Ge doping at a-Si/SiO₂ interfaces can be employed to selectively induce the nucleation at the interfaces.

DOI： 10.1016/j.tsf.2004.06.010

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Solid-phase growth of the [a-Si/a-FeSiGe] _n (n: 1, 2, 4; total thickness: 500nm) stacked structure has been investigated. After annealing at 700°C, the [a-SiGe/β-FeSi ₂ (Ge)] _n stacked structures were formed. From the analysis of the X-ray diffraction spectra, it was found that β-FeSi ₂ (Ge) was strained by 0.4-0.5% for n = 1. With increasing n, the strains decreased, which was due to segregation of Ge atoms from the a-FeSiGe layers to the a-Si layers. After annealing at 800°C, agglomeration of β-FeSi ₂ occurred and Ge atoms vanished completely from the β-FeSi ₂ lattice. Thus, nanocrystals of relaxed β-FeSi ₂ and c-Si _0.7 Ge _0.3 were formed. These new structures can be useful for formation of opto-electrical devices.

DOI： 10.1016/S0169-4332(04)01007-4

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Growth of SiGe/β-FeSi₂ superstructures by annealing of a-Si/a-FeSiGe layered structures was investigated for control of the strains in β-FeSi₂ by Ge doping. The [a-SiGe/β-FeSi ₂(Ge)]_n multi-layered structures were formed after annealing at 700°C. From the analysis of the X-ray diffraction (XRD) spectra, it was found that β-FeSi₂(Ge) was strained by 0.4-0.5% for the sample with n=1. The strains decreased with increasing n, which was due to that the segregation of the Ge atoms from the a-Fe_0.4Si _0.5Ge_0.1 layers to the a-Si layers became large with increasing n. After annealing at 800°C, agglomeration of β-FeSi ₂ occurred, and nanocrystals of relaxed β-FeSi₂ and c-Si_0.7Ge_0.3 were formed. These demonstrate that the SiGe/β-FeSi₂ superstructures were formed by the Ge segregation. These new structures are useful for formation of opto-electrical devices.

DOI： 10.1016/j.tsf.2004.02.068

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1016/j.tsf.2004.02.048

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Dependence of solid-phase growth of β-FeSi₂ thin films on the crystal orientation of Si substrates has been investigated by using a-Fe (thickness: 20 nm)/c-Si(100), (110) and (111) stacked structures. X-ray diffraction (XRD) measurements suggested that the substrate orientation dependence of the formation rate of β-FeSi₂ was as follows: (100)>(111)>(110). This dependence can be explained on the basis of the lattice mismatch between β-FeSi₂ and Si substrates, i.e., the lattice mismatch between β-FeSi₂(100) and Si(100), β-FeSi₂(110) or (101) and Si(111), and β-FeSi ₂(010) or (001) and Si(110) of 1.4-2.0%, 5.3-5.5% and 9.2%, respectively. The substrate orientation dependence of solid-phase growth becomes relatively remarkable for very thin films.

DOI： 10.1016/j.tsf.2004.02.065

記述言語：英語   掲載種別：研究論文（学術雑誌）