Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1587/transinf.2018PAP0003

Repository Public URL： https://hdl.handle.net/2324/7174313

Language：Japanese   Publishing type：Research paper (scientific journal)  

Language：English  

Moore’s Law, relating to the speed and capabilities of computers is becoming less applicable. In this ‘post-Moore’ era, a cross-disciplinary team based in the Constructive Electronics Laboratory, Kyushu University, Japan, is investigating optical computing system infrastructures, with a view to driving computing technology forward in a way that negates the need to comply with Moore’s Law. Associate Professor Satoshi Kawakami is an expert in electric circuits and computer architecture who is part of the team. The team’s expertise covers materials, devices, circuits, architectures and algorithms and is geared towards pioneering new computing technologies in the post-Moore era. Kawakami believes that the continuous improvement of computer systems with higher performance and lower power consumption/energy consumption will be essential to realise a sustainable advanced information society and wants to maximise the advantages of devices and hide their disadvantages at the system level, which will necessitate collaboration with higher system layers. Another important goal is reducing power consumption by improving the efficiency of computers. In one current project, the researchers are exploring optical computing system infrastructure for simple recurrent neural networks. The team is keen to re-examine the ideal state of optical circuits from the perspective of the entire system, including electrical memory and interfaces.

CiNii Research

Language：English   Publishing type：Research paper (scientific journal)  

Repository Public URL： https://hdl.handle.net/2324/7178878

Language：English   Publisher：The Institute of Electronics, Information and Communication Engineers  

<p>The performance improvement by CMOS circuit technology is reaching its limits. Many researchers have been studying computing technologies that use emerging devices to challenge such critical issues. Nanophotonic technology is a promising candidate for tackling the issue due to its ultra-low latency, high bandwidth, and low power characteristics. Although previous research develops hardware accelerators by exploiting nanophotonic circuits for AI inference applications, there has never been considered for the acceleration of training that requires complex Floating-Point (FP) operations. In particular, the design balance between optical and electrical circuits has a critical impact on the latency, energy, and accuracy of the arithmetic system, and thus requires careful consideration of the optimal design. In this study, we design three types of Opto-Electrical Floating-point Multipliers (OEFMs): accuracy-oriented (Ao-OEFM), latency-oriented (Lo-OEFM), and energy-oriented (Eo-OEFM). Based on our evaluation, we confirm that Ao-OEFM has high noise resistance, and Lo-OEFM and Eo-OEFM still have sufficient calculation accuracy. Compared to conventional electrical circuits, Lo-OEFM achieves an 87% reduction in latency, and Eo-OEFM reduces energy consumption by 42%.</p>

DOI： 10.1587/transinf.2024pap0003

CiNii Research

Publisher：Proceedings -Design, Automation and Test in Europe, DATE  

This paper proposes a random walk circuit imple-mentation with single flux quantum devices, essential for Brownian circuits, to reduce processing energy consumption dramatically. SPICE-based simulation demonstrating its functional operation and random walks can be achieved via the Shapiro- Wilk test. Furthermore, we developed a Monte Carlo simulator for Brownian circuits, enabling functionality verification and computation step distribution analysis. Latency/energy evaluation using a half-adder as a case study revealed that proposed circuits could reduce energy consumption by 1/1260 and offer an opportunity for low-power computing systems.

Scopus

Publisher：LEOS Summer Topical Meeting  

We show our recent progress for scaling-up the optical computing engine using silica-based waveguide technology and its combination with free-space-optics (FSO). Owing to the dense parallelization in both space and wavelength division, our device can improve computational speed to sub-peta OPS scale.

DOI： 10.1109/SUM60964.2024.10614538

Scopus

Language：English   Publishing type：Research paper (international conference proceedings)  

Repository Public URL： https://hdl.handle.net/2324/7178876

Language：English   Publishing type：Research paper (international conference proceedings)  

Language：English   Publishing type：Research paper (scientific journal)  

Publisher：IEEE Transactions on Applied Superconductivity  

We demonstrate the functioning of a high-throughput, gate-level-pipelined floating-point adder and multiplier over 50 GHz. The gate-level-pipelined floating-point adder and multiplier requires dedicated circuit blocks to wait until other circuit blocks complete calculations because of the dependence between their sign, exponent, and significand parts. We revealed that the resultant delay difference of the waiting circuit blocks hinders high-frequency operation if the predesigned circuit blocks with the fixed clock distribution are connected in a simple manner. We showed that clock distribution needs to synchronize with every pipeline stage regardless of the circuit blocks to minimize the delay difference between the circuit blocks for circuits containing the waiting circuit blocks (e.g., the floating-point adder and multiplier). We designed a 5-bit floating-point adder and multiplier to demonstrate the effectiveness of the clock distribution experimentally. The test chips were fabricated using AIST 10-kA/cm$\boldsymbol{^{2}}$ Advanced Process 2. We verified the high-speed operation at over 50 GHz in the floating-point adder and multiplier. The maximum clock frequency and throughput of the floating-point adder were 56 GHz and 56 GFLOPS, respectively. The corresponding values for the floating-point multiplier were 63 GHz and 63 GFLOPS, respectively.

DOI： 10.1109/TASC.2023.3250614

Web of Science

Scopus

Language：English   Publishing type：Research paper (international conference proceedings)  

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1145/3587135.3592187

Web of Science

Publisher：Proceedings - 2023 16th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2023  

Operating IoT devices by supplying power from an energy harvester and installing AI accelerators in IoT devices are required. Nevertheless, conventionally selected architectures for AI processing require a large amount of power, making it difficult to operate in low-power bands such as IoT devices or even impossible to operate in the first place. Therefore, driving AI accelerators with power that energy harvesters can supply is an issue. However, there has been no past exploration of AI accelerators in the driven of the μW scale. In this paper, we analyze the configuration of Vector Matrix Multiplier, mainly used for AI accelerators, and show the effective configuration for μW scale IoT devices. Using 180nm CMOS to synthesize the four architectures of various sizes, we characterize device performance and analyze energy consumption and circuit area. As a result of the analysis, it shows that the configuration in which all calculations are deployed on the circuit can have the lowest energy consumption. In addition, we found that when there is a limit on circuit area, a configuration in which some calculations are performed in the time domain by lowering the voltage is suitable.

DOI： 10.1109/MCSoC60832.2023.00018

Web of Science

Scopus

Language：English   Publisher：Information Processing Society of Japan  

<p>This paper analyzes the impact of input sparsity and DFS/DVFS configurations for single-board computers on the execution time, power, and energy of each VGG16 layer as the first step towards efficient CNN inference on single-board computers. For this purpose, we first develop a power and execution time measurement environment and perform experiments using Raspberry Pi 4 and NVIDIA Jetson Nano. Our results show that clock frequency strongly correlates with execution time and power. Inversely, input sparsity has a weak correlation with execution time and power. Then, we show that a coarse-grained DVFS model can explain over 96% of the variations in the power of each VGG16 layer even when sets of clock frequency and voltage on the single-board computer are unavailable.</p>

DOI： 10.2197/ipsjjip.31.478

Scopus

CiNii Research

Language：English   Publishing type：Research paper (international conference proceedings)  

Language：English   Publishing type：Research paper (international conference proceedings)  

Language：English   Publishing type：Research paper (international conference proceedings)  

Language：English   Publishing type：Research paper (other academic)  

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (international conference proceedings)  

Publisher：Proceedings - IEEE International Symposium on Circuits and Systems  

This paper presents the design of an ultra-high-speed, low-power arithmetic unit that supports variable bit-width operations with single flux quantum (SFQ) technology. Because of the high-speed nature of superconductor devices, we can achieve extremely high power-performance efficiency that cannot be achieved by state-of-the-art CMOS devices. To implement the complex function to support the variable bit-width feature, we introduce a novel circuit architecture to maintain the high-speed operation over 50GHz. Our prototype chip design successfully demonstrated 53.5GHz 1.59mW operations.

DOI： 10.1109/ISCAS48785.2022.9937317

Web of Science

Scopus

Publisher：Proceedings - 2022 IEEE 15th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2022  

The performance improvement by CMOS circuit technology is reaching its limits. Many researchers have been studying computing technologies that use emerging devices to challenge such critical issues. Nanophotonic technology is a promising candidate due to its ultra-low latency, high bandwidth, and low power natures. The advanced research activity of nanophotonic computing is to design hardware accelerators for AI inference applications. However, few considerations about nanophotonic accelerators for AI training applications have been conducted. The main reason is that state-of-the-art nanophotonic AI accelerators involve integer operations, whereas floating-point (FP) sum-of-products dominate the training process. However, to the best of the authors' knowledge, there are no optical circuits that target floating-point arithmetic units. This study proposes a novel Opto-Electrical Floating-point Multiplier (OEFM) toward ultra-low-latency, a power-efficient nanophotonic accelerator for AI training applications. We design a microarchitecture of OEFM, including a novel optical integer multiplier and other electrical components. Based on our evaluation framework, we analyze the calculation accuracy of the proposed multiplier and OEFM. Experimental results show that OEFM achieves a 56 % reduction in latency and a 41 % reduction in energy consumption compared with a conventional electrical circuit.

DOI： 10.1109/MCSoC57363.2022.00057

Scopus

Publisher：2022 IEEE 8th World Forum on Internet of Things, WF-IoT 2022  

Recently IoT edge devices have become more diverse and lower cost. In addition, small low-power single-board computers' computing performance has significantly increased. These conditions make it possible to process locally without communicating to the cloud. Since the advantages of in-edge processing are security and privacy, we applied in-edge IoT to smart homes with rich private information to be secured. In in-edge processing, conventional cloud-managed abnormality monitoring and system maintenance cannot be involved. We developed a lamp control system with in-edge processing. It detects failures using camera image processing and recovers from the failure. The abnormalities of the image processing are detected by monitoring cyclic outdoor brightness change observed on windows captured with the same camera. We have developed a prototype system with Python with OpenCV and FastAPI, etc., over PHP-based lamp timer control while keeping source code size small and considering validation easiness. The camera detectors work at 10 FPS on Python with as small as 1607 total source code lines (three times of code lines against the original lamp control timer).

DOI： 10.1109/WF-IoT54382.2022.10152281

Web of Science

Scopus

Publisher：Proceedings - 2022 IEEE 15th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2022  

Recurrent neural networks (RNNs) have achieved high performance in inference processing that handles time-series data. Among them, hardware acceleration for fast processing RNNs is helpful for tasks where real-time performance is es-sential, such as speech recognition and stock market prediction. The nano-photonic neural network accelerator is an approach that takes advantage of the high speed, high parallelism, and low power consumption of light to achieve high performance in neural network processing. However, existing methods are inefficient for RNNs due to significant overhead caused by the absence of recursive paths and the immaturity of the model to be designed. Therefore, architectural considerations that take advantage of RNN characteristics are essential for low latency. This paper proposes a fast and low-power processing unit for RNNs that introduces activation functions and recursion processing using optical devices. We clarified the impact of noise on the proposed circuit's calculation accuracy and inference accuracy. As a result, the calculation accuracy deteriorated significantly in proportion to the increase in the number of recursions, but the effect on inference accuracy was negligible. We also compared the performance of the proposed circuit to an all-electric design and a hybrid design that processes the vector-matrix product optically and the recursion electrically. As a result, the performance of the proposed circuit improves latency by 467x, reduces power consumption by 93.0% compared with the all-electrical design, improves latency by 7.3x, and reduces power consumption by 58.6% compared with the hybrid design.

DOI： 10.1109/MCSoC57363.2022.00058

Scopus

Language：English   Publishing type：Research paper (international conference proceedings)  

Language：English   Publishing type：Research paper (international conference proceedings)  

Language：English   Publishing type：Research paper (international conference proceedings)  

Language：English   Publishing type：Research paper (other academic)  

Language：English   Publishing type：Research paper (international conference proceedings)  

DOI： 10.1145/2489068.2489071

Event date： 2024.8

Language：English   Presentation type：Poster presentation  

Event date： 2024.8

Language：English   Presentation type：Poster presentation  

Event date： 2024.8

Language：English   Presentation type：Poster presentation  

Event date： 2024.8

Language：English   Presentation type：Poster presentation  

Event date： 2024.7

Language：Japanese   Presentation type：Public lecture, seminar, tutorial, course, or other speech  

Event date： 2024.7

Language：Japanese   Presentation type：Public lecture, seminar, tutorial, course, or other speech  

Event date： 2024.7

Language：English   Presentation type：Oral presentation (invited, special)  

Event date： 2024.6

Language：Japanese  

Event date： 2024.6

Language：Japanese  

Event date： 2024.3

Language：English   Presentation type：Oral presentation (invited, special)  

Country：Japan  

Event date： 2024.3

Language：English  

Country：Japan  

Event date： 2024.3

Language：English   Presentation type：Oral presentation (invited, special)  

Event date： 2024.3

Language：Japanese   Presentation type：Poster presentation  

Event date： 2024.3

Language：Japanese   Presentation type：Oral presentation (general)  

Country：Japan  

Event date： 2024.2

Language：Japanese   Presentation type：Oral presentation (invited, special)  

Country：Japan  

Event date： 2023.12

Language：English   Presentation type：Oral presentation (invited, special)  

Country：Korea, Republic of  

Event date： 2023.11

Language：English   Presentation type：Oral presentation (general)  

Country：Japan  

Event date： 2023.10

Language：Japanese   Presentation type：Oral presentation (invited, special)  

Country：Japan  

Event date： 2023.10

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Country：Germany  

Event date： 2023.5

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Country：Italy  

Event date： 2023.4

Language：Japanese   Presentation type：Oral presentation (invited, special)  

Country：Japan  

Event date： 2023.3

Language：Japanese   Presentation type：Oral presentation (invited, special)  

Venue：芝浦工業大学   Country：Japan  

Event date： 2023.3

Language：Japanese   Presentation type：Oral presentation (invited, special)  

Venue：芝浦工業大学   Country：Japan  

Event date： 2023.3

Language：English   Presentation type：Oral presentation (general)  

Country：Japan  

Event date： 2023.3

Language：Japanese  

Venue：東京大学   Country：Japan  

Event date： 2023.3

Language：Japanese  

Venue：東京大学   Country：Japan  

Event date： 2023.3

Language：Japanese  

Venue：東京大学   Country：Japan  

Event date： 2023.3

Language：Japanese  

Venue：東京大学   Country：Japan  

Event date： 2023.3

Language：Japanese   Presentation type：Oral presentation (general)  

Country：Japan  

Event date： 2023.1

Language：Japanese   Presentation type：Oral presentation (invited, special)  

Country：Japan  

Event date： 2022.12

Language：Japanese   Presentation type：Oral presentation (general)  

Country：Japan  

Event date： 2022.11

Language：English   Presentation type：Oral presentation (general)  

Country：Japan  

Event date： 2022.11

Language：Japanese   Presentation type：Oral presentation (invited, special)  

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Language：Japanese   Presentation type：Oral presentation (general)  

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Language：English   Presentation type：Oral presentation (general)  

Country：Japan  

Event date： 2021.12

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：オンライン   Country：Japan  

Event date： 2021.10

Language：English   Presentation type：Oral presentation (general)  

Country：Japan  

Event date： 2021.10

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Country：Japan  

Event date： 2021.6

Language：Japanese   Presentation type：Oral presentation (general)  

Country：Japan  

Event date： 2021.5

Language：Japanese  

Venue：On-line   Country：Japan  

Event date： 2021.5

Language：Japanese  

Venue：On-line   Country：Japan  

Event date： 2021.5

Language：Japanese  

Venue：On-line   Country：Japan  

Event date： 2021.5

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Venue：On-line   Country：Japan  

Event date： 2021.3

Language：Japanese   Presentation type：Oral presentation (general)  

Country：Japan  

Event date： 2021.3

Language：Japanese   Presentation type：Oral presentation (general)  

Country：Japan  

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Language：Japanese   Presentation type：Oral presentation (general)  

Country：Japan  

Event date： 2021.1

Language：Japanese   Presentation type：Oral presentation (general)  

Country：Japan  

Event date： 2021.1

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Country：Japan  

Event date： 2020.10

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Event date： 2020.6

Language：Japanese   Presentation type：Symposium, workshop panel (public)  

Venue：指宿   Country：Japan  

Event date： 2020.6

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：指宿   Country：Japan  

Event date： 2020.6

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Venue：北見   Country：Japan  

Event date： 2020.6

Language：English   Presentation type：Oral presentation (general)  

Country：China  

Event date： 2020.6

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Event date： 2020.6

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Country：Japan  

Event date： 2020.6

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Country：Japan  

Event date： 2020.6

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：日吉   Country：Japan  

Event date： 2019.5

Language：Japanese  

Country：Japan  

Event date： 2019.5

Language：Japanese  

Country：Japan  

Event date： 2019.5

Language：Japanese  

Country：Japan  

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Language：Japanese  

Country：Japan  

Language：Japanese   Presentation type：Oral presentation (general)  

Type：Competition, symposium, etc. 

Type：Competition, symposium, etc. 

Type：Academic society, research group, etc. 

Type：Peer review 

Number of peer-reviewed articles in foreign language journals：3

Number of peer-reviewed articles in Japanese journals：0

Proceedings of International Conference Number of peer-reviewed papers：0

Proceedings of domestic conference Number of peer-reviewed papers：3

Type：Competition, symposium, etc. 

Type：Peer review 

Number of peer-reviewed articles in Japanese journals：0

Proceedings of International Conference Number of peer-reviewed papers：12

Proceedings of domestic conference Number of peer-reviewed papers：0

Type：Competition, symposium, etc. 

Type：Competition, symposium, etc. 

Type：Peer review 

Number of peer-reviewed articles in Japanese journals：0

Proceedings of International Conference Number of peer-reviewed papers：6

Proceedings of domestic conference Number of peer-reviewed papers：0

Type：Competition, symposium, etc. 

Type：Peer review 

Number of peer-reviewed articles in foreign language journals：1

Number of peer-reviewed articles in Japanese journals：0

Proceedings of International Conference Number of peer-reviewed papers：6

Proceedings of domestic conference Number of peer-reviewed papers：0

Type：Competition, symposium, etc. 

Type：Competition, symposium, etc. 

Type：Peer review 

Number of peer-reviewed articles in foreign language journals：2

Number of peer-reviewed articles in Japanese journals：0

Proceedings of International Conference Number of peer-reviewed papers：5

Proceedings of domestic conference Number of peer-reviewed papers：0

Type：Competition, symposium, etc.