担当区分：筆頭著者,　責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE Transactions on Circuits and Systems II: Express Briefs  

This brief proposes an on-chip bandpass filter (BPF) that achieves low loss and reduced out-of-band rejection by cascading two resonators and a low pass filtering admittance (J) inverter between them. The proposed J-inverter uses a T-network with negative mutual coupling to generate a transmission zero, and the design equations for this component are provided and verified through circuit simulations. Additionally, a resonator is proposed that utilizes a high impedance line loaded capacitor, and its poles and zeros are thoroughly investigated. Finally, the efficacy of the proposed approach is demonstrated through an on-chip prototype. The measured results show an insertion loss of 3.3 dB at 61 GHz, a 3-dB fractional bandwidth of 25%, and an extended rejection of less than 30 dB between 82 GHz and 115 GHz.

DOI： 10.1109/TCSII.2023.3283532

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE MTT-S International Microwave Symposium Digest  

For sub-terahertz band applications, two compact and low-loss on-chip substrate integrated waveguide (SIW) cavities are designed in CMOS technology. Compact size cavity is achieved by utilizing the folded ridge structure in the quarter mode SIW (QMSIW) structure which is loaded with complementary split-ring resonators (CSRRs). Two prototypes of the proposed QMSIW cavities with and without CSRR are fabricated in 1P6M CMOS technology. From the measurement, both cavities present return losses higher than 27 dB and external Q-factors higher than 140. The proposed work shows that even at such high frequencies, compact and low-loss SIWs can be fabricated in commercial CMOS technology and opens a window to utilizing such cavities for other low-loss components such as oscillators, on-chip bandpass filters and on-chip antennas for sub-terahertz band applications.

DOI： 10.1109/IMS37964.2023.10188161

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE MTT-S International Microwave Symposium Digest  

Low-loss half-mode substrate integrated waveguide (HMSIW)-based interconnects and transmission lines are designed and implemented in Complementary Metal-Oxide Semiconductor (CMOS) technology. In HMSIW interconnects, complementary split ring resonators (CSRR) whose self-resonance is much higher than the cut-off frequency of the SIW are etched on, due to which matching is improved. By controlling the parameters of the CSRRs, the losses due to microstrip to SIW transition are substantially improved, and no extra external matching circuit is required. A prototype was fabricated in 1P6M CMOS technology and tested. The measured cut-off frequency of the proposed HMSIW transmission line is 110 GHz, and the measured attenuation constant at frequencies of 175-220 GHz is less than 1.4 dB/mm. This work confirms a significant performance improvement of the CMOS interconnects in the sub-terahertz frequency band.

DOI： 10.1109/IMS37964.2023.10188034

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE Transactions on Antennas and Propagation  

A novel stacked wideband metamaterial is proposed for a robust and compact dual-band wireless power transfer (WPT) system. The proposed metamaterial employs split-ring resonator (SRR) unit cells loaded by nonuniform capacitors. First, two types of unit cells that exhibit two resonance frequencies are analyzed. The results show that it can only improve the coupling between the transmitter (Tx) and the receiver (Rx) at the single band. Then, each unit cell is sandwiched with each other, and a hybrid unit cell that indicates three resonance frequencies is finally proposed. The hybrid SRR exhibits near-zero permeability within the wide frequency range of interest. Therefore, the proposed metamaterial is effective at both bands simultaneously. The system was fabricated and tested, including a compact dual-band WPT system. The size of the Tx (Rx) and the metamaterial is $15\times15$ and $20\times20$ mm, respectively. The measured figures of merit (FOM) are 0.92 at 390 MHz and 0.85 at 770 MHz at a power transfer distance of 20 mm, which is a significant improvement over recently proposed dual-band WPT systems with metamaterials.

DOI： 10.1109/TAP.2023.3262977

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE Transactions on Circuits and Systems I: Regular Papers  

A K-band two-stage power amplifier (PA) with capacitive-feedbacked cold-phase compensator (cold-PC) linearizer and power-added-efficiency (PAE) enhancer is introduced in 180-nm CMOS technology. This cold-PC consists of two parts. First, a cold-FET analog pre-distorter (APD) with a new capacitive-feedbacked technique is proposed to improve the linear behavior of the PA by enhancing the corresponding APD's compensation slope. The proposed implementation has a reduced insertion loss and a minimal chip area overhead. Second, a low-pass two-tunable inductive and capacitive PC is proposed to solve the phase shift problem at intermediate nodes that would enhance the PAE of the stacked-transistors configuration. The implemented PA achieves, at 23.5-GHz, a maximum measured PAE of 21.2%, output power at the 1-dB compression point (OP1dB) of 13.4-dBm, and saturated output power of 15-dBm using a total chip area of 0.58 mm2. Employing the proposed cold-PC results in a decrease of the measured error vector magnitude (EVM) of the 400-MHz 5G-NR of 64-QAM modulated signal and an increase of the OP1dB and its PAE by 2.5-dB and 7%, respectively (enhancement by 78% and 72% from the original case, respectively), which, to the best of authors' knowledge, is the highest reported enhancement of the linearizers of k-band PAs.

DOI： 10.1109/TCSI.2022.3205367

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：RFIT 2022 - 2022 IEEE International Symposium on Radio-Frequency Integration Technology  

A three-Tunable low-pass π-phase compensator technique is proposed and employed in a K-band CMOS power amplifier (PA) to solve the phase shift problem at intermediate nodes of stacked transistor configurations (STCs). Also, it reduces the effects of harmonic signals that in turns, enhances the overall power added efficiency (PAE) of the PA. The PA consists of two stages i.e. driver and main stages, designed using 2-STCs in 180-nm CMOS technology. The fabricated PA achieved a power gain of 12.8 dB at 23 GHz, a maximum PAE of 18.3%, an output power of 1 dB compression point \left(\mathrm{P}{1 \mathrm{~dB}}\right) of 14.1 1 dBm, and saturated output power \left(\mathrm{P}{\text {sat }}\right) of 16.0 dBm while it consumes chip area of 0.604 mm2 including pads.

DOI： 10.1109/RFIT54256.2022.9882403

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE Microwave and Wireless Components Letters  

A two-stage 180-nm CMOS wideband (14-22 GHz) power amplifier (PA) with a superimposed staggered technique and defected-ground-structure (DGS) inductors is introduced, where a wideband peaking main stage is designed at the center frequency; then, a superimposed dual-band (SDB) driver stage is proposed to obtain the optimally flat gain response over the whole bandwidth (BW). Also, DGS inductors are used to enhance the power added efficiency (PAE) of the implemented PA by decreasing the matching circuits' insertion losses. The proposed PA achieved a power gain of 12 dB at a total chip area of 0.564 mm2. Also, at the center frequency, it achieved a saturated output power of 16.6 dBm exhibiting the smallest reported amplitude-to-phase (AM-PM) distortion (2.1°) and group delay (GD) variations (±66 ps). Finally, it gives among the highest fractional bandwidth (FBW) (44.4%) and the PAE (18.7%) so far. Also, it achieves an error vector magnitude of -25 dB at 9.3-dBm output power for a 400-MHz 5G-NR signal.

DOI： 10.1109/LMWC.2022.3189347

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：2022 Wireless Power Week, WPW 2022 - Proceedings  

A broadband rectification circuit is usually designed with complex matching circuits to achieve decade and octave impedance which result is the bulkiness of the layout and increases the losses. To mitigate these problems, an ultra-wideband high-efficiency rectification circuit without any inductors and transmission lines at the input section [1] is utilized and employed with 3-bit digitally controlled signals to vary the length of a short stub at the grounding so that reconfigurable operation of the proposed rectifier is obtained in the frequency range of 60 MHz to 3.8 GHz. The proposed compact rectification circuit offers reconfigurable operation over a wide bandwidth and is best suitable for the applications in wirelessly powered multiband and software-defined radios or other portable devices.

DOI： 10.1109/WPW54272.2022.9901332

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE MTT-S International Microwave Symposium Digest  

A novel wideband stacked metamaterial is proposed for a dual-band wireless power transfer (WPT) system. Firstly, two types of split-ring resonators (SRRs) of different self-resonance frequencies are proposed. Then we sandwiched each type of the unit cell. Consequently, the proposed metamaterial exhibits wideband near-zero characteristics on both the real part and imaginary part of the permeability. Also, compared with conventional 1-D metamaterial [2], the proposed metamaterial can significantly empower both bands simultaneously of the dual-band WPT system. An experiment shows that the proposed metamaterial of size (20 mm x 20 mm 5.468 mm) has improved the efficiencies of both bands from 18.6%, 22.9% to 51.8% and 47.8%, respectively, at a wireless power transfer distance of 20 mm.

DOI： 10.1109/IMS37962.2022.9865455

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担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE MTT-S International Microwave Symposium Digest  

Millimeter-wave miniaturized Substrate Integrated Waveguide (SIW) cavity resonator is proposed in 0.18-μm CMOS technology. Miniaturization of the SIW cavity resonator is achieved first by taking 1/16thparts of the standard SIW and employing folded ridge structure. Later this folded ridge sixteenth mode SIW cavity is inductively loaded by a complementary split-ring resonator, which provides internal matching within the cavity resonator. This improved matching enhances the return loss, the external Q-factor, and ultimately, the loaded Q-factor of the proposed cavity resonator. At 60 GHz resonance frequency, the fabricated prototype of the proposed cavity resonator presents a measured reflection coefficient of -33.42 dB, with the external Q- factor 112. Moreover, the active area of the fabricated cavity without measuring pads is only 0.019 mm2.

DOI： 10.1109/IMS37962.2022.9865522

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE MTT-S International Microwave Symposium Digest  

We propose a low magnetic loss multi-ring resonator (MRR) metamaterial. Then, we utilize this MRR metamaterial in a stacked configuration as the WPT transmitter (TX) for a miniaturized receiver (RX) embedded in biomedical tissue. A prototype is fabricated, and the measurement shows an efficiency of 51% at 50 MHz when the TX/RX separation distance is 9 mm. The TX/RX sizes are 20 mm × 20 mm and 7 mm × 7 mm, respectively. Hence, the proposed system has a figure-of- merit of 0.42, which is a significant improvement over the previously reported WPT systems. Also, the simulated specific absorption rate is within the recommended level when the input power is 21 dBm.

DOI： 10.1109/IMS37962.2022.9865438

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE Microwave and Wireless Components Letters  

This letter proposes a W -band compact cavity resonator for future applications of on-chip bandpass filters (BPFs), oscillators, phase shifters, and so on. To mitigate the leakage from the open sides of a folded ridged quarter-mode substrate integrated waveguide (SIW) cavity, shielding structures made of vias are employed. Two parallel inductive slots are etched on the top metal layer for further size reduction. Later, the one-port cavity is converted to a two-port cavity resonator and utilized in the design of W -band BPF. The proposed design is implemented in a commercial complementary metal-oxide-semiconductor (CMOS) technology, fabricated, and measured. The active size of the proposed cavity resonator is only 99 mu text{m},,boldsymbol {times },,99,,mu text{m} ( 0.054 boldsymbol {lambda }-{mathbf {g}},,{ boldsymbol {times }},,0.054{} boldsymbol {lambda }-{mathbf {g}} ), and the measured insertion loss ( vert S-{21}vert ) is 2.26 dB.

DOI： 10.1109/LMWC.2021.3122149

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Asia-Pacific Microwave Conference Proceedings, APMC  

Millimeter-wave compact, high quality (Q-) Substrate Integrated Waveguide (SIW) cavity is proposed in 0.18-µm CMOS technology. Compact size of the SIW cavity resonator is achieved first by taking 1/16th parts of the standard SIW and employing folded ridge structure. Two prototypes of the proposed cavity resonator with different feeding structures were fabricated and measured. The measurement results present a reflection coefficient lower than -22 dB and the external Q-factor greater than 60 in both cases. Experimentally, it is verified that due to the low losses associated with the top feed structure, it presents better return losses and Q-factor than the transition feed structure. Moreover, the active area of the fabricated cavity resonators without measuring pads are only 0.024 mm2, which is only 0.563% when compared to the standard SIW cavity.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：2022 52nd European Microwave Conference, EuMC 2022  

A compact size millimeter-wave on-chip defected ground structure (DGS)-based bandstop filter (BSF) is proposed and implemented in 0.18-μm CMOS technology. The proposed BSF is realized with T-shape DGS. In combination with the series resonance circuits, the proposed design realizes two transmission poles: one at either side of parallel resonance. Despite the compact size, the proposed BSF still maintains higher quality (Q) factors and group delay. The proposed BSF optimized at 52 GHz frequency is fabricated and tested. The active area of the fabricated prototype without pads is 0.0129 mm2 which is only 50% of the size of a wideband BSF recently proposed in a similar technology [8] and [16]. The measured loaded and unloaded Q-factors are 4.57 and 20.55, respectively.

DOI： 10.23919/EuMC54642.2022.9924382

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：Asia-Pacific Microwave Conference Proceedings, APMC  

An ultrawideband rectifier without an external impedance matching circuit offers many benefits, such as compact circuit size and lower losses. Generally, the rectifier is designed using the conventional voltage doubler circuit, which has varying input impedance for the operating frequency. But, to achieve the wideband rectification, the input impedance of the proposed circuit must be matched with 50 O impedance throughout the desired frequency band. For varying impedance, it is challenging to design the impedance matching network. In [11], the idea of a virtual DC battery is utilized to achieve ultra-wideband rectification without using any external matching at input section. For the further improvement of rectification efficiency, in this work, parallel diode connection is proposed instead of single diode. The proposed design achieved maximum flat conversion efficiency for energy harvesting and wireless power transfer applications.

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記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/TMTT.2018.2852661

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/TCPMT.2018.2861411

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/LMWC.2018.2801031

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/TCSII.2017.2740401

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/LMWC.2017.2750032

その他リンク： http://ieeexplore.ieee.org/document/8059822/

記述言語：英語   掲載種別：研究論文（学術雑誌）  

その他リンク： http://ieeexplore.ieee.org/document/8010799/

記述言語：英語   掲載種別：研究論文（学術雑誌）  

This paper investigates a possibility of application of a virtual inductor realized by an integrated defected ground structure (DGS) to design a front-end circuit in CMOS technology. Two types of DGS are analyzed and found that the inductance realized by a square-shaped DGS achieves smaller size and higher quality factor than an H-shaped DGS. Then, a 15-GHz low phase noise voltage-controlled oscillator (VCO) employing the proposed square-shaped DGS in 0.18-μm 1P6M CMOS technology is designed. The fabricated VCO operates from 15.2 to 16.12 GHz and consumes 5-mW power. The measured phase noise is -132.08 dBc/Hz at 10-MHz offset frequency, and this results in the figure of merit (FoM) and FoM taking account of the area to be 189.1 and 199.9 dB, respectively.

DOI： 10.1109/JEDS.2017.2728686

その他リンク： http://ieeexplore.ieee.org/document/7984797/

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： http://dx.doi.org/10.1109/TMTT.2016.2618919

その他リンク： http://dx.doi.org/10.1109/TMTT.2016.2618919

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： http://doi.org/10.1587/elex.13.20160591

その他リンク： http://doi.org/10.1587/elex.13.20160591

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/LMWC.2016.2601300

その他リンク： http://dx.doi.org/10.1109/LMWC.2016.2601300

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/LMWC.2016.2597219

その他リンク： http://ieeexplore.ieee.org/document/7542143/?arnumber=7542143

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1002/mop.29650

その他リンク： http://onlinelibrary.wiley.com/doi/10.1002/mop.29650/full

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1587/elex.13.20151115

その他リンク： https://www.jstage.jst.go.jp/article/elex/advpub/0/advpub_13.20151115/_article

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1049/el.2015.4465

その他リンク： http://digital-library.theiet.org/content/journals/10.1049/el.2015.4465

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：International Journal of Electronics  

In this article, a self-bias MOSFET-based dual-resistive feedback low-noise amplifier (LNA) is investigated. A detailed mathematical analysis of the addressed amplifier has been carried out using the return ratio-based feedback analysis technique. Furthermore, the LNAs have been simulated via Cadence using the TSMC 65 nm PDK. Two (Formula presented.) strategies are described to handle the performance trade-offs for enhancing gain, noise figure (NF) and power consumption. The two strategies are conceptually similar to one another, with the selection of the transconductance efficiency being the only difference. While the first technique uses a transconductance efficiency to achieve the lowest power consumption while keeping an acceptable NF, the second strategy uses a particular transconductance efficiency for flawless noise cancelling without consideration for reduced power consumption. According to simulation results, the first recommended LNA has a voltage gain of 12 dB over a 3 dB bandwidth of 0.5–10 GHz, a minimal NF of 1.7 dB @ 7.014 GHz, a maximum NF of 1.932 dB @ 0.5 GHz, consumes 12.42 mW from a low supply voltage of 1.2 V and achieved a third-order intercept of −2.34 dBm @ 1 GHz. The simulation results of the second recommended LNA also show that it can operate with a low supply voltage of 1.2 V and still achieve a minimum NF of 0.978 dB @ 2.729 GHz, a maximum NF of 1.048 dB @ 6 GHz, (Formula presented.) of 1.34 dBm and a voltage gain of 13 dB over a 3 dB bandwidth of 0.5–6 GHz with a consuming power of 25 mW.

DOI： 10.1080/00207217.2024.2384001

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出版者・発行元：IEEE MTT-S International Microwave Symposium Digest  

This paper proposes a metamaterial-inspired absorber designed to enhance isolation in a simultaneous wireless information and power transfer (SWIPT) system through biological tissue. The study delves into the metamaterial perspective, focusing on the characteristics of split-ring resonators (SRRs) within the proposed absorber unit cells. The absorber exhibits a significant real part near -1 and an imaginary part close to 0 in permeability. A 10-mm-thick human body equivalent phantom is used for the SWIPT system's evaluation. Experimental results indicate that embedding this absorber between power and signal ports in both Tx and Rx of a SWIPT system results in a 3 dB improvement in isolation performance. Concurrently, with the assistance of the proposed absorber, the datarate improves by 3.6 Mb/s, allowing signals to be transmitted with 5 dBm weaker power than the original system.

DOI： 10.1109/IMS40175.2024.10600186

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE MTT-S International Microwave Symposium Digest  

A method for calculating transition loss in long lowloss substrate integrated waveguide (SIW)-based transmission lines fabricated using commercial complementary metal-oxidesemiconductor (CMOS) technology is presented. To quantify the accurate transition loss, the proposed approach employed twostep de-embedding technique besides normal measurement setup calibration using impedance standard substrate (ISS) at two distinct reference points: the first mitigates measuring pad effects, and the second removes both pads and transition structures. By using the attenuation constants calculated from these reference planes, the intrinsic transition loss is estimated. From the experiment, a low transition loss is observed in the proposed SIW design, which varies between 0.2 dB and 1.3 dB over a wide measurement bandwidth of 120 to 220 GHz. The experimental results underscore the efficacy of the proposed method and suggest the potential for consistent performance above the current measurement threshold of 220 GHz, which could be pivotal for terahertz (THz) applications.

DOI： 10.1109/IMS40175.2024.10600291

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：2023 IEEE Wireless Power Technology Conference and Expo, WPTCE 2023 - Proceedings  

The frequency switching dual power band rectifier is proposed to achieve both low-power and high-power applications from a single circuit. Two different operating frequencies f1 = 900 MHz and f2 = 2.4 GHz are selected for low-power and high-power applications, respectively. The proposed rectifier fulfills stable operation at two levels of input power by making frequency switching. The Schottky diodes HSMS 2850 and HSMS 2860 are selected for f1 and f2, respectively, based on their performance with respect to the input power. Instead of conventional lumped inductors, defected ground structure (DGS)-based inductors are employed in matching circuits. For maximum RF-to-dc conversion efficiency in both low and high-power conditions, two different optimal loads are required, which is achieved from the load-modulation technique by using Bipolar Junction Transistor (BJT). The measurement result of the proposed rectifier shows more than 50% conversion efficiency for the power range -18 dB to 2 dBm and 8 dBm to 20 dBm with circuit size of 35 mm × 30 mm.

DOI： 10.1109/WPTCE56855.2023.10216256

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担当区分：筆頭著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：2023 IEEE Wireless Power Technology Conference and Expo, WPTCE 2023 - Proceedings  

In this work, a new clock and data recovery (CDR) scheme is proposed for amplitude shift keying (ASK) with pulse width modulation (PWM) encoding. Such a technique can fully recover the clock as well as the encoded data without the need for any comparator. The clock is recovered by passing the ASK-PWM encoded data to the frequency divider and frequency multiplier. Then, the data sampler can recover the data by sampling the ASK-PWM modulated data using a delayed version of the recovered clock with no additional processing. This technique is intended for a data transfer system over an inductively coupled wireless power transfer system (WPT) system for biomedical implants where the data will modulate the power carrier without the need for a dedicated data channel. A prototype example implementation of the CDR scheme on a 180 nm Complementary-Metal-Oxide-Semiconductor (CMOS) technology with a data rate of 2 Mbps is provided as a proof-of-concept. This CDR prototype has an area of 8000 μm2 and consumes a power of 129 microwatts from a 1.4 Voltage dc supply.

DOI： 10.1109/WPTCE56855.2023.10215978

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：2023 35th General Assembly and Scientific Symposium of the International Union of Radio Science, URSI GASS 2023  

Sub-terahertz (sub-THz) band low-loss on-chip substrate integrated waveguide (SIW)-based transmission line interconnects, and cavities are presented and implemented in complementary metal oxide semiconductor (CMOS) technology. SIW cavities are designed with standard and half-mode (HM) SIW structures. Similarly, low-loss SIW interconnect design is implemented by introducing complementary split ring resonators (CSRR) in HMSIW interconnects. The prototypes of the proposed SIW cavities and the interconnects structures are fabricated and experimented in 1P6M CMOS at 200 GHz band. The measurement results of designed SIW cavities present return loss better than 25 dB and the external quality (Q-) factor better than 130 from both designs. Similarly, the HMSIW interconnect presents a measured attenuation constant of less than 1.6 dB/mm at the frequency range of 130-220 GHz band. This works shows that on-chip low-loss SIW-based designs can be implemented in frequency bands like sub-THz and above and can find application for designing transmission lines, filters, oscillators, antennas, etc., for THz applications.

DOI： 10.23919/URSIGASS57860.2023.10265470

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：2022 Wireless Power Week, WPW 2022 - Proceedings  

In this paper, we propose a multiple-input single-output (MISO) wireless power transfer (WPT) system using a stacked meta-surface structure for achieving a high transmission distance. We started by studying two coupled DGS resonators one is a transmitter and the other is a receiver, each resonator is excited by a microstrip line to transfer power at a frequency of 670 MHz. In order to improve the power transfer efficiency, five extra DGS transmitters are employed. Therefore, the proposed multiple-input transmitter is composed of six DGS resonators printed on one layer of a single substrate. On the other side, the receiver is a single DGS resonator. The size of the transmitter and receiver are 46.4mm × 30.7 mm and 15mm × 15 mm, respectively. The stacked meta-surface is in three layers. And the size of it is 25.4mm × 25 mm. In measurement, the WPT efficiency of the MISO system with meta-surface is a maximum of 31.1% higher than that of the MISO system without meta-surface.

DOI： 10.1109/WPW54272.2022.9853985

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記述言語：英語   掲載種別：研究論文（学術雑誌）  

Defected Ground Structure (DGS) based on-chip bandstop filter (BSF) design is proposed for millimeter-wave applications. In the proposed structure, a capacitively loaded T-shape resonator is embedded in the original DGS resonator, which forms two high quality ( ${Q}$ -) factor small loop resonators. Moreover, this structure, in combination with the feedline and series capacitor, independently realizes the position of two transmission poles: one at each side of the parallel resonance without increasing the layout size. The proposed BSF presents a sharp scattering (S-) parameter response due to the appearance of two transmission poles. As a result, the loaded ${Q}$ -factor and negative group delay of the BSF are improved. The prototype of the proposed BSF is fabricated in 0.18- $mu ext{m}$ Complementary Metal-Oxide-Semiconductor (CMOS) process and measured. The measurement result shows a return loss of 1.78 dB at 53.2 GHz center stopband frequency with the negative group delay of 161 pS. The measurement results also agree well with the electromagnetic simulation results. Without pads, the active area of the prototyped BSF is only 0.024 mm2.

DOI： 10.1109/TCSII.2022.3158995

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Defected Ground Structure (DGS) based on-chip bandstop filter (BSF) design is proposed for millimeter-wave applications. In the proposed structure, a capacitively loaded T-shape resonator is embedded in the original DGS resonator, which forms two high quality ( Q -) factor small loop resonators. Moreover, this structure, in combination with the feedline and series capacitor, independently realizes the position of two transmission poles: one at each side of the parallel resonance without increasing the layout size. The proposed BSF presents a sharp scattering (S-) parameter response due to the appearance of two transmission poles. As a result, the loaded Q -factor and negative group delay of the BSF are improved. The prototype of the proposed BSF is fabricated in 0.18- μm Complementary Metal-Oxide-Semiconductor (CMOS) process and measured. The measurement result shows a return loss of 1.78 dB at 53.2 GHz center stopband frequency with the negative group delay of 161 pS. The measurement results also agree well with the electromagnetic simulation results. Without pads, the active area of the prototyped BSF is only 0.024 mm2.

DOI： 10.1109/TCSII.2022.3158995

その他リンク： https://ieeexplore.ieee.org/document/9733395

担当区分：最終著者   記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE Microwave and Wireless Components Letters  

This letter presents a $V$ -band low phase noise voltage-controlled oscillator (VCO) design using a novel integrated two-branches defected ground structure (DGS) resonator in 0.18- $\mu \text{m}$ complementary metal-oxide-semiconductor (CMOS) technology. The proposed DGS resonator is realized in the top metal layer (M6) which has not only a higher quality factor than its predecessors but is also effective to reduce the length of interconnects. The measured carrier frequency and phase noise are 49 GHz and -122.05 dBc/Hz (-102.58 dBc/Hz) at 10-MHz (1-MHz) offset frequencies, respectively. The VCO core consumes 5.5 mW of dc power from the dc supply, which results in a figure of merit (FoM) of -189 dBc/Hz. The proposed VCO using the two-branches DGS resonator may give an alternative low-cost solution for designing a high-performance VCO or frequency synthesizer at $V$ -band and beyond.

DOI： 10.1109/LMWC.2022.3171405

Scopus

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記述言語：英語   掲載種別：研究論文（学術雑誌）  

This letter presents a V-band low phase noise voltage-controlled oscillator (VCO) design using a novel integrated two-branches defected ground structure (DGS) resonator in 0.18-μm complementary metal-oxide-semiconductor (CMOS) technology. The proposed DGS resonator is realized in the top metal layer (M6) which has not only a higher quality factor than its predecessors but is also effective to reduce the length of interconnects. The measured carrier frequency and phase noise are 49 GHz and -122.05 dBc/Hz (-102.58 dBc/Hz) at 10-MHz (1-MHz) offset frequencies, respectively. The VCO core consumes 5.5 mW of dc power from the dc supply, which results in a figure of merit (FoM) of -189 dBc/Hz. The proposed VCO using the two-branches DGS resonator may give an alternative low-cost solution for designing a high-performance VCO or frequency synthesizer at V-band and beyond.

DOI： https://doi.org/10.1109/LMWC.2022.3171405

その他リンク： https://ieeexplore.ieee.org/document/9773303

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/TCSII.2021.3123954

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/TCSII.2021.3123954

その他リンク： https://ieeexplore.ieee.org/document/9594096

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/TCSII.2021.3123655

その他リンク： https://ieeexplore.ieee.org/document/9592631

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/TCSII.2021.3123655

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Asia-Pacific Microwave Conference Proceedings, APMC  

In this paper, effectiveness of multi-resonance around the parallel resonance of an LC-tank circuit on the reduction of K-band Voltage-Controlled Oscillators (VCOs) phase noise is proposed. The skirt characteristics of the Scattering (|S|) parameters of the resonators is sharpened by introducing transmission poles beside the parallel resonance of the LC-tank circuit. In return, an enhanced the resonator loaded quality (Q) factor without compromising the unloaded Q-factor is obtained. Three designs are realized, verified and compared to the others in a differential VCO topology and the phase noise reduction in post-layout simulations is confirmed. Finally, two chips are fabricated in 0.18-µm CMOS technology and measured.

Scopus

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1038/s41598-021-99405-7

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1038/s41598-021-01677-6

その他リンク： https://www.nature.com/articles/s41598-021-01677-6

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/IMS19712.2021.9574938

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/WPTC51349.2021.9458177

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/LMWC.2021.3064602

記述言語：英語   掲載種別：研究論文（学術雑誌）  

A voltage-controlled oscillator (VCO) is usually designed by maximizing the quality (Q-) factor of the LC-tank resonator to realize a low phase noise. For the same frequency, the ratio of C/L affects the loaded Q-factor (QL) and then phase noise of the VCO. This affect has not been considered so far in the design of VCO because the conventional on-chip spiral inductor cannot be optimized for C/L ratio. This brief first investigates the effects of C/L ratio on the phase noise, and a design methodology for optimized C/L ratio using defected ground structure (DGS) resonator is presented. Then, the resonators were further evaluated based on LgL-product simulation for a fixed Ibias. Employing the proposed resonator, a very low phase noise KUband VCO is designed and implemented in 0.18-lm CMOS technology. The measurement result shows that the proposed VCO has a phase noise of -110.77 dBc/Hz at 1 MHz offset of 17.5 GHz carrier frequency and a frequency tuning range of 8.7%. The VCO consumes 2.3 mW power, which results in a figure of merit (FoM) of -191.95 dB.

DOI： 10.1109/TCSII.2021.3079309

その他リンク： https://ieeexplore.ieee.org/document/9428594

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1038/s41598-021-84333-3

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/TCSII.2020.3016385

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.23919/EuMC48046.2021.9338129

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/LMWC.2020.3016136

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/IMS30576.2020.9223866

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/LMWC.2020.3004753

記述言語：その他   掲載種別：研究論文（学術雑誌）  

This work proposes a new theory to reduce the phase noise of K-band Voltage-Controlled Oscillators (VCOs) in Complementary Metal Oxide Semiconductor (CMOS) process by introducing one or more transmission poles around the parallel resonance of an LC-tank circuit. Introduction of transmission poles beside the parallel resonance of the LC-tank circuit sharpens the skirt characteristics of the Scattering (S) parameters of the resonators. In return, sharp S-parameters slope enhances the resonator loaded quality (Q) factor without compromising the unloaded Q-factor. In addition, the transmission pole can be realized near the second harmonic of the oscillation. This allocation of the transmission pole leads to the cancellation of this second harmonic and a further reduction of the phase noise. The proposed theory is verified by three different designs based on defected ground structure (DGS) resonators. These designs realized a low-band transmission pole before the parallel resonance, a high-band transmission pole after the parallel resonance, and dual-band transmission poles around the parallel resonance. First, each design is verified and compared to the others using circuit and electromagnetic simulations to establish the Q-factor improvement. Then, each of the resonators is utilized in a differential VCO topology and the phase noise reduction in post-layout simulations is confirmed. Finally, two chips are fabricated in 0.18-μ m CMOS technology and measured. The measurement results are in good agreement with the simulations, which confirm our claim about the proposed theory.

DOI： 10.1109/TCSI.2020.2965007

記述言語：その他   掲載種別：研究論文（学術雑誌）  

This letter presents the improvement of the phase noise (PN) of a voltage-controlled oscillator (VCO) by using a defected ground structure (DGS) resonator with a high-band transmission pole. The proposed DGS resonator has two loops in a coplanar stripline topology. The outer loop is loaded by a series capacitance, which produces the high-band transmission pole. The overall combination has a parallel capacitor to generate the necessary parallel resonance for the VCO operation. This proposed DGS resonator has a sharper impedance and frequency response slope, which results in an improved quality factor. In return, utilization of this DGS resonator into a KU-Band VCO reduces its PN. The prototyped VCO in 0.18-µm CMOS oscillates at 15.52 GHz and shows a PN of −111.27 and −134.07 dBc/Hz at 1- and 10-MHz offset, respectively, while consuming 3.3-mW power. The VCO has a frequency tuning range of 9.5%, which results in a figure of merit (FoM) of −192.7 dB.

DOI： 10.1109/LMWC.2019.2950525

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

In this paper, to characterize the effect of interconnects inductance on VCO's phase noise precisely, two K-band VCO circuits that employ DGS as an inductor are designed and analyzed. It's shown that not only the quality factor of the inductor in resonator has a significant effect on VCO's phase noise, the parasitic inductance of the interconnecting transmission lines will also inflect the phase noise severely. To get the Quantitative analysis, a K-band (25 GHz) VCO is implemented in the 0.18-mu mathrm{m} 1P6M CMOS process and measured.

DOI： 10.1109/APMC46564.2019.9038781

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/LMWC.2019.2935621

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/TCSII.2018.2883671

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/LMWC.2019.2917747

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/mwsym.2019.8700821

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/mwsym.2019.8700853

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/WISNET.2019.8711815

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

This work proposes a new theory to improve the phase noise of a Voltage-Controlled Oscillator (VCO) by introducing dual series resonances around the parallel resonance of an LC-tank circuit. The overall circuit has an improved susceptance slope parameters, which results in the improvement of quality (Q-) factor. Later, its effectiveness is demonstrated to design a low phase noise K-band VCO. The proposed characteristics are realized by a compact defected ground structure (DGS) resonator in a coplanar strip line (CPS) topology. The DGS is loaded by a capacitor, and this combination introduces the parallel resonance. The CPS signal line is implemented with high characteristic impedance to introduce a series inductance. Then, a gap in the CPS is introduced with a loading series capacitance forming a series resonance circuit with the CPS inductance. The overall combination of the series and parallel resonance circuits allowed the targeted two series resonances before and after the parallel resonance. The design is implemented in 0.18-μm CMOS technology, and the post-layout simulation shows that the VCO has a phase noise of -112.31 dBc/Hz @1 MHz offset of 22.07 GHz oscillation, which is 2.3 dB improvement compared to single series resonance VCO. The VCO consumes 4 mW power resulting in a figure of merit (FoM) of -193.2 dB.

DOI： 10.1109/ISCAS.2019.8702264

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/WPT.2018.8639281

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/WPT.2018.8639134

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

A novel technique for a low phase noise and compact K-band Voltage-Controlled Oscillator (VCO) using multi-layers DGS resonator is proposed. The proposed DGS resonator realizes an additional series resonance at the higher side of parallel resonance frequency, and this results in improving both the active and loaded quality factor of the resonator. The proposed resonator has active quality factor of 130 and a compact size of 0.009 mm 2 (0.000459 ? 2 ). Using the proposed DGS resonator in the VCO causes 9 dB improvement in the phase noise compared the VCO implemented using the conventional LC resonator. Two VCOs are designed using the method to illustrate the effect of the series resonance. The first VCO is designed three layers DGS resonator and the other VCO using two layers DGS resonator. The designs are implemented in 0.18 µm CMOS technology and consume 2.9 mW power, and from the post layout results, the first proposed VCO oscillates from 19.6 to 21.3 GHz (8.3 %) and has a phase noise of -113.2 dBc/Hz at 1 MHz offset frequency, and this results in the figure of merit (FoM) and FoM taking account of the tuning range to be -194.4 and -192.7 dB, respectively. The second VCO has a tuning range of 6.1 % and phase noise of -114 dBc/Hz @ 1 MHz offset at 19.6 GHz oscillation.

DOI： 10.1109/MWSCAS.2018.8623874

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.2528/pierm18101608

記述言語：その他   掲載種別：研究論文（学術雑誌）  

This paper presents a new type of a low-loss miniaturized coplanar-waveguide (CPW) transmission line (TL) by employing distributed loading, capacitors and inductors, in 0.18-μm complementary metal-oxide-semiconductor (CMOS) technology. The capacitors are realized by vertical parallel plates made of vias, and a group of open stubs inserted to the signal line, whereas the inductors are realized by high impedance lines. Then, the proposed CPW-TL is employed to design a miniaturized millimeter wave ultra-wideband low-loss Wilkinson power divider/combiner (WPD/C). The proposed distributed loading results in reducing each WPD/C arm length by more than 50% without changing its characteristic impedance and insertion loss (IL). The design is fabricated in 0.18-μm CMOS technology and tested. The measured results show a wideband performance from dc to 67 GHz with 1-dB IL and isolation greater than 15 dB from 36 to 67 GHz. In addition, the fabricated WPD/C achieves an excellent amplitude imbalance and phase imbalance of less than 0.16 dB and 0.45°, respectively. The core chip size is 336 × 165 μm 2 , which is almost 32.8% compact compared to the recently proposed WPD in the same technology.

DOI： 10.1109/TMTT.2018.2873381

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/RFIT.2018.8524088

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/TMTT.2018.2852661

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/TCPMT.2018.2861411

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/IMaRC.2017.8449719

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/ACCESS.2018.2866457

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/IMBIOC.2018.8428951

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ISCAS.2018.8351670

記述言語：その他   掲載種別：研究論文（学術雑誌）  

A novel 22-GHz-band oscillator using an integrated defected ground structure (DGS) resonator is presented for quasi-millimeter waveband applications. The DGS is etched on the first metal layer (M1) below a 50-Ω microstrip line on the top metal layer (M6) of 0.18-μm one-poly six-metal (1P6M) complementary metal-oxide-semiconductor (CMOS) technology. The proposed oscillator is fabricated using 0.18-μm CMOS technology, and the measured carrier frequency and phase noise are 22.88 GHz and-129.21 dBc/Hz (-108.05 dBc/Hz) at 10-MHz (1 MHz) offset frequency, respectively. The power dissipation is 6 mW that results in a figure of merit to be-188.8 dB. As the DGS resonator could be designed at any high frequency, it may give an alternative design approach of high performance voltage controlled oscillator and frequency synthesizers at K-band and beyond, thus alleviates the problem of self-resonance that a spiral inductor usually encounters at higher frequency.

DOI： 10.1109/LMWC.2018.2801031

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/RWS.2018.8304959

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/TCSII.2017.2740401

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

In the paper, we propose a novel voltage-controlled oscillator (VCO) employing defected ground structure (DGS) band stop filter (BSF). The VCO operates from 15.24 GHz to 15.86 GHz. A square shaped DGS etched at the lowest metal layer (M1) below 50-Ohm microstrip line on the top metal layer (M6) of 0.18 μm 1P6M CMOS process. The proposed square-shaped DGS resonator achieves smaller size and higher quality factor than those of a conventional spiral inductor resonator at Ku band frequency. The power dissipation of the VCO is 4 mW. The measured carrier frequency and phase noise are 15.76 GHz and-127.57 dBc/Hz (104.25 dBc/Hz) at 10 MHz (1 MHz) offset frequency, respectively. The measured figure of merit (FoM) is 182.9 dB. The fabricated chip core VCO size is only 0.084mm2 which increases figure of merit (FoMa) to 194 dB.

DOI： 10.23919/EuMC.2017.8230959

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/LMWC.2017.2750032

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/JEDS.2017.2728686

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/LMWC.2017.2734771

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/APMC.2017.8251489

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/APMC.2017.8251624

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/APMC.2016.7931382

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/RWS.2017.7885983

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/TMTT.2016.2618919

記述言語：その他   掲載種別：研究論文（学術雑誌）  

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/APCCAS.2016.7803949

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/LMWC.2016.2601300

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1587/elex.13.20160591

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/LMWC.2016.2597219

記述言語：英語   掲載種別：研究論文（学術雑誌）  

その他リンク： http://jairo.nii.ac.jp/0001/00389403

記述言語：その他   掲載種別：研究論文（学術雑誌）  

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/WAMICON.2016.7483829

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/WAMICON.2016.7483819

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/EuCAP.2016.7481426

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1049/el.2015.4465

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1002/mop.29650

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

A design of an improved open loop resonator on-chip bandpass filter for 60 GHz millimeter-wave applications using 0.18 μm CMOS technology is presented. The proposed on-chip BPF employs H-shaped parasitic structure inserted between two open loop coupled resonator. The adoption of a two open loop coupled resonators BPF and the utilization of two transmissions zero located at 48 and 80 GHz permit a compact size and high selectivity of the BPF. In addition, the parasitic H-shaped structure increases the capacitance between the two resonators, which enables a further reduction of the physical length of the filter and enhances the coupling between the resonators which improve the filter insertion loss. The proposed BPF has a center frequency of 60 GHz, an insertion loss of-2 dB, a 3dB band width of 13 GHz, and a core size 160 × 480 μm2 with total chip size 680 × 280 μm2 (including bonding pads).

DOI： 10.1109/ICM.2015.7438049

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ICM.2015.7438050

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ICECS.2015.7440292

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1587/elex.13.20151115

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/APCAP.2015.7374402

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/SIRF.2015.7119885

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/EuMC.2014.6986380

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/USNC-URSI.2014.6955519

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/MWSYM.2013.6697475

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/EuCAP.2012.6206127

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/JEC-ECC.2012.6186968

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/MECAP.2010.5724184

開催年月日： 2015年12月

記述言語：英語   会議種別：口頭発表（一般）  

国名：モロッコ王国  

その他リンク： http://ieeexplore.ieee.org/document/7438050/

開催年月日： 2015年12月

記述言語：英語   会議種別：シンポジウム・ワークショップ パネル（公募）  

国名：エジプト・アラブ共和国  

その他リンク： http://ieeexplore.ieee.org/document/7440292/

開催年月日： 2015年6月 - 2015年7月

記述言語：英語   会議種別：口頭発表（一般）  

国名：インドネシア共和国  

その他リンク： http://ieeexplore.ieee.org/document/7374402/

開催年月日： 2015年1月

記述言語：英語  

国名：アメリカ合衆国  

その他リンク： http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=7119885&abstractAccess=no&userType=inst

開催年月日： 2014年10月

記述言語：英語   会議種別：口頭発表（一般）  

国名：イタリア共和国  

その他リンク： http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6986380&abstractAccess=no&userType=inst

開催年月日： 2014年7月

記述言語：英語   会議種別：口頭発表（一般）  

国名：アメリカ合衆国  

その他リンク： http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6955519&abstractAccess=no&userType=inst

開催年月日： 2013年6月

記述言語：英語   会議種別：口頭発表（一般）  

国名：アメリカ合衆国  

その他リンク： http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6697475

開催年月日： 2012年3月

記述言語：英語   会議種別：口頭発表（一般）  

国名：チェコ共和国  

その他リンク： http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=6206127&abstractAccess=no&userType=inst

開催年月日： 2012年3月

記述言語：英語   会議種別：口頭発表（一般）  

国名：エジプト・アラブ共和国  

その他リンク： http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=6186968&abstractAccess=no&userType=inst

開催年月日： 2010年10月

記述言語：英語   会議種別：口頭発表（一般）  

国名：エジプト・アラブ共和国  

その他リンク： http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5724184&abstractAccess=no&userType=inst

開催年月日： 2022年12月

記述言語：英語   会議種別：口頭発表（招待・特別）  

国名：エジプト・アラブ共和国  

開催年月日： 2022年4月

記述言語：英語   会議種別：口頭発表（一般）  

開催地：London   国名：グレートブリテン・北アイルランド連合王国(英国)  

Recently, defected ground structure (DGS) resonators have been employed to design a low phase noise Voltage-Controlled Oscillator (VCO) for quasi-millimeter wave applications [10]. A few advantages of such VCOs are that a DGS resonator has a higher Q-factor than an on-chip spiral inductor, and it has a higher self-resonance frequency compared to a conventional LC resonator so that a stable inductance value with respect to the frequency can be realized. However, one of its drawbacks is that the tuning range of DGS-based VCOs is limited. In this paper, a method to realize a wide tuning range of DGS-based VCOs has been proposed using two interconnected DGS resonators. As a result, the designed VCO implemented in 0.18-µm 1P6M CMOS technology achieves a 19.8% tuning range with the best phase noise performance of -109.43dBc/Hz at 1-MHz offset frequency in simulations. The experiment result shows that the fabricated VCO has a phase noise of -108.41dBc/Hz at 1-MHz offset frequency with the carrier frequency of 18.51GHz, which exhibits good agreement with the simulation.

その他リンク： https://ieeexplore.ieee.org/document/9783689

開催年月日： 2022年4月

記述言語：英語   会議種別：口頭発表（一般）  

国名：グレートブリテン・北アイルランド連合王国(英国)  

その他リンク： https://ieeexplore.ieee.org/document/9784336

開催年月日： 2022年4月

記述言語：英語   会議種別：口頭発表（一般）  

国名：グレートブリテン・北アイルランド連合王国(英国)  

その他リンク： https://ieeexplore.ieee.org/document/9784207

開催年月日： 2022年4月

記述言語：英語   会議種別：口頭発表（一般）  

国名：グレートブリテン・北アイルランド連合王国(英国)  

その他リンク： https://ieeexplore.ieee.org/document/9784281

開催年月日： 2022年4月

記述言語：英語   会議種別：口頭発表（一般）  

開催地：London   国名：グレートブリテン・北アイルランド連合王国(英国)  

This paper proposes a compact, high quality (Q-) factor cavity in commercial CMOS technology for terahertz band applications. The proposed cavity consists of a folded quarter-mode substrate integrated waveguide (QMSIW) topology. It also outlines some guidelines for creating layouts with specific foundries, particularly for building vertical walls using an array of vias. The cavity was implemented in 0.18 µm CMOS technology and measurements were taken. The measurements showed that the resonant frequency and reflection coefficient were 96.9 GHz and -30.14 dB, respectively, in good agreement with the simulation results. The area of the proposed cavity was 0.0506 mm2 without measurement pads, which is only 2.4% and 8.9% when compared to the standard full-mode SIW cavity and the recently proposed 87 GHz.

その他リンク： https://ieeexplore.ieee.org/document/9784193

開催年月日： 2021年6月

記述言語：英語   会議種別：口頭発表（一般）  

国名：アメリカ合衆国  

その他リンク： https://ieeexplore.ieee.org/document/9574938

開催年月日： 2021年6月

記述言語：英語   会議種別：口頭発表（一般）  

国名：アメリカ合衆国  

その他リンク： https://ieeexplore.ieee.org/document/9458177

開催年月日： 2021年1月

記述言語：英語   会議種別：口頭発表（一般）  

国名：オランダ王国  

その他リンク： https://ieeexplore.ieee.org/document/9338129

開催年月日： 2017年1月

記述言語：英語   会議種別：口頭発表（一般）  

国名：アメリカ合衆国  

その他リンク： http://ieeexplore.ieee.org/document/7885983/

開催年月日： 2016年10月

記述言語：英語   会議種別：口頭発表（一般）  

国名：大韓民国  

その他リンク： http://ieeexplore.ieee.org/document/7803949/