Language：Others   Publishing type：Research paper (scientific journal)   Publisher：Elsevier BV  

This paper reports the mechanism of gate voltage spike in the turn-off operation by a digital gate control. In the previous work, it was clarified that the gate voltage spike Vg_spike was generated by parasitic inductance and a large gate current change due to the digital gate control. However, the main cause of resonance leading to Vg_spike generation has never been clear. Three types of IGBT modules, which have the same gate inductance and different input capacitance, were tested under three-step digital gate control. It was found that the Vg_spike was independent of input capacitance in IGBT. As for the stray capacitance in the digital gate driver, external capacitors Cex were connected in parallel with the gate driver, and the Vg_spike decreased with increasing Cex. Furthermore, the second vector of the digital control, which was applied for suppressing the overshoot in collector-emitter voltage by a small value, needed to be set as a large value to suppress the Vg_spike. From these results, output impedance of gate driver is a key factor for the Vg_spike, and the second vector must be optimized for not only the collector voltage overshoot but also Vg_spike suppression for safety operation.

DOI： 10.1016/j.pedc.2023.100054

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Language：Japanese   Publisher：The Institute of Electrical Engineers of Japan  

<p>Surge voltage at IGBT turn-off switching was analyzed with dependence on cell design parameters. Although drift layer thinning is effective to improve trade-off characteristics between turn-off loss <i>E_off</i> and on-state voltage <i>V_on</i>, voltage surge is induced due to quick expanding depletion layer. Therefore, the surge voltage <i>V_surge</i> has also trade-off relationship with the <i>V_on</i> at the same <i>E_off</i> condition. The origin of voltage surge was analyzed using TCAD simulation, and total amount of remained hole in the drift layer during turn-off switching is a key factor for the <i>V_surge</i>. Narrow mesa structure and thick buffer layer are effective for improvement of trade-off characteristics between <i>V_surge</i> and <i>V_on</i>.</p>

DOI： 10.1541/ieejeiss.144.198

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CiNii Research

Publisher：Japanese Journal of Applied Physics  

In silicon insulated gate bipolar transistors, the trench gate structure is used to achieve smaller cell size and lower ON resistance, and thereby reduces energy loss. However, the thermal process can cause large stress near the trench and sometimes degrades device performance. This study proposed a three-dimensional model of a silicon chip with trench structures to analyze the stress distribution induced by thermal process around the trench, the scribe line, and the bottom surface of the chip. The calculated stress is in good agreement with measurement by Raman spectroscopy. The mesa top has much higher stress than the scribe line and the bottom surface. The stress depends on oxide thickness and the size scaling may reduce the stress.

DOI： 10.35848/1347-4065/ad1e00

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Publisher：Japanese Journal of Applied Physics  

The demand for grown-in defect-free wafers for high-performance silicon semiconductor devices is significantly increasing. To obtain defect-free crystals, the ratio v/G of the growth rate v to the temperature gradient G in the growth direction near the solid-liquid interface during crystal growth must be kept at a critical value ξ cri . Furthermore, ξ cri depends on the interface shape, which is interpreted as the change in the diffusion direction of point defects due to the change in the interface shape. In this study, we present a new interpretation based on simulations and experiments, in which ξ cri changes due to the effect of the diffusion direction of point defects when the solid-liquid interface shape is convex, as in the conventional interpretation, as well as the effect of thermal stress when it is concave.

DOI： 10.35848/1347-4065/ad2d79

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Publisher：Japanese Journal of Applied Physics  

Surge voltage at insulated gate bipolar transistor turn-off switching was analyzed with dependence on cell design parameters. Although drift layer thinning is effective in improving trade-off characteristics between turn-off loss E off and on-state voltage V on, voltage surge is induced due to the quickly expanding depletion layer. Therefore, the surge voltage V surge has also a trade-off relationship with V on at the same E off condition. The origin of the voltage surge was analyzed using TCAD simulation, and the total amount of remaining holes in the drift layer during turn-off switching is a key factor for the V surge. A narrow mesa structure and thick buffer layer are effective for the improvement of trade-off characteristics between V surge and V on. However, the optimum buffer layer thickness depends on the voltage-class due to the speed for punch through.

DOI： 10.35848/1347-4065/ad106d

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Publisher：IEEE Electron Devices Technology and Manufacturing Conference: Strengthening the Globalization in Semiconductors, EDTM 2024  

SiC has high expectations as a next-generation power device material and device because of its excellent semiconductor properties. This report introduces power electronics application fields in which SiC is expected to be used. SiC wafer technology, which is the starting point of the supply chain for realizing this goal, is also introduced.

DOI： 10.1109/EDTM58488.2024.10512311

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Publishing type：Research paper (scientific journal)   Publisher：Institute of Electrical and Electronics Engineers (IEEE)  

This paper proposes a solid-state circuit breaker comprising silicon carbide (SiC) MOSFETs and a SiC diode, based on the principle of avalanche voltage clamping. The key challenge in realizing a solid-state circuit breaker lies in reducing conduction loss. A parallel connection of power semiconductor devices is the suitable configuration that can meet these requirements. However, in such a configuration, the current balance during cutoff operation may be affected by the variation in the breakdown voltage characteristics of the power semiconductor devices. To address this issue, the proposed circuit breaker employs clamping with a SiC merged pin Schottky (MPS) diode, with high avalanche tolerance and robust characteristics under repetitive avalanche events. The effectiveness of the proposed solid-state circuit breaker is validated through experiments conducted in an unclamped inductive switching (UIS) test circuit using a 400-V, 50-A DC distribution system. Eventually, the demonstrations indicate that the SiC diode clamping method contributes to more compact implementations for solid-state circuit breakers.

DOI： 10.1109/OJPEL.2024.3365830

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Publishing type：Research paper (scientific journal)   Publisher：Institute of Electrical and Electronics Engineers (IEEE)  

The health monitoring prediction of power devices is vital for power electronics applications such as renewable converters, electric vehicles, and machine drives. One significant failure mode in the power cycle degradation of Insulated Gate Bipolar Transistor (IGBT) modules is bond wire lift-off. This study uses the gate voltage waveform (Vge ) as an input to an artificial intelligence (AI) model with the Convolutional Neural Network (CNN). The CNN was demonstrated to accurately estimate the IGBT bond wire lift-off, categorizing it into four levels: no damage, light damage, medium damage, and heavy damage. The Digital Gate Driver (DGD) IC was implemented to generate the Vge and collect the data waveforms by two switching modes: Conventional Vector Control (CVC) and 2-step Vector Control (2-sVC). The experiment evaluated the accuracy of the four-level estimation in several aspects. These aspects include switching modes, the number of datasets, and parts of the waveform The results show that the CNN model achieved high accuracy in estimating the wire lift-off trend. The Vge waveform generated by the 2-sVC switching mode showed better estimation accuracy compared to the CVC mode. Furthermore, it also obtained an effective switching performance Eloss -Vce-surge Trade-off curve. Therefore, the DGD is suitable for application and useful for health monitoring and achieving effective switching performance.

DOI： 10.1109/ACCESS.2024.3427643

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Publishing type：Research paper (scientific journal)   Publisher：Elsevier BV  

This paper investigates the reliability of a solid-state circuit breaker with a clamped SiC diode as avalanche voltage after repeated cutoff operations. In solid-state circuit breakers, a clamping element is connected in parallel with a power semiconductor switch to divert the cutoff current. The SiC merged PiN Schottky (MPS) diode is one of the candidates for clamping elements in solid-state circuit breakers because of its high avalanche tolerance and good robustness after the shocks. Reliability tests indicate that no significant electrical characteristics are found for both the SiC MOSFET and the SiC MPS diode in the proposed circuit breaker, even after more than 10,000 unclamped inductive switching (UIS) cycles. These results are based on a 400 V, 50 A DC distribution system with the UIS condition. The results show that the SiC MPS diode works well as a clamped element for the long-term reliability of the solid-state circuit breaker.

DOI： 10.1016/j.microrel.2023.115119

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Language：Others   Publishing type：Research paper (scientific journal)   Publisher：Elsevier BV  

This paper aims to clarify the effect of asymmetric gate inductance Lg and emitter inductance Le inside power modules with two parallel-connected IGBTs on switching characteristics when a three-step digital gate driver is employed. Five types of IGBT modules with different Lg and Le were fabricated to implement double pulse tests by conventional gate driving and digital gate driving with three-step vectors. Under the conventional gate driving, the asymmetric Le introduced an imbalanced current during on-stage, and the asymmetric Lg introduced gate voltage spike Vg_spike and an imbalanced current during the turn-off interval. Large Lg introduced large Vg_spike. From the miller plateau in the turn-off, the current started to concentrate on the IGBT whose Lg is small. In the turn-on interval, the asymmetric Le made current share in two IGBTs become imbalanced, and the occurred large Vg_spike is positively corresponding to the difference of emitter current Ie flowing through two IGBTs. Under digital gate driving, it was found that the tradeoff between switching loss and voltage/current overshoots can be improved. And, the difference of Eoff between two IGBT chips, which results from asymmetric Le mainly, could be decreased more than that in conventional gate driving. In the turn-on interval, the large Vg_spike can be suppressed by a small vector number at the second step, and the difference of turn-on loss Eon could be also decreased. According to the above switching characteristics, the design considerations of power modules with parallel-connected IGBTs were proposed as the digital gate driver is applied.

DOI： 10.1016/j.pedc.2023.100047

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Language：Others   Publishing type：Research paper (scientific journal)   Publisher：Elsevier BV  

This paper presents a new detection method of bond wire lift-off in Insulated Gate Bipolar Transistor (IGBT) power module. The bond wire lift-off is a major failure mode in power cycle degradation of the IGBT module, and many monitoring methods have been proposed and demonstrated for safety operation of power electronics systems in the previous works. In this study, we focus on the gate voltage waveform as an indicator to detect wire-lift for a simple and straightforward detection method. Due to the increase in parasitic inductance caused by bond wire lift-off, the turn-off switching waveform becomes modulated. The digital gate control (DGC) was employed to control the switching behavior to obtain precision for low-noise and high-performance. Furthermore, the DGC 2-step vector control (2-sVC) can enhance the sensitivity of bond wire lift-off failure detection by gate voltage waveform change. As feature quantities, the gate voltage spike peak, its amplitude and the timing shift were measured at various operating conditions. The DGC obtained larger feature quantities compared with conventional gate control. In particular, high-current conditions were found to be more favorable for achieving high sensitivity due to the high die/dt. From these results, the DGC is effective to achieve both the high sensitivity to detect bond wire lift-off by gate voltage waveform and maintaining the best switching performance.

DOI： 10.1016/j.pedc.2023.100052

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Language：Others   Publishing type：Research paper (scientific journal)   Publisher：IEEE Transactions on Industry Applications  

This paper proposes a current limiting function for a self-sensing and self-triggering monolithically integrated SiC circuit breaker device. The proposed function provides the device not only with a fast-response current breaking operation but also with the current limiting operation, including supplying a constant current to the load and preventing the detection of inrush currents. This function is suitable for replacing mechanical conductors in initial charging circuits within rectifiers and safety equipment in case of overcurrent phenomena. The proposed method achieves certain constant currents through a simple variation of the gate-drive circuit with the adjustable parameters of an additional MOSFET. The mechanism of the current limiting function is verified using TCAD simulations based on certain conditions. Consequently, experimental results verified that the circuit breaker device with the current limiting function reduces the inrush current by up to 76.9&#x0025; using a 500 VDC distribution circuit system.

DOI： 10.1109/TIA.2023.3288856

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Language：Others   Publishing type：Research paper (scientific journal)   Publisher：Microelectronics Reliability  

The bond wire lift-off is the one of main failures for insulated gate bipolar transistors (IGBT) power modules. The wire lift-off increases parasitic inductance LeE in the module and the gate voltage Vge waveform is modulated by LeE·dIe/dt. Therefore, the Vge waveform has the potential for an indicator of condition monitoring. The Digital gate control (DGC) can control switching behavior precisely for low-loss and low-noise switching. It is also effective for sensitivity enhancement of Vge waveform changed by the wire lift-off. This paper reports how the DGC 2-step vector control (2-sVC) can improve the wire lift-off failure detection sensitivity by Vge waveform. The experiment results showed that the Vge spike was generated by LeE·dIe/dt at the turn-off switching and the spike generation timing depended on the wire number. The DGC obtained the larger timing-shift Δtwire and the amplitude ΔVge-surge than those at the conventional gate control. In addition, the best vector condition improved the trade-off between turn-off loss and collector voltage overshoot compared with the conventional gate control. From these results, the DGC is effective to enhance the sensitivity of bond wire lift-off detection by Vge waveform maintaining the best switching performance.

DOI： 10.1016/j.microrel.2023.115067

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Language：Others   Publishing type：Research paper (scientific journal)   Publisher：Microelectronics Reliability  

A new sensor device is proposed for detection of power cycle degradation. Proposed sensor device is consisting of a Schottky-barrier MOSFET and the sensing principle is based on change of I-V characteristics by mechanical stress. Samples were fabricated by metal lift-off process and SiO2 gate insulator film deposition and the fundamental operation was evaluated by four-point bending test for mechanical stress applying. The fabricated device showed monotonically drain current change with number of stress cycles and about 5 times current change compared with initial current after 10,000 cycles of 4 N stress. Large current change by cyclic mechanical stress is attractive for a simple detection of power cycle degradation without expensive analog-circuits.

DOI： 10.1016/j.microrel.2023.115068

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Language：Others   Publishing type：Research paper (scientific journal)   Publisher：Japanese Journal of Applied Physics  

Thermally activated defect behaviors in nitrogen (N)-doped Czochralski silicon (Cz-Si) single crystals were investigated using deep level transient spectroscopy and quasi-steady-state photoconductance to confirm the crystals’ applicability in insulated gate bipolar transistors (IGBTs). The thermally activated defects, which were probably N-vacancy complexes and degraded the minority carrier lifetime, were detected with extremely low densities in N-doped Cz-Si compared with N-rich floating zone Si single crystals after heat treatments at 500 °C, resulting in a high remaining value of minority carrier lifetime. The difference was assumed to come from whether vacancies were released in the Si matrix during heat treatment. For the Cz-Si, vacancies were assumed to be strongly bound with oxygen atoms with concentrations of 1017 atoms cm−3. Therefore, vacancies were not released during heat treatment, resulting in low remaining N-vacancy complex densities. N-doped Cz-Si are potential materials for IGBTs because of their low densities from thermally activated defects.

DOI： 10.35848/1347-4065/ace011

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Language：Others   Publishing type：Research paper (scientific journal)   Publisher：Japanese Journal of Applied Physics  

Grown-in defect-free wafers are required in silicon semiconductor devices. A point defect concentration simulation was performed along with an experimental investigation, demonstrating a wide range of oxygen concentrations from 1.6 × 1017 to 9.1 × 1017 cm−3 in crystals. Thus, the effect of oxygen atoms in a Czochralski silicon single crystal with grown-in defect behavior was revealed. Consequently, the increasing vacancy concentration trapped by the oxygen atom (oxygen coefficient) was estimated as 4.61 × 10−5 per oxygen atom. Previously, for obtaining the oxygen coefficient, a regression equation assuming thermal equilibrium concentrations of vacancy (V) and interstitial Si (I) was applied to the experimental results. However, the interface shape, thermal stress, and hot-zone structure of the experimental level needed to be arranged; this affected the grown-in defect behavior. In this study, the oxygen coefficient and thermal equilibrium concentration of V and I were determined uniquely without arranging the situations experimental level.

DOI： 10.35848/1347-4065/acde27

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Language：Others   Publishing type：Research paper (scientific journal)   Publisher：Journal of Crystal Growth  

This study investigated the impact of the Marangoni effect of oxygen on the solid–liquid interface shape in the silicon single-crystal growth process by the transverse magnetic-field-applied Czochralski (Cz) method. To this end, the results of a 3D heat and mass transfer analysis were compared with the experimental results. The findings of the study revealed that the Marangoni effect of oxygen affected the solid–liquid interface shape predicted by the simulation. Moreover, with the introduction of this effect, both the solid–liquid interface shape and temperature distribution of the melt were found to be in good agreement with the experimental values.

DOI： 10.1016/j.jcrysgro.2023.127123

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Language：Others   Publishing type：Research paper (other academic)   Publisher：7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023  

There are several thermal budget processes for Si-IGBT fabrication, which sometimes cause dislocation propagation. The dislocation propagation depends on temperature and time of the process. In this paper, we analyzed the dislocation propagation in Si wafer during Si-IGBT fabrication process. We also calculated the dislocation density during diffusion process with several temperatures and times, and we confirmed that the lower temperature process causes the smaller dislocation propagation which may carry out the good device performance.

DOI： 10.1109/EDTM55494.2023.10103031

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Language：Others   Publishing type：Research paper (scientific journal)   Publisher：Journal of Crystal Growth  

The effect of the thermal conductivity of a crucible in a silicon carbide physical vapor transport furnace on the dislocation distribution in crystal was investigated using numerical analysis. The numerical analysis includes stress and dislocation propagation calculations based on the Alexander–Haasen model. Modifying the thermal conductivity of the carbon crucible can reduce the dislocation density. It can also homogenize the temperature distribution in the radial distribution in the crystal. The density of dislocations could be further by reduced using a carbon crucible with low thermal conductivity.

DOI： 10.1016/j.jcrysgro.2022.126981

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Language：Others   Publishing type：Research paper (scientific journal)   Publisher：Institute of Electrical and Electronics Engineers (IEEE)  

This paper clarifies the effect of gate inductance $L_{g}$ inside IGBT modules on gate voltage spikes when a digital gate driver is employed. Three IGBT modules with different $L_{g}$ were fabricated to implement double pulse tests by conventional gate driving and digital control gate driving with three-step vectors. It was found that the tradeoff between switching loss and voltage/current overshoots can be improved by digital control, but a large gate voltage spike was generated when gate-driving vectors were changed. And the spike voltage $V_{g\_{}spike}$ was positively correlated to the $L_{g}$. Although the $V_{g\_{}spike}$ can also be suppressed by decreasing the difference of gate driving vectors between the first and the second steps, the improvement of the tradeoff is weakened. Therefore, it is required that the $L_{g}$ inside the IGBT modules should be reduced to suppress the $V_{g\_{}spike}$ while improving the tradeoff by the digital gate driver at the same time. Furthermore, by analyzing the oscillation of the $V_{g\_{}spike}$ , it indicates that there should be some other stray elements, which couple $L_{g}$ and the stray capacitance inside IGBT chips, affecting the $V_{g\_{}spike}$.

DOI： 10.1109/access.2023.3237266

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Publishing type：Research paper (international conference proceedings)   Publisher：ICPE 2023-ECCE Asia - 11th International Conference on Power Electronics - ECCE Asia: Green World with Power Electronics  

This paper proposes a solid-state circuit breaker with avalanche robustness during cutoff operation using series-connection of SiC diodes. Solid-state circuit breakers need to consume energy generated by energy dissipation in the wiring inductance when the cutoff operation. The proposed solid-state circuit breaker improves the cutoff current tolerance by using SiC diodes connected in series to share the avalanche energy. Furthermore, the consuming energy by the solid-state circuit breaker is reduced by maintaining a higher clamping voltage than using single SiC diode during the interruption operation. Experimental results show that the proposed solid-state circuit breaker with two series-connection SiC diodes reduces the consumed avalanche energy by 34.3% compared to using single SiC diode under the same cutoff condition. The proposed solid-state circuit breaker is investigated based on a 400 VDC distribution system with unclamped inductive switching (UIS) condition up to 50 A cutoff current.

DOI： 10.23919/ICPE2023-ECCEAsia54778.2023.10213947

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Publishing type：Research paper (international conference proceedings)   Publisher：Proceedings of the International Symposium on Power Semiconductor Devices and ICs  

Failure process by overvoltage stress in GaN-HEMTs is discussed by burst UIS waveforms and C-V characteristics shift. One of the critical disadvantages of GaN-HEMTs is its lack of the UIS withstanding capability, because there is no removal structure of holes, which generated by the avalanche breakdown. Although overvoltage margin for the GaN power converters has been discussed by dynamic breakdown voltage, failure process by overvoltage stress has not been discussed sufficiently. This paper shows that overvoltage stress generated local shunt path between drain and substrate, graduated dielectric breakdown and hole trap/de-trap were observed by repetitive overvoltage stress. These results verify catastrophic failure of GaN-HEMTs by overvoltage stress is ascribed to a percolation process activated by the high-vertical electric field in hetero-epitaxial layers.

DOI： 10.1109/ISPSD57135.2023.10147411

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Language：Others   Publishing type：Research paper (scientific journal)   Publisher：Microelectronics Reliability  

N parallel-connected SiC MOSFETs were investigated to apply to solid-state circuit breakers (SSCB), and it is an extension of a method that was proved valid by experiment of two parallel-connected SiC MOSFETs. The unclamped inductive switching (UIS) test was considered as the emergency interruption of SSCBs in this research. Because of the variations of breakdown voltage among SiC MOSFETs, the current flowing through devices is imbalanced during emergency interruption of SSCBs, which can drive some of the devices into thermal destruction prematurely. There are many compound cases for several SiC MOFETs with a certain maximum breakdown voltage variation. And the worst case, where the breakdown voltage of one device is assumed as the lowest, whereas the other devices have the same breakdown voltage, was extracted from the calculated results of four parallel-connected situation. In the worst case, it was found that the relation of breakdown voltage variations and current capacity is linear. Moreover, the distributions of breakdown voltage were taken as normal distributions. Using the worst case and distributions, a linear relation of breakdown voltage distributions and rated current of an SSCB could be concluded as a function of paralleled-connected numbers (N). Utilizing the function, the necessary breakdown voltage distributions and N of SiC MOSFETs can be evaluated for SSCBs meeting a certain yield ratio and current.

DOI： 10.1016/j.microrel.2022.114737

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Language：Others   Publishing type：Research paper (scientific journal)   Publisher：IEEE Transactions on Semiconductor Manufacturing  

Nitrogen-doped silicon wafers manufactured using the Czochralski technique (Cz-Si) with an oxygen concentration (OI) of 2.5&#x2013;5.6 &#x00D7; 1017 atoms cm-3 are heat treated to simulate the conventional and scaled manufacturing processes of insulated gate bipolar transistors (IGBTs). Subsequently, the oxygen precipitation, lifetime, and gate oxide integrity (GOI) of the Cz-Si wafers are evaluated. After the high-temperature heat treatment that simulates the conventional process, the lifetime of the Cz-Si with an OI of 5.6 &#x00D7; 1017 atoms cm-3 only degrades slightly even when oxide precipitates are not detected. In contrast, after the low-temperature heat treatment that simulates the scaled process, oxide precipitates are detected and the lifetime reduces substantially at an OI of 5.6 &#x00D7; 1017 atoms cm-3. The Cz-Si with OI values below 3.3 &#x00D7; 1017 atoms cm-3 are considered suitable materials for IGBTs because no oxide precipitate is formed, and the lifetime is not degraded after high-and low-temperature heat treatments. Upon using GOI evaluation, the nitrogen-doped Cz-Si wafers are found to exhibit a breakdown voltage equal to that of an annealed Cz-Si wafer conventionally used for IGBTs. Therefore, nitrogen-doped Cz-Si wafers with OI below 3.3 &#x00D7; 1017 atoms cm-3 are potential materials for conventional and scaled IGBTs.

DOI： 10.1109/TSM.2022.3199862

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

Unclamped inductive switching (UIS) robustness of SiC devices with parallel-connected varistor was evaluated to design the cutoff current capability of solid-state circuit breakers (SSCBs). Because the operation of UIS tests is similar to that in the interruption of SSCBs, UIS tests of SiC devices without varistor and with a parallel-connected varistor were implemented. It was found that the cutoff current of SiC devices with the varistor was much larger than that without varistor. The effect of varistor on the increase of cutoff current depended on the device type and rating current. The cutoff current was 3-6 times higher for planar MOSFETs and 5-10 times higher for trench MOSFETs compared with no varistor condition. In contrast, the effect of varistor for JFET was small because the gate drive condition strongly affected the current switching time from SiC-JFET to varistor. The index of rating current for cutoff current capability was changed by parallel varistor connection because the destruction mechanism of SiC devices was changed because of the change in self-heating timing during the UIS.

DOI： 10.1109/TED.2022.3200637

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：Institute of Electrical and Electronics Engineers ({IEEE})  

A new parameter optimization method using zoomed response surface (RS) is proposed for automatic design of low-voltage power MOSFET. Low-voltage MOSFET characteristics have been improved continuously considering with not only low power loss but also low cost to answer request to high-performance system. Complicated requirements lead long development schedule and low yield. Model-based design and machine learning are prospective method to answer the problem. However, reported methods require many simulation numbers (>1000) for training to obtain high accuracy, and it is difficult to optimize parameters considering the process margin at the same time. This article shows a simple design method using zoomed RS. Five parameters were automatically designed, taking account to process margin with simulation number of 130 only.

DOI： 10.1109/JEDS.2022.3187151

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：Institute of Electrical and Electronics Engineers ({IEEE})  

Scaling design effects on surface buffer (SB) insulated gate bipolar transistor (IGBT) is analyzed not only for power loss reduction but also for switching controllability and robustness using TCAD simulation. Although the scaling design improves turn-off loss and on-state voltage drop V-ce(sat) trade-off due to injection enhancement (IE) effect, turn-on surge current is increased by the enhancement of negative gate capacitance due to thin gate oxide. Dual gate control improves turn-on switching controllability by hole current path control. Short circuit robustness is improved by the scaling design, because the saturation current is decreased with the scaling design due to pinch-off of the n-MOS channel. From these results, the scaling design is effective in improving the SB-IGBT characteristics including high robustness.

DOI： 10.1109/JEDS.2021.3129162

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Language：Others   Publishing type：Research paper (other academic)   Publisher：2022 IEEE Energy Conversion Congress and Exposition, ECCE 2022  

This paper proposes a current limit feature for a multi-functional SiC circuit breaker device with a “dual thyristor” structure. The proposed feature provides the device not only with a fast-response current breaking operation but also with the current limiting function, including supplying a constant current to the load and preventing the detection of inrush currents. The proposed feature is suitable for replacing mechanical circuit breakers in initial charging circuits for the rectifiers and a safety equivalent in case of overcurrent accidents. The proposed method achieves various constant currents by simply varying the gate-drive circuit with adjustable parameters of an additional MOSFET. Experimental results verified that the device with the current limit feature reduces the inrush current to up to 22.6% of capacitive load condition using a 500 VDC circuit system.

DOI： 10.1109/ECCE50734.2022.9948054

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Language：Others   Publishing type：Research paper (other academic)   Publisher：IEEE Workshop on Wide Bandgap Power Devices and Applications in Europe, WiPDA Europe 2022  

Unclamped inductive switching (UIS) robustness of SiC MOSFETs with parallel connected varistor was evaluated to design the cutoff current capability of solid-state circuit breakers. Because the operation of UIS tests is similar to that in the interruption of solid-state circuit breakers, UIS tests of SiC MOSFETs without varistor and with a parallel-connected varistor were implemented. It was found that the cutoff current of SiC MOSFETs with the varistor was 3 to 6 times larger than that without varistor. The index of rating current for cutoff current capability was changed by parallel varistor connection, because the destruction mechanism of SiC MOSFETs was changed because of the change in self-heating timing during the UIS. From dependence of cutoff current on rating current, load inductance and varistor voltage, it is verified that the cutoff current of SiC MOSFET with varistor was limited by saturation current and current filament.

DOI： 10.1109/WiPDAEurope55971.2022.9936060

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Language：Others   Publishing type：Research paper (other academic)  

This paper presents the short circuit performance of a novel SiC circuit breaker device, which is based on the 'thyristor dual' functionality. The developed device structure is motivated with regard to manufacturing aspects and electrical requirements. Furthermore, the basic 'thyristor dual' operation is elaborated on the basis of quasi-static electrical measurements of a fabricated prototype. The proposed self-sensing and self-triggering devices make auxiliary circuitry like sensors and micro-controllers expendable and practically have no propagation delay. As a result, short circuit clearance within 122 ns at 800 V is demonstrated in experiments. Moreover, by utilisation of a third device terminal, a temporary current limiter functionality can be obtained. The scalability of the current limit value is discussed on the basis of measurements in time domain. The maximum current limit value achieved is 7.4 times higher than the trigger current level of the circuit breaker device. Additionally, the same circuit configuration which is used for the current limiting mode, allows to remotely reset the circuit breaker after it turned to blocking-state. This opens up a wide range of possibilities to enhance the circuit breaker with intelligent functionalities.

Publishing type：Research paper (international conference proceedings)  

This paper presents the short circuit performance of a novel SiC circuit breaker device, which is based on the 'thyristor dual' functionality. The developed device structure is motivated with regard to manufacturing aspects and electrical requirements. Furthermore, the basic 'thyristor dual' operation is elaborated on the basis of quasi-static electrical measurements of a fabricated prototype. The proposed self-sensing and self-triggering devices make auxiliary circuitry like sensors and micro-controllers expendable and practically have no propagation delay. As a result, short circuit clearance within 122 ns at 800 V is demonstrated in experiments. Moreover, by utilisation of a third device terminal, a temporary current limiter functionality can be obtained. The scalability of the current limit value is discussed on the basis of measurements in time domain. The maximum current limit value achieved is 7.4 times higher than the trigger current level of the circuit breaker device. Additionally, the same circuit configuration which is used for the current limiting mode, allows to remotely reset the circuit breaker after it turned to blocking-state. This opens up a wide range of possibilities to enhance the circuit breaker with intelligent functionalities.

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Language：Others   Publishing type：Research paper (other academic)   Publisher：Proceedings of the International Symposium on Power Semiconductor Devices and ICs  

This work presents the switching performance of a novel solid-state circuit breaker device suitable for DC-applications up to 800 V. These "dual thyristor"devices are manufactured employing a 4H-SiC JFET technology. With respect to scalability, the influence of specific design parameters on the quasi-static output characteristics are discussed along with corresponding fabrication aspects. In order to investigate the switching performance, clamped and unclamped inductive switching (CIS and UIS) experiments at up to 800 V are carried out. In case of CIS, current clearance is achieved within 642 ns after the self-sensed trigger event at 1.75 A. The UIS experiments reveal stable current handling capability during avalanche.

DOI： 10.1109/ISPSD49238.2022.9813628

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Language：English   Publishing type：Research paper (other academic)   Publisher：IEEE  

Design of trench gate and p-column position in Superjunction (SJ)-IGBTs are discussed to improve the trade-off characteristics between surge voltage/current and turn-off/-on losses. Power electronics systems require not only low power loss but also low EMI noise for high cost performance by system downsizing. Although SJ-IGBTs are attractive for low loss operation due to thin drift layer and fast removal of the excess carriers through the p- and n-columns at the turn-off operation, the switching trade-off characteristics of SJ-IGBTs compared with the conventional IGBT and the improvement design have not been discussed sufficiently. This paper shows better switching trade-off compared with a conventional IGBT can be obtained by the trench gate and p-column designs due to management of the gate capacitance and hole current flow, because negative gate capacitance influences on not only turn-on switching but also turn-off switching.

DOI： 10.1109/ISPSD49238.2022.9813643

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Language：Others   Publishing type：Research paper (other academic)   Publisher：Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC  

This paper proposes a solid-state DC circuit breaker composed of SiC MOSFETs and a SiC diode, based on the principle of avalanche voltage clamping. To realize a solid-state DC circuit breaker, it is necessary to reduce the conduction loss and increase the breaking capability. A parallel connection of power semiconductor devices is the most suitable configuration that can meet these requirements. However, in such a configuration, the current balance during current interruption may be affected by the difference in the breakdown voltage characteristics of the power semiconductor devices. The proposed solid-state DC circuit breaker is clamped using a SiC merged pin Schottky diode with high avalanche tolerance and robust characteristics under repetitive avalanche events. Experimental results from an unclamped inductive switching test circuit with a 400-V DC distribution system show that the proposed solid-state DC circuit breaker can interrupt currents up to 50-A.

DOI： 10.1109/APEC43599.2022.9773380

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Language：Others   Publishing type：Research paper (other academic)  

This paper aims to clarify the effect of parallel-connected varistor on unclamped inductive switching (UIS) robustness of SiC MOSFETs to improve the cut-off current capability of solid-state circuit breakers (SSCB). Because the operation of UIS tests is similar to that in the interruption of SSCB, UIS tests of SiC MOSFETs without varistor and with a parallel-connected varistor were implemented. It was found that the cut-off current of SiC MOSFETs with the varistor is much larger than that of SiC MOSFETs without varistor. The effect of varistor on increase of cut-off current depends on the MOS-gate type. The cut-off current is 3-5 times higher for planar-gate devices and 5-10 times higher for trench-gate devices compared with no varistor condition. To analyze mechanism of cut-off current increased by the varistor, the junction temperature in UIS tests with and without the varistor was estimated by simulation using experimental wave-forms. The simulation results show that the destruction mechanism of SiC MOSFETs is changed by varistor connection due to change of self-heating timing during the UIS.

Publishing type：Research paper (international conference proceedings)  

This paper aims to clarify the effect of parallel-connected varistor on unclamped inductive switching (UIS) robustness of SiC MOSFETs to improve the cut-off current capability of solid-state circuit breakers (SSCB). Because the operation of UIS tests is similar to that in the interruption of SSCB, UIS tests of SiC MOSFETs without varistor and with a parallel-connected varistor were implemented. It was found that the cut-off current of SiC MOSFETs with the varistor is much larger than that of SiC MOSFETs without varistor. The effect of varistor on increase of cut-off current depends on the MOS-gate type. The cut-off current is 3-5 times higher for planar-gate devices and 5-10 times higher for trench-gate devices compared with no varistor condition. To analyze mechanism of cut-off current increased by the varistor, the junction temperature in UIS tests with and without the varistor was estimated by simulation using experimental wave-forms. The simulation results show that the destruction mechanism of SiC MOSFETs is changed by varistor connection due to change of self-heating timing during the UIS.

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Language：Others   Publisher：Japanese Journal of Applied Physics  

In this paper, the turn-on characteristics of the 1.2 kV Trench IGBT (TIGBT) and the 1.2 kV Trench Clustered IGBT (TCIGBT) are investigated through TCAD simulations and experiments. The TCIGBT shows much lower turn-on energy loss (E on) due to higher current gain than an equivalent TIGBT and the negative gate capacitance effect is effectively suppressed in the TCIGBT by its self-clamping feature and PMOS action. In addition, the impact of 3D scaling rules on the turn-on performance of TIGBT and TCIGBT is analyzed in detail. Simulation results show that scaling rules result in a significant reduction of E on in both TIGBT and TCIGBT. Furthermore, the experimental results indicate that TCIGBT technology is well suited for high current density operations with low power losses. Compared to the state-of-the-art IGBT technology, an 18% reduction of total power loss can be achieved by the TCIGBT operated at 300 A cm-2 and 175 °C.

DOI： 10.35848/1347-4065/ac40aa

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Publisher：ETG-Fachbericht  

This paper aims to clarify the effect of parallel-connected varistor on unclamped inductive switching (UIS) robustness of SiC MOSFETs to improve the cut-off current capability of solid-state circuit breakers (SSCB). Because the operation of UIS tests is similar to that in the interruption of SSCB, UIS tests of SiC MOSFETs without varistor and with a parallel-connected varistor were implemented. It was found that the cut-off current of SiC MOSFETs with the varistor is much larger than that of SiC MOSFETs without varistor. The effect of varistor on increase of cut-off current depends on the MOS-gate type. The cut-off current is 3-5 times higher for planar-gate devices and 5-10 times higher for trench-gate devices compared with no varistor condition. To analyze mechanism of cut-off current increased by the varistor, the junction temperature in UIS tests with and without the varistor was estimated by simulation using experimental wave-forms. The simulation results show that the destruction mechanism of SiC MOSFETs is changed by varistor connection due to change of self-heating timing during the UIS.

Scopus

Publisher：24th European Conference on Power Electronics and Applications, EPE 2022 ECCE Europe  

This paper presents the short circuit performance of a novel SiC circuit breaker device, which is based on the 'thyristor dual' functionality. The developed device structure is motivated with regard to manufacturing aspects and electrical requirements. Furthermore, the basic 'thyristor dual' operation is elaborated on the basis of quasi-static electrical measurements of a fabricated prototype. The proposed self-sensing and self-triggering devices make auxiliary circuitry like sensors and micro-controllers expendable and practically have no propagation delay. As a result, short circuit clearance within 122 ns at 800 V is demonstrated in experiments. Moreover, by utilisation of a third device terminal, a temporary current limiter functionality can be obtained. The scalability of the current limit value is discussed on the basis of measurements in time domain. The maximum current limit value achieved is 7.4 times higher than the trigger current level of the circuit breaker device. Additionally, the same circuit configuration which is used for the current limiting mode, allows to remotely reset the circuit breaker after it turned to blocking-state. This opens up a wide range of possibilities to enhance the circuit breaker with intelligent functionalities.

Scopus

Web of Science

Language：English   Publishing type：Research paper (scientific journal)  

The realization of a DC breaker using semiconductors requires multiple power devices with low ON resistance to be connected in parallel. On the other hand, power devices that experience current interruption enter the avalanche mode to consume the energy stored in the parasitic inductance in the circuit wiring. In other words, a DC breaker requires the current balancing of multiple power devices connected in parallel during the avalanche mode. In this paper, a method to balance the current of power devices in avalanche mode is investigated. As a result, the use of SiC-JFET with cascode connections is found to be a suitable method by 400 V experimental system.

DOI： 10.1016/j.microrel.2021.114237

Language：Others   Publishing type：Research paper (scientific journal)  

This paper aims to investigate the acceptable breakdown voltage variation of parallel-connected SiC power MOSFETs applied to solid-state circuit breakers (SSCB) under different total current conditions and its numerical simulation model. Due to variation of breakdown voltage among SiC power MOSFETs, the current flowing through devices is imbalanced during emergency interruption of SSCBs, which can drive some of the devices into thermal destruction. The unclamped inductive switching (UIS) test was imaged as the emergency interruption of SSCBs in this research. The UIS test of two parallel-connected SiC power MOSFETs was implemented. Proposed numerical simulation represents the experimental results with failure criteria by considering self-heating due to imbalanced current flowing. And it was found that the acceptable breakdown voltage variation and the total current have a linear relation.

DOI： 10.1016/j.microrel.2021.114270

Language：English   Publishing type：Research paper (international conference proceedings)  

DOI： doi:10.23919/SISPAD49475.2020.9241627

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/JEDS.2021.3079396

Language：Others   Publishing type：Research paper (scientific journal)  

The interstitial oxygen concentration ([OI]) dependence of the as-grown defect (voids and dislocation clusters) behavior in nitrogen-doped silicon crystals fabricated by Czochralski technique (Cz-Si) have been investigated. Nitrogen-doped Cz-Si crystals with [OI] values of 7–8 and 1–3 × 1017 atoms cm−3 are evaluated, and it was found that the range of v/G in which as-grown defect-free (AGDF) region can be obtained become wide with decreasing [O I], where v is the crystal growth rate and G is the axial temperature gradient at the solid–liquid interface. This result indicates that as-grown defect suppression effect by nitrogen doping is enhanced at low [OI].By the analysis based on a thermodynamic model, it is shown that nitrogen–vacancy (NV) and nitrogen–oxygen (NO) complexes compete in the nitrogen-doped Cz-Si crystals and their concentration fraction changes with [OI] value. At low [OI], the concentration of the NO complex becomes low; thus, the concentration of nitrogen that can form NV complexes increases, thereby enhancing the as-grown defect suppression effect. Silicon wafers for insulated gate bipolar transistors (IGBTs) are required AGDF and oxide precipitate-free, therefore nitrogen-doped Cz-Si crystals with low [OI] values are suitable for the fabrication of silicon wafers for IGBTs.

DOI： 10.1016/j.jcrysgro.2021.126236

Language：English   Publishing type：Research paper (scientific journal)  

DOI： doi:10.35848/1347-4065/abc1d0

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/LED.2021.3075657

Language：English   Publishing type：Research paper (scientific journal)  

A new device design in trench-gate insulated gate bipolar transistor (IGBT) with dual gate control is proposed for high switching controllability with low loss operation. Injection enhancement effect is effective to obtain low power loss operation of IGBTs. However, excess drift carriers limit turn-off dV/dt, and turn-on dI/dt, and the switching controllability by the external gate resistance is degraded. Surface buffer (SB) IGBT with dual gate control is effective to improve the switching controllability, because the hole current can be modulated effectively by the p-MOS control. TCAD simulation results show the SB-IGBT type-II with dual gate control is the best choice for good turn-off and turn-on switching performances.

DOI： 10.1109/LED.2021.3075657

Language：English   Publishing type：Research paper (scientific journal)  

Language：Others   Publishing type：Research paper (scientific journal)  

The design direction of low voltage field-plate (FP) power MOSFETs was studied toward the figure-of-merit (FOM) limit by TCAD simulation. The FOMs of R on Q g, R on Q sw, and R on Q oss are considering the on-resistance and the charge required for the switching to evaluate the conduction loss and the switching loss. The results show that thin oxide and narrow mesa structure is desired for minimizing on-resistance R on A and opposite design of thick oxide and wide mesa structure is a good choice to reduce R on Q sw for high switching frequency application. In addition, the potential of R on A and R on Q sw reduction is maintained, however, it is difficult to reduce the R on Q g and R on Q oss by the design parameter optimization. It is verified that power loss reduction in whole operating condition cannot be achieved only by the design parameter optimization and requires approach from the other direction.

DOI： 10.35848/1347-4065/abe801

Language：English   Publishing type：Research paper (other academic)  

A new structure with the optimum gate control is proposed for low power loss operation of low-voltage power MOSFETs. Although the application system requires continuing the on-resistance RonA reduction for more power efficiency improvement, RonA trend is facing the theoretical limit even with the FP technology. Assist Gate (AG) structure was proposed to improve the RonA and turn-off loss Eoff tradeoff, because the channel and drift resistances can be reduced with avoiding the Cgd increase by dual gate control. Dual gate control with synchronous rectify (SR) of AG-MOSFET also improves turn-on switching performance. This paper shows the AG-MOSFET with optimum gate control achieves 27&#37; lower turn-on loss Eon and 42&#37; lower surge current compared with no SR operation. A case study of the half-bridge application also shows 17&#37; to 46&#37; of total power loss reduction.

DOI： 10.23919/ISPSD50666.2021.9452240

Language：Others   Publishing type：Research paper (scientific journal)  

Current flowing through parallel-connected SiC MOSFETs are imbalanced during unclamped inductive switching (UIS) test, which can be imaged as the emergency interruption of solid-state circuit breakers, due to variations of breakdown voltage. The imbalanced current can drive devices into thermal destruction. This study evaluated acceptable breakdown voltage variations of two parallel-connected SiC MOSFETs under different total current, load inductances, and breakdown voltage temperature coefficient conditions during UIS mode operation by numerical simulation. The acceptable variation at 298 K was found to decrease with increasing total current and be influenced by the change of total current greater with larger inductances. SiC MOSFETs with larger breakdown voltage temperature coefficients allowing larger variations were also clarified.

DOI： 10.35848/1347-4065/abebc1

Language：Others   Publishing type：Research paper (other academic)  

Silicon trench-gate insulated gate bipolar transistors (IGBTs) were analyzed using technology CAD (TCAD). Excellent agreement was confirmed between the J_{C}^{- } }V_{ ext{CE} characteristics obtained by 3D- TCAD simulations and experiments. The carrier lifetime requirement for scaled trench-gate IGBTs was determined by extraction of the on-resistance of the n-base layer derived from the electric potential profile.

DOI： 10.1109/EDTM50988.2021.9420922

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.35848/1347-4065/abe801

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/TPEL.2020.3014560

Language：Others   Publishing type：Research paper (scientific journal)  

Turn-off dV/dt controllability is an essential feature in insulated gate bipolar transistors (IGBTs) for flexible design in power switching applications. However, the occurrence of dynamic avalanche (DA) during the turn-off transients plays a key role on the turn-off power loss, dV/dt controllability and safe operating area of IGBTs. This article aims to clarify the impact of DA on the turn-off characteristics of 1.2-kV trench IGBTs through three-dimensional technology computer aided design (TCAD) simulations as well as experimental demonstrations. Measurement results show that DA is enhanced at high current density and high supply voltage conditions, which aggravates its influence on the dV/dt controllability as well as turn-off power loss. To eliminate the DA for high current density and low loss operations, a DA free design is experimentally demonstrated in the Trench Clustered IGBT (TCIGBT). Due to effective management of electric field and unique p-channel metal oxide semiconductor (PMOS) actions during turn-off, TCIGBT can retain high dV/dt controllability and low power loss at high current density operations.

DOI： 10.1109/tpel.2020.3014560

Language：Others   Publishing type：Research paper (scientific journal)  

High-performance power devices require silicon crystals with long minority carrier lifetimes and, subsequently, low carbon concentrations. This paper reports in-situ measurements of carbon monoxide (CO) in a Czochralski growth furnace used for the growth of single-crystal silicon. During the heating and melting processes, the major causes of CO gas generation are (i) outgassing from carbon parts inside the furnace, (ii) reactions between the quartz and carbon crucible, and (iii) reactions between the silicon melt and quartz crucible. By conducting heating experiments with and without polysilicon and quartz crucibles, we successfully measured the independent CO generation contributions of causes (i), (ii), and (iii) listed above. The outgassing process generated CO gas during the heating process of the raw material. CO generated during the melting process of the raw material was attributed to reactions between (ii), the quartz and carbon, and (iii), the silicon melt and carbon parts, which occurred after CO outgassing from carbon parts in the furnace.

DOI： 10.1016/j.jcrysgro.2020.126015

Language：English   Publishing type：Research paper (scientific journal)  

DOI： doi:10.1016/j.jcrysgro.2020.126015

Language：English   Publishing type：Research paper (scientific journal)  

Language：Japanese   Publishing type：Research paper (scientific journal)  

DOI： https://doi.org/10.35848/1347-4065/abebc1

Language：Others   Publishing type：Research paper (other academic)  

Full integration of a back-gate-controlled IGBT (BC-IGBT), which comprises top and bottom independently controlled MOS gates, is experimentally demonstrated. By using the back side MOS gate for accelerating electron drain and blocking of hole injection, more than 60&#37; reduction of turn-off loss was achieved. Instead of the conventional wafer bonding approach, a cost effective process flow using double side lithography has been developed and used. Thanks to the process flexibility, back side design was carefully optimized to achieve stable operation and manufacturability, in addition to low switching loss. BC-IGBT will provide a new technological option for expanding the applicable switching frequency / voltage range of Si power devices.

DOI： 10.1109/IEDM13553.2020.9371909

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/LED.2020.3034898

Language：English   Publishing type：Research paper (scientific journal)  

A design direction in surface buffer insulated gate bipolar transistor (SB-IGBT) is shown for improvement of turn-on switching characteristics, such as switching controllability, current surge and turn-on loss. At turn-on switching, hole current around the gate degrades the switching controllability and induces EMI noise due to negative gate capacitance. However, SB-IGBT can be designed to suppress the negative gate capacitance by enhancement of hole evacuation through pMOS channel. Although turn-on loss can be decreased by small gate-collector capacitance C {gc} , the influence of negative gate capacitance is remarkable. Therefore, TCAD simulation results show that high hole evacuation through pMOS channel and optimum C {gc} design are effective to improve turn-on switching characteristics.

DOI： 10.1109/led.2020.3034898

Language：English   Publishing type：Research paper (scientific journal)  

This paper proposes a gate drive circuit for the current balancing of parallel-connected SiC-JFETs under avalanche mode. For a solid-state DC circuit breaker, the power devices have to be connected in parallel to reduce the ON-resistance and increase the current rating. In addition, it is reported that the SiC-JFET is suitable power devices from the viewpoint of both conduction loss and long-term reliability. This paper presents the behavior of current balancing of SiC-JFETs in parallel, and then proposes a design procedure of gate drive circuits. The gate drive circuits can achieve the current balance equalization of parallel-connected SiC-JFETs under avalanche mode. The validity of the proposed gate drive circuit is verified by the experiment that uses 1.2 kV SiC-JFETs in a 400 V system.

DOI： 10.1016/j.microrel.2020.113776

Language：English   Publishing type：Research paper (scientific journal)  

We report on the relationship between carrier lifetime degradation of floating-zone silicon (FZ Si) and the guard ring formation process for silicon integrated gate bipolar transistor (Si-IGBT). A clear carrier lifetime degradation was observed through the guard ring oxidation and annealing processes for Si-IGBT and showed interstitial oxygen (O-i) concentration dependence, which was obtained by Fourier transform infrared absorption spectroscopy. Based on the carrier lifetime measurements through the step etching of the FZ Si substrate, it has been suggested that the carrier lifetime degradation is not only caused by the O-i itself near the FZ Si surface region but also the other defects induced by the O-i injection. Diffused interstitial Si atoms kicked-out by the O-i into the FZ Si substrate, which has a longer diffusion length than O-i, can be considered to be the origin of the carrier lifetime degradation.

DOI： 10.35848/1347-4065/abc1d0

Language：English   Publishing type：Research paper (scientific journal)  

We report on the relationship between carrier lifetime degradation of floating-zone silicon (FZ Si) and the guard ring formation process for silicon integrated gate bipolar transistor (Si-IGBT). A clear carrier lifetime degradation was observed through the guard ring oxidation and annealing processes for Si-IGBT and showed interstitial oxygen (Oi) concentration dependence, which was obtained by Fourier transform infrared absorption spectroscopy. Based on the carrier lifetime measurements through the step etching of the FZ Si substrate, it has been suggested that the carrier lifetime degradation is not only caused by the Oi itself near the FZ Si surface region but also the other defects induced by the Oi injection. Diffused interstitial Si atoms kicked-out by the Oi into the FZ Si substrate, which has a longer diffusion length than Oi, can be considered to be the origin of the carrier lifetime degradation.

DOI： 10.35848/1347-4065/abc1d0

Language：Others   Publishing type：Research paper (scientific journal)  

It is well-known that the dynamic avalanche (DA) phenomenon poses fundamental limits on the power density, turn-off power loss, dV/dt controllability, and long-term reliability of MOS-bipolar devices. Therefore, overcoming this phenomenon is essential to improve the energy efficiency and ensure their safe operation. In this work, a detailed analysis of the 1.2-kV MOS-bipolar devices is undertaken through both calibrated TCAD simulations and experiments to show the fundamental cause of DA and the impact of the current density, supply voltage, and 3-D scaling rules on the DA performance. Furthermore, the DA performance of a 1.2-kV non-punch-through (NPT) trench clustered insulated gate bipolar transistor (TCIGBT) is evaluated for high current density and low power loss operations. The results indicate that this device configuration is free of DA and can be used for ultrahigh current density operation in an energy-efficient manner.

DOI： 10.1109/ted.2020.3007594

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/TED.2020.3007594

Language：Others   Publishing type：Research paper (other academic)  

Technology CAD (TCAD) has been recognized as a powerful design tool for Si insulated gate bipolar transistors (IGBTs). Here, physical models, such as a mobility model for carrier-carrier scattering, were investigated for a predictive TCAD. Simulated currentvoltage characteristics of the trench-gate IGBTs were compared with measurements. The difference between 3D- and 2D-TCAD simulations was observed in a high current region, which was explained by a bias-dependent current flow. A test element group (TEG) for separation of the emitter currents for holes and electrons was also determined as effective for calibration of lifetime model parameters.

DOI： 10.23919/SISPAD49475.2020.9241627

Language：English   Publishing type：Research paper (international conference proceedings)  

A new trench gate design in Si-IGBTs is proposed and analyzed for high controllability of turn-off dV/dt and turn-on dI/dt with low loss operation. Power electronics systems require not only low power loss but also low EMI noise for high cost performance by system downsizing. Although turn-off loss &#36;E _{off}&#36; and on-state voltage drop &#36;V _ce(sat)&#36;trade-off of IGBT can be improved by enhancement of Injection Enhancement (IE) effect, &#36;E _off&#36; is limited by dynamic avalanche at low external gate resistance &#36;R_{g}&#36; condition. In addition, EMI noise is induced by negative gate capacitance at the turn-on switching due to high dI/dt and large surge current &#36;I_{surge}&#36;. Therefore, the system designers require good switching controllability by &#36;R_{g}&#36; to adjust the power loss and EMI noise trade-off for the optimum system design. This paper shows the dynamic avalanche and negative gate capacitance can be suppressed by management of electric field concentration and hole current flow around the trench gate by proposed Alternated Trench (AT) structure and both good switching controllability and low power loss can be obtained.

DOI： 10.1109/ISPSD46842.2020.9170118

Language：English   Publishing type：Research paper (international conference proceedings)  

Dynamic Avalanche (DA) effects in the Super-Junction Trench IGBTs are analyzed through 3-D TCAD simulations for the first time. A DA free solution for high power density and low loss is proposed and demonstrated in detail. Furthermore, simulation results show that DA results in significant increase in turn-off losses in the Super-Junction Trench IGBTs at high current density operations, which poses a fundamental limit on the power density of IGBT applications. In contrast, the Super-Junction Trench Clustered IGBTs remain DA free at high current density and show low switching losses due to enhanced PMOS action. Therefore, the Super-Junction Trench IGBTs are well suitable for high power density operations with a potential to operate beyond the 1-D unipolar 4H-SiC limit.

DOI： 10.1109/ISPSD46842.2020.9170129

Language：English   Publishing type：Research paper (international conference proceedings)  

This paper shows a new process guideline of high thermal budget process with Si 300 mm wafer in order to eliminate the dislocations. In the case of IGBT, high thermal budget process such as oxidation, diffusion, etc., cause large stress in wafer, and make dislocation propagation, slip, then degrade the device performance and yield. This degradation is enhanced with increasing wafer diameter, and becomes more serious for 300 mm process than that of 200 mm. We clarify the relation between the process condition (time-temperature profile) and dislocation behavior quantitatively under high thermal budget process, and propose the guideline to optimize the process condition. The optimized process minimizes the dislocation propagation in 300 mm Si wafer as same as that in 200 mm Si wafer with the conventional process condition.

DOI： 10.1109/ISPSD46842.2020.9170035

Language：English   Publishing type：Research paper (scientific journal)  

A new gate structure in the trench-gate insulated-gate bipolar transistor (IGBT) design is proposed and analyzed for power-loss reduction and the suppression of electromagnetic-interference (EMI) noise. Although the turn-off loss and the ON-state voltage drop {V}_{ ext {ce(sat) } } are improved by the injection-enhancement (IE) effect, the IE effect caused dynamic avalanche that limits the turn-off loss reduction. In addition, EMI noise is induced by high dI/dt and large surge current due to the negative gate capacitance. This article shows that the dynamic avalanche and the negative gate capacitance can be suppressed by the management of the electric field concentration and hole current flow around the trench gate by the proposed alternated trench-gate (AT) IGBT structure, and both low power loss and good switching controllability can be obtained. The device simulation results show that the AT-IGBT improves the turn-on surge current {I}_{ ext {surge } } - {V}_{ ext {ce(sat) } } tradeoff compared with the conventional IGBTs.

DOI： 10.1109/TED.2020.3002510

Language：Others   Publishing type：Research paper (other academic)  

High dV/dt controllability of IGBTs is important to achieve high power efficiency and switching speed. However, the Dynamic Avalanche (DA) phenomenon in MOS-gated bipolar devices is one major issue to affect dV/dt controllability, switching loss as well as gate stability. In this paper, the fundamental limit of the turn-off dV/dt controllability of trench IGBTs is analyzed through 3-D TCAD simulations. A DA free design enabled by Trench Clustered IGBT (TCIGBT) is investigated to show significant improvement in dV/dt controllability compared to that of conventional TIGBT at same turn-off energy loss (Eoff) condition. Furthermore, experimental results confirm that TCIGBT can remain DA free performance and high dV/dt controllability at high temperature.

Language：English   Publishing type：Research paper (scientific journal)  

A new structure in trench-gate insulated gate bipolar transistor (IGBT) design is proposed and analyzed not only for power loss reduction but also for long-termstability and suppressing electromagnetic interference (EMI) noise using a device simulation. Although turn-off loss and ON-state voltage drop V-ce(sat) are improved by injection enhancement(IE) effect, IE effect causes dynamic avalanche that limits turn-off loss reduction and degrades long-term stability by the charge trap at the trench gate oxide interface. In addition, hole current around the gate induces EMI noise due to the negative gate capacitance. This article shows that the proposed surface buffer (SB) IGBT suppresses dynamic avalanche and negative gate capacitance maintaining low power loss by covering the trench gate bottom and hole evacuation from the pMOS channel.

DOI： 10.1109/TED.2020.2999874

Language：English   Publishing type：Research paper (scientific journal)  

A new gate structure in the trench-gate insulated-gate bipolar transistor (IGBT) design is proposed and analyzed for power-loss reduction and the suppression of electromagnetic-interference (EMI) noise. Although the turn-off loss and the ON-state voltage drop V-ce(sat) are improved by the injection-enhancement (IE) effect, the IE effect caused dynamic avalanche that limits the turn-off loss reduction. In addition, EMI noise is induced by high dI/dt and large surge current due to the negative gate capacitance. This article shows that the dynamic avalanche and the negative gate capacitance can be suppressed by the management of the electric field concentration and hole current flow around the trench gate by the proposed alternated trench-gate (AT) IGBT structure, and both low power loss and good switching controllability can be obtained. The device simulation results show that the AT-IGBT improves the turn-on surge current I-surge - V-ce(sat) tradeoff compared with the conventional IGBTs.

DOI： 10.1109/TED.2020.3002510

Language：English   Publishing type：Research paper (scientific journal)  

A new structure in trench-gate insulated gate bipolar transistor (IGBT) design is proposed and analyzed not only for power loss reduction but also for long-term stability and suppressing electromagnetic interference (EMI) noise using a device simulation. Although turn-off loss and ON-state voltage drop {V}_{ ext {ce(sat) } } are improved by injection enhancement (IE) effect, IE effect causes dynamic avalanche that limits turn-off loss reduction and degrades long-term stability by the charge trap at the trench gate oxide interface. In addition, hole current around the gate induces EMI noise due to the negative gate capacitance. This article shows that the proposed surface buffer (SB) IGBT suppresses dynamic avalanche and negative gate capacitance maintaining low power loss by covering the trench gate bottom and hole evacuation from the pMOS channel.

DOI： 10.1109/TED.2020.2999874

Language：English   Publishing type：Research paper (scientific journal)  

Assist Gate (AG) MOSFET is proposed for low power loss operation of low-voltage power MOSFETs by a new structure with the optimum gate control. The second channel and accumulation layer reduce the channel and drift resistances. In addition, the gate control of AG-MOSFET decreases turn-off loss. 40 and 100 V-class AG-MOSFET characteristics were analyzed using TCAD simulation. The AG-MOSFET improves on-resistance and turn-off loss trade-off. The simulation results show 34&#37; lower on-resistance with 16&#37; lower turn-off loss for 40 V-class device and 21&#37; lower on-resistance with 10&#37; lower turn-off loss for 100 V-class device.

DOI： 10.1109/LED.2020.2991927

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/LED.2020.3000239

Language：English   Publishing type：Research paper (scientific journal)  

The on-resistance limit of 100 V-class Field-Plate (FP) trench power MOSFETs was analyzed by TCAD simulation. In the previous works, the lateral pitch narrowing effect to reduce the on-resistance has been studied from the viewpoint of charge compensate concept. This work focused on optimization of FP oxide thickness, which affects both the breakdown voltage and the stress induced electron mobility enhancement. The simulation results show that thin oxide structure is desired for low on-resistance design due to lateral pitch narrowing, although thick oxide enhances the increase of the electron mobility. However, the on-resistance reduction by lateral pitch narrowing is limited by increase of the drift layer thickness for maintain the breakdown voltage. As a limit value, the on-resistance of 24.7mOmm² at the breakdown voltage of 114 V was estimated and corresponds to 13&#37;-24&#37; improvement of Figure-of-Merit, which is V_B^2.5/R_on, compared with the previous works of two step and multiple step oxide structures.

DOI： 10.1109/LED.2020.3000239

Language：English   Publishing type：Research paper (scientific journal)  

This paper discusses the edge termination design of high-voltage insulated gate bipolar transistors with large current turn-off switching operation. We discovered that the phenomena of current crowding and impact ionization act as separated heat sources and induce one local hot spot that causes thermal destruction in the edge termination during the turn-off switching period. Optimizing the backside hole injection efficiency and relaxing the electric field of the surface pn junction edge at the edge termination region prevent the above problems. These concepts benefit the dynamic ruggedness under hard-switching conditions. This paper presents our novel edge termination design that achieves robust turn-off capability without deteriorating other performances of the device.

DOI： 10.1016/j.microrel.2020.113635

Language：English   Publishing type：Research paper (international conference proceedings)  

High dV/dt controllability of IGBT is an important factor for flexible design as well as low switching loss in power electronics systems. However, Dynamic Avalanche (DA) phenomenon poses a fundamental limit on their dV/dt control range, operating current density, turn-off power loss as well as reliability. Overcoming this phenomenon is essential to ensure their safe operation and high robustness in emerging electric transport. In this work, detailed analysis of 1.2 kV trench gated IGBTs is undertaken through experiments and calibrated TCAD 3-dimensional simulations to show the fundamental cause of the low dV/dt controllability of conventional IGBTs and a method to achieve DA free design by Trench Clustered IGBT (TCIGBT). The potential of TCIGBT for ultra-high current density operation with high dV/dt controllability is also presented.

DOI： 10.1109/APEC39645.2020.9124293

Language：Others   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/TED.2020.2990387

Language：English   Publishing type：Research paper (scientific journal)  

In this article, we investigated the destructive behavior of the latest power diode when operating a hard-switching process. From the numerical simulation analysis, the destruction behavior originates in the enhanced impact ionization at the p-n junction on the anode side and current filament in the active region. A relaxing electric field on the anode side and a moderated electric field on the cathode side prevent the above-mentioned behavior. These improvements result from controlling the carrier-plasma layer in the n-buffer layer on the cathode side. This article demonstrates the effective n-buffer technology for the power diode that achieves superior dynamic robustness and high operating temperature over 448 K.

DOI： 10.1109/TED.2020.2990387

Language：English   Publishing type：Research paper (scientific journal)  

Vertical PNP bipolar transistor test structures were fabricated and measured, attempting to electrically obtain information on carrier lifetime in the voltage-supporting base region of Insulated Gate Bipolar Transistors (IGBTs). Owing to the structural similarity, the test structures and functional IGBTs can be integrated on the same wafers, making it possible to directly correlate lifetime data and IGBT characteristics. To solve a problem of leaky backside PN junction, common base current gain of the test devices was measured without applying a reverse bias between the collector and base terminals, which suppressed the leakage to an acceptable level. A simple analytical formula to convert the current gain to hole lifetime in the N-type base region was proposed and used, that takes into account the existence of a commonly used N-buffer layer adjacent to the backside P-collector layer. The validity of the formula was confirmed using TCAD simulations. This method was applied to IGBT wafers with two different wafer thicknesses (i.e., base lengths): 120~{ { mu } }text{m} and 360~{ { mu } }text{m}. Consistent lifetime values extracted in spite of the largely different thicknesses supports the validity of the proposed lifetime estimation method.

DOI： 10.1109/TSM.2020.2972369

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1016/j.jcrysgro.2020.125594

Language：English   Publishing type：Research paper (scientific journal)  

In this work, effects of structural parameter scaling on IGBT performance were systematically studied for both 1200 V non-scaled (k = 1) and scaled (k = 3) IGBTs. Relatively small area IGBT test devices with varied device parameters were fabricated on 3 inch wafers simultaneously with full size IGBTs. Mesa width, trench depth, p-base depth (MOS channel length) and gate oxide thickness were varied to clarify the contribution of each scaling parameter. P-collector dose was also varied for both k = 1 and k = 3 IGBTs to control the on-sate voltage. Clear on-state voltage improvement was verified in scaled IGBTs, in agreement with TCAD simulations. The origin of the performance improvement and the possibility of further improvement by scaling are discussed.

DOI： 10.35848/1347-4065/ab7414

Language：English   Publishing type：Research paper (international conference proceedings)  

This paper investigates a degradation of SiC power device for DC circuit breaker through repetitive unclamped inductive switching (UIS) tests. Being lower ON­resistance compared with Si devices, it has been considered an application for DC circuit breakers using SiC semiconductor. In order to use for the DC breaker, it is essential to evaluate the destructive endurance for UIS test. This paper evaluates a deterioration phenomenon by paying attention to the decrease of the gate voltage of the SiC­MOSFETs under the degradation at repetitive UIS test.

DOI： 10.4028/www.scientific.net/MSF.1004.1010

Language：English   Publishing type：Research paper (scientific journal)  

We conducted the transient global simulations for the crystal pulling process of Czochralski silicon (CZ-Si) growth with the cusp-shaped magnetic field (CMF). The generation, transport, and segregation of oxygen (O) were considered for the crystal growing process. Further, the incorporation, accumulation, and segregation of carbon (C) were also predicted based on our previous studies on CZ-Si growth. The distributions of O and C at the growth interface were dynamically predicted for the diameter pulling stages, and their segregations were plotted as a function of solidified fraction and crystal length. The O level and uniformities at the growth interface exhibit a strong correlation with the depth of melt in the crucible and the flow structures inside the melt. The comparisons of different CMFs indicated that adjustments of the zero-Gauss plane (ZGP) have the potential to optimize the O segregation into the pulling crystal from the level, axial, and radial uniformities. Further, the C concentration increased with the increase in the crystal length because of the continuous contamination and the lower segregation coefficient. Hence, the developed dynamic global model also has applications in the segregation prediction of other dopants and impurities in the CZ-Si growing process.

DOI： 10.1016/j.jcrysgro.2019.125404

Language：English   Publishing type：Research paper (scientific journal)  

A transient global model for the crystal pulling process was developed for magnetic-field-applied Czochralski silicon (CZ-Si) growth. Heat transfer by solid conduction, melt convection, and diffuse gray radiation is taken into account for the crystal, melt, and other components in the furnace. The mesh adaption and view factor updating for the dynamic pulling process were realized by the structured grid deformations for different domains. By imposing the thermal boundary conditions in the vicinity of the triple point, the inverse control by the virtual proportional integral derivative controller and heat flux is acceptable for the transient global simulation of the pulling process in CZ-Si crystal growth. The applied cusp-shaped magnetic field (CMF) suppressed the turbulent melt flow and stabilized the heat and mass transport. CMF with different zero-Gauss-plane locations resulted in different flow patterns, which could affect the impurity transport during the pulling process. This developed transient global model can be applied for the segregation predictions of impurities (oxygen and carbon) and dopants in the CZ-Si growing process.

DOI： 10.1016/j.jcrysgro.2019.125405

Language：English   Publishing type：Research paper (international conference proceedings)  

Dynamic Avalanche (DA) phenomenon poses a fundamental limit on the operating current density, turn-off power loss as well as reliability of MOS-bipolar devices. Overcoming this phenomenon is essential to ensure their safe operation in emerging electric transport. In this work, detailed analysis of 1.2 kV trench gated IGBTs are undertaken through experiments and calibrated TCAD simulations to show the fundamental cause of the DA as well as a method to achieve DA free design for ultra-high current density operation and reliability in 1.2 kV Si-IGBTs.

DOI： 10.1109/IEDM19573.2019.8993596

Language：English   Publishing type：Research paper (scientific journal)  

In this article, we investigated two typical destruction modes during reverse recovery in power diodes. These phenomena originated, while using numerical simulation analysis, in snap-off behavior and local heating during the recovery period in modern high-frequency power application. A relaxing electric field and optimizing electron injection efficiency at the cathode region prevent the above behavior. These improvements are the result of controlling the carrier plasma layer and its interaction with the electric field in the drift region during the recovery process. This article demonstrates the effective diode technology that achieves superior dynamic ruggedness with low overall loss.

DOI： 10.1109/TED.2019.2941710

Language：English   Publishing type：Research paper (international conference proceedings)  

In this work, the switching of 3300V IGBTs by 5V gate drive voltage has been successfully demonstrated for the first time. IGBT was designed based on a scaling principle. Comparing with conventional 15V-driven non-scaled IGBTs, the tum-off tail current of the scaled devices significantly decreased. The improvement of E-{mathrm{off } } vs V-{mathrm{cesat } } relationship by 35&#37; was achieved.

DOI： 10.1109/ASICON47005.2019.8983633

Language：English   Publishing type：Research paper (scientific journal)  

This paper investigates the degradation of SiC power devices for DC circuit breaker through repetitive unclamped inductive switching (UIS) tests. The ON resistance of SiC power devices such as MOSFET and JFET are lower compared with Si devices. Therefore, SiC power devices are suitable for use as DC circuit breakers. Several papers have discussed degradation of SiC power devices; however, few studies have determined a suitable power device for a DC breaker from a degradation standpoint. In this paper, four types of SiC devices were subjected to repetitive UIS tests. Our research demonstrated SiC-JFET to be suitable for a DC breaker.

DOI： 10.1016/j.microrel.2019.113417

Language：English  

In this study, effects of nitrogen and aluminium dopant on the SiC crystal structure and polytype stability were investigated by density functional theory. With taking account of the stacking energy of additional bilayer, the carbon terminated surface as seed surface with nitrogen doped condition is the only condition of 4H single polytype SiC growth. Under the other conditions, polytype conversion and inclusion might occurre.

DOI： 10.1016/j.jcrysgro.2019.04.018

Language：English   Publishing type：Research paper (scientific journal)  

GaN-based p-channel devices using a two-dimensional hole gas are of interest for the realization of GaN CMOS circuits, and threshold voltage control using a back-gate is useful for the circuit design of these devices. In this paper, the back-gate effect on p-channel GaN MOSFETs on polarization-junction substrates is studied. The results show that the obtained dependence of the threshold voltage on the back-gate voltage can be derived by a model equation considering the back surface channel. Also, by comparing the measured characteristics with the simulation result under ideal conditions, it is found that the amount of interfacial charges can be quantitatively evaluated for the fabricated device. (C) 2019 The Japan Society of Applied Physics

DOI： 10.7567/1347-4065/ab1c78

Language：English   Publishing type：Research paper (scientific journal)  

This paper presents a condition-monitoring method of dc-link capacitors used in a high-power three-phase PWM inverter with an evaluation circuit intended for ageing tests. Although its power rating is 1/25 of the inverter, the evaluation circuit provides the equivalent ripple current waveform and dc-bias voltage to the high-power inverter. The monitoring method independently extracts the capacitance and ESR of the dc-link capacitor, where the fast Fourier transform is introduced to the ripple current waveform and the dc-link voltage of the evaluation circuit. Experimental results verify that the monitoring method obtains both the ESR and capacitance changes of a capacitor under test.

DOI： 10.1541/ieejjia.8.480

Language：English   Publishing type：Research paper (other academic)  

TCAD simulation has been recognized as a powerful design tool for insulated gate bipolar transistors (IGBTs). In this work, excellent agreement between 3D TCAD simulations and experimental current-voltage characteristics were obtained in the up to 1000 A/cm(2) region for IGBTs with scaled trench-gates. The results of 2D and 3D simulations are compared to discuss the difference in current-voltage characteristics and their physical origins. A method to evaluate the saturation current (J(Csat)) using a 2D simulation is also presented with an appropriate correction.

DOI： 10.1109/ispsd.2019.8757640

Language：English   Publishing type：Research paper (other academic)  

In this work, 5V gate drive 3300V IGBTs, designed based on a scaling principle, have been demonstrated. Turn-off characteristics without noticeable degradation in the gate voltage waveforms were confirmed. Turn-off tail current of the scaled devices significantly decreased than conventional 15V-driven devices. As a result of both Vce and turn-off loss reduction, 35&#37; improvement in Eoff vs Vcesat relationship was achieved.

DOI： 10.1109/ispsd.2019.8757626

Language：English   Publishing type：Research paper (scientific journal)  

This study evaluates minority carrier lifetime in floating zone Si affected by advanced and conventional Si IGBT (insulated gate bipolar transistor) processes. Si gate oxidations reduce lifetime due to the formation of interface states between the Si and the oxide. As a result, cross-sectional photoluminescence imaging shows that the lifetime around a trench is lower than that in the bulk region. The high temperature thermal treatment for B-base/P-emitter layer activation after gate oxidation improved the interface, thus resulting in the recovery of the lifetime. TEM observations reveal that the (110) trench surface shows irregular contrast while the (100) surface shows relatively smooth contrast, which is consistent with the lifetime result of "trench side wall surface (100)" > "trench side wall surface (110)." Our study conclusively clarifies that lifetime is correlated with the SiO2 surface state. (C) 2019 The Japan Society of Applied Physics

DOI： 10.7567/1347-4065/aafd90

Language：English  

This study evaluates minority carrier lifetime in floating zone Si affected by advanced and conventional Si IGBT (insulated gate bipolar transistor) processes. Si gate oxidations reduce lifetime due to the formation of interface states between the Si and the oxide. As a result, cross-sectional photoluminescence imaging shows that the lifetime around a trench is lower than that in the bulk region. The high temperature thermal treatment for B-base/P-emitter layer activation after gate oxidation improved the interface, thus resulting in the recovery of the lifetime. TEM observations reveal that the (110) trench surface shows irregular contrast while the (100) surface shows relatively smooth contrast, which is consistent with the lifetime result of "trench side wall surface (100)" > "trench side wall surface (110)." Our study conclusively clarifies that lifetime is correlated with the SiO2 surface state. (C) 2019 The Japan Society of Applied Physics

DOI： 10.7567/1347-4065/aafd90

Language：English  

Vertical PNP bipolar transistor test structures were fabricated, which can be integrated on the same wafer with functional IGBTs. Common-base current gain was measured by applying zero voltage to the leaky back side junction, from which minority carrier lifetime in the base region was extracted. The structure makes it possible to measure the lifetime after a real IGBT fabrication process flow, and to correlate it with the characteristics of IGBTs on the same wafer.

DOI： 10.1109/ICMTS.2019.8730922

Language：English  

Power devices with high-performance require long carrier lifetimes within their silicon crystals. This paper reports the in-situ measurement of carbon monoxide in a Czochralski growth furnace of silicon single crystals. Moreover, this paper reports analytical investigation on contamination to silicon melt as functions of pressure in the furnace, argon gas flow velocity and gap width between the melt and a thermal shield. The experimental results show the carbon contamination to the melt increases when the pressure increases and the flow rate decreases. Increase of the gap width increases the contamination of carbon. We could explain the results qualitatively using a simple transport model.

DOI： 10.1016/j.jcrysgro.2018.11.017

Language：English  

Functional trench-gated 1200V-10A class Si-IGBTs, designed based on a three dimensional (3D) scaling concept, were fabricated, and 5V gate voltage switching operation has been demonstrated for the first time. 33&#37; reduction of turn-off loss and 100mV improvement of on-state voltage were achieved, while keeping 1.2kV forward blocking voltage.

DOI： 10.1109/IEDM.2018.8614491

Language：English   Publishing type：Research paper (international conference proceedings)  

Thermal management is essential to reliable design of power modules. In this report, a trend in the thermal resistance of power modules was examined by reviewing the current cooling technologies. The thermal resistance of power modules has decreased to approximately 1/3x in 10 years. Our numerical simulation about cooling suggests that a straightforward development in liquid cooling technology can achieve the update corresponds to the expected change in next 5 year when it keeps this trend in next decades. However, further progress in thermal resistance shall require higher thermal-conductive materials for spreader and two-phase cooling technologies.

Language：English  

A new methodology to evaluate the process temperature dependence of the minority carrier lifetime has been developed. A TEG layout with p+-stripes on an n-Si substrate was designed. When all the p+n junctions are made forward, the minority carrier diffusion current flows one dimensionally into the substrate. On the other hand, for making only the one center p+n junction forward, the current spreads laterally and flows cylindrically into the substrate. By the difference in the flow path of the minority carrier diffusion, we can successfully extract the minority carrier lifetime. We applied this methodology to the evaluation of the minority carrier lifetime depending on process temperatures and confirmed the lifetime degradation for high temperature process.

DOI： 10.1109/VLSIC.2018.8502399

Language：English  

The injection enhancement effect in IGBTs was experimentally verified by separately measuring emitter electron-and hole-currents for the first time. Finger contacts were employed as ladder-like periodic n+ and p+ emitters to allow the independent measurement of these currents. Both reducing the mesa width and increasing the cell pitch were found to increase electron injection from the emitter, demonstrating the injection enhancement effect. These experimental results agreed well with the simulation results.

DOI： 10.1109/ESSDERC.2018.8486870

Language：English  

Czochralski silicon (CZ-Si) crystal growth is invariably accompanied by the generation and transport of impurities, such as carbon (C) and oxygen (O), from chemical reactions in the high-temperature range. Reduction of C contamination in the grown crystal is required for the production of a high-quality Si wafer. Therefore, we systematically performed the transient global simulations and in situ measurements of CO concentrations in argon (Ar) gas domain. Parametric studies on the furnace pressure, flow rate of argon gas, and gap width were conducted for the transport of CO and accumulation of C during the melting process of Si feedstock. SiO etching reactions on graphite and SiC coating are the major sources of CO production. The contact reaction between the crucible and susceptor is an additional source of CO and SiO. Furthermore, the control mechanisms of gas flow on the incorporation of the generated CO and the accumulation of C in Si feedstock were clarified by comparison of different parameter settings. According to the mechanisms of C transport, the final C content of the melting process depends on the contamination flux at the gas/melt interface which could be controlled by the Péclet number of the gas flow and diffusion distance of CO.

DOI： 10.1016/j.jcrysgro.2018.07.020

Language：English  

Condition monitoring plays an important role in estimating health condition of capacitors because the ageing of the capacitors is usually accompanied by an increase in equivalent series resistance (ESR) and a decrease in capacitance. Either capacitance or ESR cannot be a unique indicator of the lifetime of capacitors in some cases. This paper presents a condition monitoring method of a dc-link capacitor used in a three-phase PWM inverter with a front-end diode rectifier intended for motor drives. The monitoring method extracts both the ESR and capacitance of a capacitor under test from the actual ripple current and voltage without disconnecting the capacitor nor injecting an additional current. The monitoring method, therefore, can be implemented online. Experimental results verify that the monitoring method independently obtains the ESR and capacitance changes of the capacitor under test. This contributes to accurate lifetime estimation of dc-link capacitors.

DOI： 10.1016/j.microrel.2018.07.023

Language：English  

High-performance electronics require long carrier lifetimes within their silicon crystals. This paper reports the effects of thermal donors on the lifetimes of carriers in as-grown n-type silicon crystals grown by the Czochralski method. We grew silicon crystals with two different concentrations of thermal donors using the following two cooling processes: one was cooled with a 4-h halt after detaching the crystal from the melt, and the other was cooled continuously. The crystal grown with the cooling halt contained higher concentrations of thermal donors of the order of 1 × 10¹³ cm⁻³, while the crystal without the halt had no thermal donors. The measured bulk lifetimes were in the range of 15–18 ms. We concluded that thermal donors in Czochralski-grown silicon crystals do not act to reduce their lifetimes.

DOI： 10.1016/j.jcrysgro.2018.02.034

Language：English   Publishing type：Research paper (other academic)  

This paper presents a condition monitoring method of dc-link capacitors used in a high-power three-phase PWM inverter intended for load life testing with an evaluation circuit consisting a low-voltage inverter. The evaluation circuit provides the equivalent ripple current waveform and dc-bias voltage to those of the high-power inverter. Hence, the monitoring method allows the load life testing with the equivalent condition to the high-power inverter at low cost. Experimental results verify that the monitoring method extracts both the ESR and capacitance changes of a capacitor under test.

Language：English   Publishing type：Research paper (scientific journal)  

Gallium nitride (GaN)-based P-channel (Pch) and N-channel (Nch) metal-oxide-semiconductor field-effect transistors (MOSFETs) with normally off operations were realised. Both Pch and Nch MOSFETs were monolithically fabricated in a polarisation-junction platform wafer. The platform wafer was constructed with a GaN/aluminium GaN/GaN double heterostructure, which has both two-dimensional hole gas (2DHG) and 2D electron gas (2DEG). The drain currents of Pch and Nch MOSFETs flow through 2DHG and 2DEG, respectively. The threshold gate voltages of the fabricated Pch and Nch MOSFETs were -2.7 and 6.7 V, respectively. It was shown that the threshold voltage and the on-state resistance of the Pch MOSFET can be controlled by adjusting the 2DEG potential. Furthermore, using Pch and Nch MOSFETs, complementary MOS inverter operation was demonstrated.

DOI： 10.1049/iet-pel.2017.0376

Language：English  

Attention has been paid to reliability-related issues for dc-link capacitors such as monitoring methods, power-loss estimation, and ageing tests. The degradation of the capacitors depends on their operating condition including temperature, ripple current, and dc-bias voltage, which has a strong influence on failures as well. In design stages of power converters, it is desirable to know the relation between the degradation and electrolytic parameters. This paper makes an intensive discussion on the voltage dependence of the degradation of a small aluminum electrolytic capacitor with an ageing test and a leakage-current measurement. The ageing test reveals that a higher dc-bias voltage brings a faster increase in ESR but results in a slower drop in capacitance in a range within the rated voltage. This result implies that either capacitance or ESR cannot be a unique indicator of the lifetime. Attention should be paid both to the ESR and to the capacitance when one monitors the capacitor condition. On the other hand, more than the rated voltage leads a rapid degradation of the capacitor, which can be confirmed by a leakage-current measurement instead of the ageing test.

DOI： 10.1016/j.microrel.2018.02.012

Language：English  

This paper aims to clarify the effect of carbon concentration on carrier lifetime in as-grown n-type and non-doped silicon crystals produced via the Czochralski (CZ) method. We grew n-type and non-doped silicon single crystals with 3-in. diameters along with different carbon and phosphorous contents. The resistivity, concentrations of oxygen and carbon, and lifetime were measured using four-point measurements, Fourier-transform infrared spectroscopy, and the eddy current method, respectively. The oxygen concentrations of the crystals were 6–8 × 10¹⁷ atoms/cm³, and the bulk lifetimes ranged from 10 to 20 ms. The carrier lifetime of CZ silicon crystals depended on dopant concentration but had no significant dependence on carbon concentration.

DOI： 10.1016/j.jcrysgro.2018.01.020

Language：English   Publishing type：Research paper (other academic)  

Three dimensionally (3D) scaled IGBTs that have a scaling factor of 3 (k=3) with respect to current commercial products (k=1) were fabricated for the first time. The scaling was applied to the lateral and vertical dimensions as well as the gate voltage. A significant decrease in ON resistance, - V_ce(sat) reduction from 1.70 to 1.26 V - was experimentally confirmed for the 3D scaled IGBTs.

DOI： 10.1109/ASICON.2017.8252681

Language：English  

High-power conversion systems are based not only on three-phase inverters but also on singlephase inverters because modular multilevel cascade converters (MMCC) consist of half- or fullbridge single-phase converters. Their DC-link capacitors are a major constraint on the improvement of power density as well as of reliability. Evaluation of dc-link capacitors in terms of power loss, ageing, and failure rate will play an important role in the next-generation power converters. This paper presents an evaluation circuit for dc-link capacitors used in a high-power single-phase PWM inverter. The evaluation circuit produces a practical ripple current waveform and a dc bias voltage into a capacitor under test with a downscaled voltage-rating inverter, which is equivalent to those of the full-scale inverter. Theoretical analysis and experimental results verify the effectiveness of the evaluation circuit.

DOI： 10.1109/SBMicro.2017.7990846

Language：English  

Experimental verification of a 3D scaling principle for low V_ce(sat) IGBT
Three dimensionally (3D) scaled IGBTs that have a scaling factor of 3 (k=3) with respect to current commercial products (k=1) were fabricated for the first time. The scaling was applied to the lateral and vertical dimensions as well as the gate voltage. A significant decrease in ON resistance, - Vce(sat) reduction from 1.70 to 1.26 V - was experimentally confirmed for the 3D scaled IGBTs.

DOI： 10.1109/IEDM.2016.7838390

Language：English  

DC-link capacitors are a major factor of degrading reliability of power electric converters because they usually have a shorter lifetime and higher failure rate than those of semiconductor devices or magnetic devices. Characteristics of the capacitors are usually evaluated by a single sinusoidal current waveform. However, actual current flowing out of the converter into the capacitor is a modulated square current waveform. This paper provides experimental comparison of the power loss dissipated in an aluminum electrolytic capacitor between sinusoidal and square-wave current injections. Power loss is estimated by temperature rise of the capacitor. Experimental results confirm that power losses of the square-wave current injection were always lower than those of the sinusoidal current injection by 10–20&#37;. Moreover, the power losses of the square-wave current injection can be estimated by a synthesis of fundamental and harmonic currents based on the Fourier series expansion, which brings a high accuracy less than 1&#37; when more than fifth harmonic current is introduced. This comparison will be useful for estimating power loss and life time of electrolytic capacitors.

DOI： 10.1016/j.microrel.2016.07.049

Language：English  

DC-link capacitors in power electronic converters are a major constraint on improvement of power density as well as reliability. Evaluation of the dc-link capacitors in terms of power loss, ageing, and failure rate will play an important role in design stages of the next-generation power converters. This paper proposes a new evaluation circuit for dc-link capacitors used in a high-power three-phase inverter, which is intended for testing power loss, failure rate, ageing, and so on. The evaluation circuit produces a practical ripple current waveform and a dc bias voltage into a capacitor under test, in which the ripple current is equivalent to that generated by the three-phase inverter on the dc link. The evaluation circuit employs a full-scale current-rating and downscaled voltage-rating inverter for producing the ripple current, so that the power rating of the evaluation circuit is much smaller than that of a full-scale current rating and full-scale voltage rating inverter.

DOI： 10.1109/APEC.2016.7468295

Language：English  

A total pressure-controlled physical vapor transport growth method that stabilizes SiC polytype is proposed. The supersaturation of carbon during SiC growth changed as a function of the growth time due to changes in the temperature difference between the surfaces of the source and the grown crystal. Supersaturation also varied as a function of the pressure inside the furnace. Therefore, modification of the pressure as a function of growth time allowed for constant supersaturation during growth. The supersaturation was calculated based on classical thermodynamic nucleation theory using data for heat and species of Si₂C and SiC₂ transfer in a furnace obtained from a global model. Based on this analysis, a method for polytype-stabilized SiC growth was proposed that involves decreasing the pressure as a function of growth time. The 4H-SiC prepared using this pressure-controlled method was more stable than that of 4H-SiC formed using the conventional constant-pressure method.

DOI： 10.1002/crat.201500344

Language：English  

Design and Analysis of a New Evaluation Circuit for Capacitors Used in a High-Power Three-Phase Inverter
DC-link capacitors in power electronic converters are a major constraint on improvement of power density as well as reliability. Evaluation of the dc-link capacitors in terms of power loss, ageing, and failure rate will play an important role in design stages of the next-generation power converters. This paper proposes a new evaluation circuit for dc-link capacitors used in a high-power three-phase inverter, which is intended for testing power loss, failure rate, ageing, and so on. The evaluation circuit produces a practical ripple current waveform and a dc bias voltage into a capacitor under test, in which the ripple current is equivalent to that generated by the three-phase inverter on the dc link. The evaluation circuit employs a full-scale current-rating and downscaled voltage-rating inverter for producing the ripple current, so that the power rating of the evaluation circuit is much smaller than that of a full-scale current-rating and full-scale voltage-rating inverter. Theoretical analysis and simulated results verify the effectiveness of new evaluation circuit.

DOI： 10.1109/TIE.2015.2511097

Language：Japanese  

Experimental Verification of a New Evaluation Circuit for DC-link Capacitors Used in a Three-Phase Inverter

Language：English  

This paper gives an overview of GaN-based polarization-junction (PJ) technologies. PJ platform wafers have both high-density 2D hole gas (2DHG) and 2D electron gas (2DEG) respectively induced by negative and positive polarization charges in undoped GaN/AlGaN/GaN double heterostructures. On the platform, monolithic operations of GaN-based n-channel transistors and p-channel transistors have been demonstrated. Because of temperature independent properties of the 2DHG and 2DEG, the GaN devices can operate in wide temperature range. In addition, high voltage transistors and diode are also available on the platform by using polarization-superjunction concept.

DOI： 10.1109/CSICS.2015.7314489

Language：English  

We demonstrate fabrication a silicon on diamond structure at around room temperature using a plasma-activated bonding (PAB) method. Thin and flat silicon-dioxide (SiO₂) film was used as an activation layer for PAB. The SiO₂ film was prepared by a chemical vapor deposition and then a chemical mechanical polishing (CMP). The surface roughness after the CMP were average ∼1 nm rms at 300 nm thick. Thinning of the SiO₂ film was carried out using 2.5&#37;HF solution. We found that there are no significant change in the surface roughness after the thinning process. The roughness of SiO₂ less than or equal to 1 nm is required for success bonding at low-temperature with vacuum environment. The scanning electron microscope has shown seamless at the bonding interface that proves to good bonding result.

DOI： 10.1109/ECTC.2015.7159590

Language：English  

Polarization junction platforms have high-density 2D hole gas (2DHG) and 2D electron gas (2DEG) respectively induced by negative and positive polarization charges in undoped GaN/AlGaN/GaN double heterostructures. Sheet resistance measurements in a wide temperature range (6-460 K) revealed that 2DHG and 2DEG resistances were monotonically enhanced with the temperature reduction. On the platform, monolithic operations of GaN-based devices including high-voltage n-channel (N-ch) transistors, N-ch Schottky diodes, low-voltage N-ch transistors and p-channel transistors has been demonstrated.

DOI： 10.1109/ISPSD.2015.7123463

Language：English  

Theoretical Loss analysis of power converters with 1200 v class Si-IGBT and SiC-MOSFET
Power converter efficiencies of 1200-V class Si-IGBT/SiC-SBD hybrid pairs and a SiCMOSFET/ SiC-SBD pair were theoretically compared at a switching frequency above the limit of human hearing (20 kHz). Si-IGBT losses were simulated by TCAD. SiC device losses were calculated by analytical minimum loss models. Calculated efficiencies of the full-SiC pair were slightly higher than that of the hybrid pairs at conventional current densities less than 200 A/cm². At a higher current density of 400 A/cm², the hybrid pairs have a potential of high performance which is comparable with the full-SiC efficiency.

Language：English  

High-speed dicing of SiC wafers by femtosecond pulsed laser
A novel dicing technology that utilizes femtosecond pulsed lasers (FSPLs) is demonstrated as a high-speed and cost-effective dicing process for SiC wafers. The developed dicing process consists of cleavage groove formation on a SiC wafer surface by the FSPL, followed by chip separation by pressing a cleavage blade. The effective FSPL scan speed on the SiC surfaces was 33 mm/s. Kerf loss is negligible in the developed FSPL dicing process. In addition, the residual lattice strain in the FSPL-diced SiC chips was comparably small to that of the conventional mechanical process using diamond saws, due to the absence of the lattice heating effect in femtosecond-laser processes.

DOI： 10.4028/www.scientific.net/MSF.821-823.524

Language：English  

Erratum Impact of semiconductor on diamond structure for power supply on chip applications (Japanese Journal of Applied Physics (2014) 53 (04EP16))

DOI： 10.7567/JJAP.53.069202

Language：English   Publishing type：Research paper (other academic)  

In this paper, the novel normally-on type bidirectional switch, in which is comprised of SiC-JFET, SiC-SBD, and Si-IGBT is proposed for one of a protection method of the Matrix Converter (MC). When the MC becomes gate block situation, a diode clamp circuit or auxiliary circuits keeps inductive load current loop in a conventional MC utilized a bidirectional switch. We focus that the normally-on type SiC-JFET becomes turn-on state, when zero gate bias voltage and a SiC-devices have a good tolerance capability for short current than silicon devices.
These characteristic of normally-on type SiC-JFET is used to replace diode clamp circuit in MC driver system. The experimentation based on indirect MC induction motor driver system was carried out. The experimental result of IM driver shows that the proposed bidirectional switch can overcome a generated inductive load current by IM. Finally, in order to design heat sink, the power loss of each devices of proposed switch was estimated by experimental results.

DOI： 10.1109/IPEC.2014.6869568

Language：English   Publishing type：Research paper (scientific journal)  

The electrical properties of two-dimensional hole gases (2DHGs) in GaN/AlGaN/GaN double heterostructures were investigated. The layers were grown on sapphire substrates and a high-quality bulk GaN substrate. The coexistence of 2DHG and 2D electron gases on both sides of the AlGaN layer was confirmed by Hall effect measurements at 80-460 K. It was also verified that the 2DHGs were generated by negative polarization at the undoped GaN/AlGaN interface, which did not have a doped Mg acceptor. It was also demonstrated that the 2DHG density could be controlled by varying the AlGaN layer thickness and was inversely related to the 2DHG mobility. The measured relation indicated that the 2DHG mobility is mainly limited by phonon scatterings at around room temperature. As a result, the maximum 2DHG mobility of 16 cm/Vs at 300 K was achieved with a density of 1 × 10 cm^-2.

DOI： 10.1063/1.4872242

Language：English  

A bi-directional isolated DC/DC converter for medium-voltage applications have been discussed for the next-generation electrical grid, such as smart girds. To realize the DC/DC converter for installing on a power distribution system, it should be achieved higher-efficiency and lower-volume. Higher switching frequency enables to reduce the volume of the transformer. However, it is difficult to realize the both higher-efficiency and lower-volume of the DC/DC converter, because it could not operate higher frequency with high power devices such as medium-voltage IGBTs. This paper discusses switching losses and operation limitations for the actual medium-voltage isolated DC/DC converter, in the case of using Si-IGBT. In addition, the experimental system rated at 2.5 kV, 200 kW, and 5kH of the DC/DC converter with a medium-frequency transformer is designed, and the experimental results are shown.

DOI： 10.1109/IPEC.2014.6869671

Language：English  

The effect of nitrogen and aluminum as doped impurities on the stability of SiC polytypes (C- or Si-face 4H and 6H substrates) formed by physical vapor transport (PVT) was investigated. The stability of the polytypes was analyzed using classical thermodynamic nucleation theory with numerical results obtained from a global model including heat, mass and species transfer in a PVT furnace. The results reveal that the formation of 4H-SiC was more stable than that of 6H-SiC when a grown crystal was doped with nitrogen using C-face 4H- and 6H-SiC as seed crystals. In contrast, formation of 6H-SiC was favored over 4H-SiC when Si-face 4H- and 6H-SiC seed crystals were used. Meanwhile, the formation of 4H-SiC was more stable than that of 6H-SiC when aluminum was the dopant and C- and Si-faces of 6H-SiC were used as seed crystals. Formation of 6H-SiC occurred over that of 4H-SiC in the cases of C- and Si-faces of 4H-SiC as seed crystals.

DOI： 10.1016/j.jcrysgro.2013.03.036

Language：English  

Impact of semiconductor on diamond structure for power supply on chip applications
In this study, we assessed a semiconductor (silicon or GaN)-on-diamond (SeOD) structure and compared it with a conventional silicon on insulator (SOI) structure, i.e., diamond, for power-supply-on-chip (power-SoC) applications by numerical simulations. The SeOD structure has thermal advantages over the conventional SOI structure without degrading electrical characteristics even using a thin diamond film (0.3 μm).

DOI： 10.7567/JJAP.53.04EP16

Language：English  

Raman intensity profiles are measured for 10H-SiC crystals, for which various zone-folded phonon modes are observed. Raman intensity profiles are calculated based on a bond polarizability model assuming several stacking sequences for the 10H polytype using a linear chain model. Among several candidates for the stacking sequences, the 3322 stacking structure provides the best-fit profile for experimental spectral profiles. The hexagonality value of 0.4 predicted from the stacking sequence of this polytype is consistent with that derived from the frequency splitting between the experimental A₁ and E-type transverse optical modes. This fact is consistent with an empirical rule that the value of the reduced wavevector for the strongest folded transverse acoustic and optical modes are equal to the hexagonality of the polytype. In the present analysis of the Raman intensity profiles, the calculated intensity profiles for specified folded transverse optical modes are found to be relatively strong and strikingly dependent on force-field parameters in α-SiC that consists of the mixture of the cubic and hexagonal stacking structures. These force-field parameters can reproduce well the experimental Raman intensity profiles of various SiC polytypes including 10H-SiC.

DOI： 10.1063/1.4828996

Language：English   Publishing type：Research paper (other academic)  

Possibility of a 10 kHz switching frequency operation of a 4.5kV-400A SiC-PiN diode and Si-IEGT hybrid pair module has been investigated to drastically increase the switching frequency of medium-voltage power converters. For this purpose, the relation among the minimum pulsed width of the PWM signal, the modulation index, and the maximum switching frequency is analyzed based on the switching characteristics of the hybrid pair module. The analyzed data show that the 10 kHz switching frequency could be available with the hybrid pair module. © 2013 IEEE.

DOI： 10.1109/ECCE.2013.6646893

Language：English   Publishing type：Research paper (other academic)  

The maximum switching frequency of a 4.5 kV-400 A SiC-PiN diode and Si-IEGT hybrid pair module has been analyzed from the viewpoints of cooling capacity of the hybrid pair module and the minimum pulse width of the PWM signal. In the developed hybrid pair module, a direct water cooling type heat sink is employed to enhance the cooling capacity. It found that the developed 4.5 kV-400 A hybrid pair module could be operate at 10 kHz PWM switching frequency with the peak current of 110 A and the dc voltage of 2.5 kV. In this operating condition, the power losses of the Si-IEGT and SiC-PiN diode in the hybrid pair module are 2380W and 100 W, respectively.

Language：English   Publishing type：Research paper (scientific journal)  

The electrical properties at the GaN(0001)/AlGaN(0001) heterointerface have been investigated. Capacitance-voltage measurement and theoretical simulation results verify the existence of a two-dimensional (2D) hole gas, which is highly confined to the GaN/AlGaN interface with a peak carrier density of over 10 ¹⁹ cm^-3. Hall-effect measurements in the 80-460 K temperature range reveal that the 2D hole gas has zero activation energy and positive sheet-resistance temperature coefficients.

DOI： 10.7567/APEX.6.091002

Language：English   Publishing type：Research paper (other academic)  

Electrical properties of two-dimensional hole gas (2DHG) at GaN/Al0.23Ga0.77N heterointerface have been investigated. Existence of 2DHG at the interface is confirmed by capacitance-voltage and Hall Effect measurement. We have discussed transport mechanism of 2DHG by comparison with hole generated by conventional Mg impurity, based on experimental evaluations by X-ray diffraction, transmission electron microscope, atomic force microscope, secondary ion mass spectroscopy, and temperature dependence Hall Effect measurements.

Language：English  

We present numerical simulations of the high temperature solution growth (HTSG) of silicon carbide (SiC) crystals. From a global simulation model, we investigate the influence of rotating magnetic fields (RMFs) and traveling magnetic fields (TMFs) on the crystal growth rate. The results reveal that heat and mass transfers are affected by magnetic fields. We show that direction of the solute flux must be controlled to increase the growth rate. For example, in presence of TMFs directed downwards the growth rate increases up to three times compared with the pure thermal HTSG. The proposed HTSG system coupled with magnetic fields has the same growth rate possibility as in the sublimation technique.

DOI： 10.1016/j.jcrysgro.2011.11.019

Language：English  

This study focuses on the epitaxial growth of silicon carbide (SiC) epitaxial layers, adopting the chloride-based chemical-vapor-deposition (CVD) process, which allows to achieve ten times higher growth rate compared to the standard process based on the mixture of a silicon-containing gas and a hydrocarbon. In order to improve the material quality, substrates with different off-angles were used, since low off-angle substrates result in a reduction of killer defects for specific devices. Different growth mechanisms dominate for different substrate off-cut and an accurate set up of dedicated surface preparation procedures and tuning of growth parameters are needed. This study demonstrates that silicon-rich gas inputs are favorable for lower off-angle (nominally on-axis) substrates, while carbon-rich are beneficial for higher off-angles (usually 8° off-axis for 4H-SiC). Methyltrichlorosilane (MTS) is shown to be the best precursor to achieve the presented results.

DOI： 10.1016/j.jcrysgro.2011.09.061

Language：English  

We investigated with ab initio calculations the energetics of the most common silicon carbide (SiC) polytypes. We considered the (0001) Si face and the (0001̄) C face of 3C-, 6H-, 4H- and 2H-SiC. Our investigation reveals that the energy differences among SiC polytypes are enhanced at the surface with respect to the bulk. We discuss the relevant role played by the surface for the crystal growth of SiC.

DOI： 10.1016/j.jcrysgro.2011.11.052

Language：Japanese  

Demonstration of 4kHz switching operation

Language：English   Publishing type：Research paper (other academic)  

A new 4.5 kV-400 A module using SiC-PiN diodes and Si-IEGTs hybrid pair has been developed. The hybrid pair module is designed to realize high-frequency switching operation of high power medium-voltage power converters (1-10MVA, voltage range 3... 10kV). In order to realize a low switching loss operation of the hybrid pair module, a hard gate driving with low gate resistor has been employed. Switching characteristics of the hybrid pair are evaluated experimentally and compared with that of a conventional 4.5 kV Si-IEGT and Si-PiN diode pair (All Si). The results show that the reverse recovery loss of diode and the turn-on loss of the Si-IEGT are reduced up to 95% and 60%, respectively. As a result, the total switching loss (i.e. turn-on and turn-off losses of the Si-IEGT plus reverse recovery loss of the diode) can be reduced up to 49% with the hybrid pair. The developed hybrid pair modules are applied to a prototype high power converter, and a high-frequency switching operation of 4 kHz has been successfully demonstrated.

Language：Japanese  

Numerical Predictions of a Novel SOI Substrate for Power Supply on Chip Applications Using Thin Diamond Film as an Insulator

Language：English  

We studied dependence of process parameters, such as temperature of a seed, pressure in a furnace and surface polarity of a substrate, on polytypes of SiC in a process of physical vapor transport. The analysis was based on a classical thermodynamic nucleation theory in conjunction with numerical results obtained from a global model. We investigated which polytype was more stable in the nucleation stage by a comparison of nucleation energies of each polytype. The results show that the formation of 4H-SiC was more stable than that of 6H-SiC when we used C-face SiC as a seed. Furthermore, the most stable polytype could change from 4H-SiC to 6H-SiC in a condition of higher supersaturation, with a condition of higher temperature of a seed and lower pressure in a furnace. Meanwhile, the formation of 6H-SiC was more stable than 4H-SiC when Si-face of a seed was used.

DOI： 10.1016/j.jcrysgro.2012.01.023

Language：English  

A study was conducted to demonstrate chloride-based chemical vapor deposition (CVD) growth of silicon carbide (SiC) for electronic applications. SiC homoepitaxial growth was done using CVD with silane (SiH ₄) as the silicon precursor and light hydrocarbons, including ethylene (C ₂H ₄) or propane (C ₃H ₈) as the carbon precursor. Simulation was an invaluable tool along with comparisons between different chlorinated chemistries to obtain a deeper understanding of the chloride-based process and provide more information. A number of approaches were selected to add chlorine to the gas mixture for the growth of SiC epitaxial layers using a chloride-based chemistry.

DOI： 10.1021/cr200257z

Language：English  

Kinetic calculations of the chemical phenomena occurring in the epitaxial growth of silicon carbide are performed in this study. The main process parameters analyzed are precursor types, growth temperature, Cl/Si ratio, and precursors' concentration. The analysis of the gas-phase reactions resulted in a model which could explain most of the already reported experimental results, performed in horizontal hot-wall reactors. The effect of using different carbon or silicon precursors is discussed, by comparing the gas-phase composition and the resulting C/Si ratio inside the hot reaction chamber. Chlorinated molecules with three chlorine atoms seem to be the most efficient and resulting in a uniform C/Si ratio along the susceptor coordinate. Further complexity in the process derives from the use of low temperatures, which affects not only the gas-phase composition but also the risk of gas-phase nucleation. The Cl/Si ratio is demonstrated to be crucial not only for the prevention of silicon clusters but also for the uniformity of the gas-phase composition.

DOI： 10.1021/cg201684e

Language：Japanese  

Design and Implementation of Non-Destructive Circuit of Si- and SiC-MOSFETs

Language：English  

Crystal growth of a certain polytype of SiC in a process of physical vapor transport was studied on the basis of classical thermodynamic nucleation theory in conjunction with numerical results obtained from a global model. Formation of a certain polytype in the nucleation stage is determined by the energy balance among surface energy, formation energy and supersaturation. The preferential growth condition of a certain polytype was estimated. The value of supersaturation was estimated using a numerical model obtained by a global model that includes species transport as well as heat transport in a furnace. The results of calculation showed that 4H polytype is more stable than 15R, 6H and 3C polytypes. Free energy difference between 4H and 6H polytypes decreased when total pressure in the furnace decreased.

DOI： 10.1016/j.jcrysgro.2011.03.059

Language：English  

Numerical investigation of the growth rate enhancement of SiC crystal growth from silicon melts
Numerical study has been applied to analyze the high temperature solution growth process for bulk silicon carbide (SiC) crystal growth. A twodimensional axisymmetric model for 2-in. SiC crystal growth was used for this study. The purpose of this paper is to investigate the possible approaches to enhance the growth rate in this process. In particular, we studied the effect of an AC magnetic field on the carbon transport to the crystal growth interface. The results revealed that the carbon flux to the growing crystal is strongly affected by the coil position and the applied frequency. If these two process parameters are properly chosen, we show that the carbon flux at the growing front, and thus the growth rate of SiC, can be enhanced.

DOI： 10.1143/JJAP.50.035603

Language：English  

We studied numerically the fluid dynamics of the silicon melt in the high temperature solution growth of silicon carbide (SiC) with the presence of alternative magnetic fields. A 2D-axisymmetric model for 2 in SiC crystal growth was used for this study. The results revealed that the melt convection is strongly affected by the coil position and the applied frequency. Results on the effect of electromagnetic convection in the presence of buoyancy convection are also given in this paper.

DOI： 10.1016/j.jcrysgro.2010.10.022

Language：English  

A fully coupled compressible multi-phase flow solver was developed to effectively design a large furnace for producing large-size SiC crystals. Compressible effect, convection and buoyancy effects, flow coupling between argon gas and species, and the Stefan effect are included. A small and experimental furnace is used to validate the solver. First, the essentiality of 2D flow calculation and the significance of incorporating buoyancy effect and gas convection, the Stefan effect, and flow interaction between argon gas and species were investigated by numerical results. Then the effects of argon gas on deposition rate, growth rate, graphitization on the powder source, and supersaturation and stoichiometry on the seed were analyzed. Finally, the advantages of an extra chamber design were explained, and improvement of growth rate was validated by the present solver.

DOI： 10.1016/j.jcrysgro.2010.08.032

Language：English  

A new SiC growth system using the dual-directional sublimation method was investigated in this study. Induction heating and thermal conditions were computed and analyzed by using a global simulation model, and then the values of growth rate and shear stress in a growing crystal were calculated and compared with those in a conventional system. The results showed that the growth rate of SiC single crystals can be increased by twofold by using the dual-directional sublimation method with little increase in electrical power consumption and that thermal stresses can be reduced due to no constraint of the crucible lid and low temperature gradient in crystals.

DOI： 10.1016/j.jcrysgro.2010.02.027

Language：English   Publishing type：Research paper (other academic)  

Previous Simulation works and experiments oil the loss of 4H-SiC floating junction Schottky barrier diodes (Super-SBDs) show that the loss is related to the doping concentration in the drift region and the pattern of the floating layer. The effect of the doping concentration for lowering the loss is characterized the breakdown voltage (V-bd) and the on-state resistances (RonS) of the Super-SBDs based oil Baliga's figure of Merit (BFOM). Experimental devices with two doping concentrations in the drift region are fabricated to investigate the static characteristics: V-bd and RonS. The V-bd of the Super-SBDs is close to the simulation result, near 3000 V. However the tendency of the V-bd by the doping concentration is not similar to the Simulation result. And the RonS are about 3.22 m Omega cm(2) which is higher than that of Simulation result. The doping concentration optimized in this study does not show significant lowering loss and the design of the floating layer in the termination region affect the low-loss static characteristics of the Super-SBD. In addition, adopting PiN Structure with floating layer (Super-PiN) affects the low-loss dynamic characteristics, optimizing the doping concentration in the drift region. We conclude that the fabricated Super-SBDs with the floating layer in the termination region, the drift region with a doping concentration of 1.0x10(16) cm(-3) and mesa-shaped termination structure, have excellent V-bd of 2990 V which is almost same as that of simulation result and RonS of 3.22 m Omega cm(2).

DOI： 10.4028/www.scientific.net/MSF.615-617.655

Language：Japanese  

Language：English  

On the engineering point of view, it is important to develop a design technology of the furnace for SiC single crystal growth. In this point of view, the recent progress of modeling on both sublimation bulk growth and hot-wall epitaxy were presented. For the sublimation, the active control of grown crystal shape by modifying crucible geometry was demonstrated. The effect of nitrogen doping on the heat transfer in a growing crystal were also investigated. For the hot-wall epitaxy, growth rate, surface morphology, and doping concentration could be predicted qualitatively with taking account of the depositing surface conditions. Chlorine-containing system was supposed to provide more stable and uniform process than the common SiH₄-based system.

DOI： 10.1016/j.jcrysgro.2008.09.105

Language：English   Publishing type：Research paper (scientific journal)  

The C(000-1) face of 4H-SiC has a lot of advantages for the power device fabrication such as the highest oxidation ratio and a smooth surface. However, the DMOS type power MOSFETs on the C(000-1) face have not been realized because of the difficulty of epitaxial growth and of high quality MOS interface formation. We have systematically investigated the device fabrication techniques for power MOSFETs on the C(000-1) face, and succeeded with the IEMOS which have blocking voltage of 660V and an on-resistance of 1.8mΩcm² and excellent dynamic characteristics.

DOI： 10.4028/3-908453-11-9.907

Language：English   Publishing type：Research paper (other academic)  

Modeling and simulation of the SiC growth processes, Physical Vapor Transport (PVT), Chemical Vapor Deposition (CVD), are sufficiently mature to help building new process equipment or up-scaling old ones. It is possible (i) to simulate accurately temperature and deposition distributions, as well as doping (ii) to quantify the limiting phenomena, (iii) to understand the important role of different precursors in CVD and hydrogen additions in PVT. The first conclusion of this paper is the importance of the "effective" C/Si ratio during CVD epitaxy in hot-wall reactors and its capability to explain the doping concentrations. The second conclusion is the influence of the C/Si ratio in alternative bulk growth technique involving gas additions.

DOI： 10.4028/3-908453-11-9

Language：English  

We have applied the floating junction (FJ) structure, which has been confirmed to be effective in reducing the on-resistance of Si power devices, to SiC FJ Schottky barrier diodes (SiC Super-SBDs). Optimization of the device parameters, which are derived by making improvements in the device simulator, and development of the fabrication process have enabled realization of Super-SBDs with a breakdown voltage of 2700 V and a specific on-resistance of 2.57 mΩ · cm². These values correspond to the world record of 11.3 GW/cm² for Baliga's figure-of-merit (BFOM} = 4V_bd²/R_on-sp).

DOI： 10.1109/TED.2008.926666

Language：English   Publishing type：Research paper (scientific journal)  

We report SiC wafer polishing study to achieve high throughput with extremely flat, smooth and damageless surface. The polishing consists of three process, wafer grinding, lapping and chemical mechanical polishing (CMP), which are completed in shortest about 200 minutes in total for 2 inch wafer. Specimens of 4H- and 6H-SiC were provided from slicing single crystal as wafers oriented (0001) with 0 or 8 degrees offset angle toward to 〈1120〉. By the first grinding using a diamond whetstone wheel, we realized flat surface on the wafers with small TTV error of 1 μm in 15 minutes. After second process of lapping, the wafers were finished by CMP using colloidal silica slurry. AFM observation showed not only scratch-free surface but also atomic steps on the wafers after CMP. Rms marks extremely flat value of 0.08 nm in 10 μm square area.

Language：English   Publishing type：Research paper (scientific journal)  

The calculation for 4H-SiC floating junction Schottky barrier diodes (Super-SBDs) was carried out by device simulation and the optimized device structure was fabricated. The best characteristics of the Super-SBDs were breakdown voltage of 2700V and the specific on-resistance of 2.57mΩcm ². The world record of Bariga's Figure of Merit (BFOM) for SiC-SBD expressed by 4V_bd ²/R_on was improved to 11,354MW/cm².

Language：English   Publishing type：Research paper (scientific journal)  

Rapid thermal annealing (RTA) on areas with diameters as large as 2 in. at high temperatures using hybrid super-RTA (HSRTA) equipment is performed in this study. The HS-RTA equipment consists of an infrared annealing unit and an RF induction annealing unit for uniform annealing over a 2-in.-φ susceptor. As a result of annealing using the HS-RTA equipment, temperature is elevated from RT to a high temperature (1600-1800°C) for less than 1 min. Using aluminum (Al)-implanted silicon carbide (SiC) samples, the performance of the HS-RTA equipment is evaluated. For Al-implanted samples annealed at 1700°C, the sheet resistance distribution on the 2-in.-φ susceptor is 8.0&#37;.

DOI： 10.1143/JJAP.46.5342

Language：English  

Numerical simulation was applied to observe the phenomena inside a crucible in silicon carbide (SiC) sublimation growth. Numerical simulation results show that crystal quality as well as crystal shape strongly depends on the temperature distribution inside the crucible. Numerical simulation also suggested that it is important to reduce the residual stress in the crystal in order to avoid the generation of dislocations. From these results, SiC sublimation growth was controlled actively, and large and high quality SiC single crystal was grown.

DOI： 10.1016/j.jcrysgro.2006.12.022

Language：English  

Numerical simulation was carried out on SiC-CVD in a horizontal hot-wall reactor. The growth and doping features of both Si- and C-terminated surfaces were analyzed by changing the inlet source gas conditions. The role of conditions at the growing surface on the growth feature was investigated. It was identified that the conditions at the growing surface are good parameters to explain the growth feature.

DOI： 10.1016/j.jcrysgro.2006.12.018

Language：English  

Backscattering Raman spectra of SiC polytype crystals with SiC{0001} polar faces have been measured using deep ultraviolet (DUV), UV, and visible (VIS) excitation sources. We have found that for DUV excitation the intensity profiles of zone-folded modes differ markedly for Si and C faces. This Raman spectral feature is attributed to the presence of nonpropagating phonon modes confined in the near-surface region. It is concluded that the surface-bound phonon modes created with DUV photon field extend over a region a few hundred nanometers in depth, and that the displacements of the phonon modes are anisotropic in the direction of the polar axis. This surface-orientation-dependent Raman spectrum can be used to identify the surface polarity of SiC polytypes.

DOI： 10.1103/PhysRevB.75.115321

Language：English   Publishing type：Research paper (scientific journal)  

In this study, we report defect analysis in 4H-SiC crystals of high nitrogen doping grown by sublimation method, and we discuss key points for defect restraint. The growth was performed in two kinds of growth directions; c-axis and a-axis. In the c-axis grown crystal with carrier density greater than 1 × 10^-19cm^-3, defect propagation was confirmed in the vertical direction for a growth direction affected by the doping by x-ray topography. This phenomenon was not observed in the a-axis grown crystals. In sublimation growth, the quantity of impurities tends to increase as growth rate decreases. Therefore, in the c-axis growth of doped 4H-SiC bulk crystals, we have to be careful so that dopant does not increase too much without intention in grown layers with lower growth rate, for example at the beginning and end of the growth.

Language：English   Publishing type：Research paper (other academic)  

We perform rapid thermal annealing (RTA) on areas as large as 2-inch phi (diameter) at high temperature using the hybrid super RTA (HS-RTA) equipment. The HS-RTA equipment consists of an infrared annealing unit and a RF induction annealing unit in order to uniformly anneal over 2-inch phi susceptor. As a result of annealing by the HS-RTA equipment, the temperature is elevated from RT to peak temperature (similar to 1800 degrees C) for less than 1 min, remain stable at annealing temperature for 30s and falls from peak temperature to 1000 degrees C within less than 20s. The temperature distributions on a 2-inch phi susceptor are +/- 10 degrees C, +/- 33 degrees C and +/- 55 degrees C at 1565 degrees C, 1671 degrees C and 1752 degrees C, respectively. Phosphorus (P) ion implanted silicon carbide (SiC) samples are used to evaluate the performance of the HS-RTA equipment. The five implanted samples placed on the 2-inch phi susceptor are annealed for 30s at 1565 degrees C, 1671 degrees C and 1752 degrees C. The mean sheet resistances of the 5 samples annealed at 1565 degrees C, 1671 degrees C and 1752 degrees C are 92.6 Omega/square, 82.6 Omega/square and 75.5 Omega/square, respectively. The sheet resistance uniformities are 9.9%, 7.9% and 9.3%. The average roughness (R-a) is calculated from 10 mu m square Atomic Force Microscopy (AFM) image. R-a values of the samples annealed at 1565 degrees C, 1671 degrees C and 1752 degrees C are 2.399 nm, 2.408 nm and 3.282 nm, respectively.

DOI： 10.4028/www.scientific.net/MSF.527-529.803

Language：English   Publishing type：Research paper (other academic)  

4H-SiC floating junction Schottky barrier diodes (Super-SBDs) were fabricated. It was found that their properties are closest to the theoretical limitation, defined by the relationship between specific on-state resistance and breakdown voltage of 4H SiC-unipolar devices. They have a p-type floating layer designed as line-and-spacing. The specific on-state resistances of Super-SBDs with a few micrometers of spacing width were found to be nearly equal to those of conventional SBDs without p-type floating layer. The breakdown voltages of Super-SBDs were higher than those of conventional SBDs. Accordingly the properties of Super-SBDs have improved the trade-off between specific on-state resistance and breakdown voltage, and the highest value to date for Baliga's Figure of Merit (BFOM) has been obtained.

Language：English  

Modeling and simulation of the SiC epitaxial growth, and doping in a horizontal hot-wall reactor from common precursors (SiH₄; C ₃H₈ diluted in H₂ for growth; N₂ and Al(CH₃)₃ for n-type and p-type doping) are presented. The growth and doping features of SiC thin layers on both Si-terminated and C-terminated surfaces are analyzed as a function of various inlet source gas conditions, i.e., various C/Si ratios. The role of the actual surface mass fluxes of both Si-containing and C-containing species and their ratio is analyzed and compared to the inlet experimental parameters. It is demonstrated that the doping level resulting from lattice site competition effects can be quantified by the actual C/Si ratio calculated above the growing surface. Moreover, the surface morphology of the epitaxial layer is explained on the basis of the mass fluxes at the growing surface.

DOI： 10.1002/cvde.200606469

Language：Japanese  

In-situ X-ray topography and simulation for silicon carbide single crystal growth

Language：Japanese  

Report on 5th International Workshop on Modeling in Crystal Growth (IWMCG-5)(Opinion, Report and Essay)

DOI： 10.19009/jjacg.33.5_403

Language：English  

We have investigated polishing-induced surface damage in nitrogen-doped {0001} 4H-SiC crystals with silicon and carbon faces through deep ultraviolet Raman microspectroscopy. The structural and electrical properties of the damaged layers were characterized as a function of the abrasive particle size, using pure phonon modes and a longitudinal-optical-phonon plasmon coupled mode as monitor bands. The degree of damage decreased with the size. Although abrasive polishing with finer particles enables the long-range order of the lattice to almost fully recover, the carrier density remains partly reduced in the polished surface layers. The number of defects that induces a reduction in the free carrier density differs between the Si and C faces of 4H-SiC crystals.

DOI： 10.1149/1.2170546

Language：English  

A numerical simulation was carried out on SiC-CVD in a horizontal hot-wall reactor. In order to explain the effect of surface polarity, Si-face and C-face, the surface reaction model was improved. Then, the growth processes and doping features of both Si-face and C-face were analyzed. The role of conditions at growing surface, such as surface mass flux of both Si-containing and C-containing species, surface concentration of Si-containing and C-containing species and their ratio, is investigated. Then, the deposition and etching rates, and doping concentration are analyzed as the function of those parameters. In addition, surface morphology of growing epitaxial layer is also investigated in connection with growing surface condition.

DOI： 10.1016/j.mee.2005.10.033

Language：English   Publishing type：Research paper (scientific journal)  

In-situ analysis for SiC bulk single crystal growth was reported using vertical X-ray diffraction (XRD) system. A furnace for SiC sublimation growth combined with the XRD system which possessed three kinds of functions including topography, rocking curve measurement and crystal growth rate monitoring was developed. These functions could contribute as a powerful tool finding the optimum growth condition by dynamic observation in the crucible. The in-situ X-ray topography succeeded to capture dynamic elongation of defects and dislocation generated in the SiC growing crystals. The in-situ rocking curve measurement revealed appearance of mosaic structure in the SiC crystal grown with high growth rate. The in-situ growth rate monitoring also succeeded very precisely using the direct X-ray beam absorption. On the base of findings and facts obtained by the in-situ observations, the importance for the SiC growth was discussed.

Language：English  

In this study, we studied the effect of growth conditions on micropipe (MP) filling during 4H-SiC epitaxial growth. We found that an MP in an on-axis substrate was filled during epitaxial growth and that this MP was filled with a spiral growth. The MP filling on on-axis substrates had a high probability and was independent of growth conditions. On the other hand, the probability of MP filling of 8° off-axis substrates showed a strong dependence on the growth pressure and the growth rate. The probability of MP filling increased with decreasing growth pressure or increasing growth rate. The probability of MP filling of the C-face was higher than that of the Si-face. From a comparison of a numerical simulation and experimental results, we found that the concentration of Si species just above the substrate was a crucial factor for MP filling.

DOI： 10.1016/j.jcrysgro.2004.11.071

Language：English  

To explain the difference between SiC-CVD on the Si-face and C-face, a heterogeneous model was improved, in which the etching, growth and doping features of SiC-CVD in a horizontal hot-wall reactor were numerically analyzed. The improved model was able to explain the etching and growth features accurately. There was no difference between the Si- and C-face. In addition, we propose the surface C/Si ratio as the universal parameter of the SiC-CVD process. Concerning doping features, the improved model showed that nitrogen and aluminum doping incorporation could be explained by the site competition model, while taking into account the amount of surface silicon and surface carbon, respectively.

DOI： 10.1016/j.jcrysgro.2004.11.072

Language：Japanese  

SiC Bulk Single Crystal Growth by Modified-Lely Method

Language：English   Publishing type：Research paper (scientific journal)  

We succeeded in continuous growth of SiC single crystal by CPD (Chemical Particle Deposition) method with the spray dried ultra-fine particle precursor powder. By the introduction of the spray dried spherical powder, we could clarify the mechanism of SiC single crystal growth by CPD method, through the observation of the deformation and the transformation of the spherical precursor powder into the epitaxial SiC grown layer on the seed crystal surface. The SiC layer grown by this method showed promising crystal quality indicated by the rocking curve with FWHM of 70-80 arcsec.

Language：English   Publishing type：Research paper (scientific journal)  

We report 4H-SiC single crystal growth of 4inch in diameter and micropipe-free crystal growth. Large single crystals were grown along c-axis and enlarged from smaller (0001) seed crystals. We confirmed that the center part of grown crystals is different in defect elongation from the enlarged part by x-ray topography. Especially, micropipes (MP) and screw dislocations (SD) are converted to basal plane dislocations in the enlarged part. By using this phenomenon, we realized a high quality crystal in the enlarged part that has x-ray rocking curve FWHM as small as 10.6arcsec. We also confirmed the crystal did not have MP and SD in a region of about 1 inch in diameter using etch pits observation and synchrotron x-ray topography. We also report the long length growth along a-axis growth on a () seed crystal and succeeded in the MP-free crystal growth.

Language：English   Publishing type：Research paper (scientific journal)  

The numerical simulation and in-situ X-ray topography were applied to observe the phenomena inside a crucible. Numerical simulation pointed out that macroscopic grown crystal quality such as grown crystal shape strongly depends on the temperature distribution inside a crucible. In-situ X-ray topography revealed that when the defects were generated, and how the defects were propagated. Most of defects were generated at the initial growth stage. It is important to control the initial stage in order to obtain a high quality SiC single crystal. Numerical simulation also suggested that it is important reduce the residual stress in a grown crystal in order to avoid the dislocation occurrence. From these results based on numerical simulation and experiment, SiC sublimation growth was controlled actively, and the large and high quality SiC single crystal have been grown.

Language：English   Publishing type：Research paper (scientific journal)  

Using our own substrate growth and epitaxial growth techniques, we fabricated a 1.4 kV mesa-type 6H-SiC pn diode with an ideal avalanche breakdown and without forward degradation. The 6H-SiC substrates were grown on Lely crystals with no micropipes and only minimal defects. A pn junction was fabricated by chemical vapor deposition (CVD) with p⁺/n epitaxial films. We obtained 1.4 kV breakdown voltage, consistent with the ideal breakdown voltage calculated from the thickness (10μm) and doping concentration (2×10¹⁶cm^-3) of the drift layer. The application of 200 A/cm² current stress in the forward direction produced no degradation, which is often observed with pn diodes on normal commercial substrates.

Language：English   Publishing type：Research paper (scientific journal)  

We fabricated 4H-SiC vertical MOSFETs with contacts to the source, p-well and polycrystalline silicon (polysilicon) gate and these were simultaneously formed from a single material, using one deposition and a single contact annealing process. Typical specific contact resistances of 4.8×10 ^-5 Ωcm² for the n⁺ source region, 1.5×10^-6 Ωcm² for the gate polysilicon and 5.2×10^-4 Ωcm² for the p-well contact region were obtained using Al/Ni (Al∼6%) as the contact metal. Also, the static characteristics of the vertical MOSFETs indicated that the MOS interface can withstand an even higher temperature process such as that used in ohmic-contact formation.

Language：English   Publishing type：Research paper (scientific journal)  

In order to grow a high quality SiC bulk single crystal, it is important to moderate the residual stress in the grown crystal. The residual stress is affected by not only the temperature distribution, but also by the boundary conditions. In this study, firstly, the effect of the polycrystal and of the crucible walls on the stress distribution was numerically analyzed. The effect of the grown crystal shape on the residual stress was also analyzed and compared to the growth experiment. It is pointed out that in order to moderate the residual stress, it is necessary to take care not only of the temperature distribution but also of the boundary conditions.

Language：English  

A 1.4-kV mesa-type 6H-SiC p⁺-n diode with an ideal avalanche breakdown and without forward degradation was fabricated. The 6H-SiC substrates were grown on Lely crystals with no micropipes and only minimal defects. The 1.4-kV breakdown voltage, consistent with the ideal breakdown voltage calculated from the thickness and doping concentration of the drift layer was obtained.

DOI： 10.1063/1.1591062

Language：English  

Silicon carbide epitaxial layers were grown by liquid-phase epitaxy on 6H-SiC-modified Lely crystals containing a high density of micropipes (MP) and other defects. The geometrical configuration of the seed crystals inside the crucible during LPE was such that the epitaxial layer growth occurred simultaneously on both the faces of the seed crystals. Layers in the range of 20-30μm thickness were deposited on both the faces of the crystals. X-ray diffraction, optical and scanning electron microscopy analyses were carried out to investigate these layers. It was found that dislocation and MP density in the substrate after LPE growth has been significantly reduced. Several MP were observed to decompose into non-hollow core dislocations. The growth centre associated with MP reduces in size in general and shifts to new centres due to the decomposition of the MP. As a result these new centres dominate the growing surfaces in LPE and make the healed MP completely invisible.

DOI： 10.1016/S0022-0248(03)01177-1

Language：Japanese  

SiC Bulk Single Crystal Growth by Sublimation Method : Use of Numerical Simulation

Language：English  

Gallium nitride (GaN) initial nucleation kinetics by the influence of SiC(0 0 0 1)_Si surface structure has been investigated. The Ga induced √3×√3R30° and 3×3 surface reconstructions are found to be more efficacious for GaN growth. During the initial stage of GaN/4H-SiC(0 0 0 1)_Si growth by molecular-beam epitaxy, coherent polygon islands grow wide (∼40 nm) along the lateral directions. These coherent islands develop 2D growth through early coalescence as evidenced by the in situ reflection high-energy electron diffraction observation. The control of Ga-adatom migration and the adsorption of 1/3 and 1 monolayer (ML) of Ga-adatom govern the surface morphology of the GaN layers. The bulk surfaces of (1 × 1) and (2 × 1) introduces incoherent nuclei, resulting in a delay of GaN coalescence, exhibits rough growth front and poor surface morphology.

DOI： 10.1016/S0039-6028(03)00016-5

Language：English   Publishing type：Research paper (scientific journal)  

The Capacitance diaphragm gauge (CDG) is one of the most important vacuum gauges in low and middle vacuum ranges. The difference of temperature between the sensor head and the vacuum chamber gives a non-linear sensitivity of the gauge depending on the pressure due to thermal transpiration effect. Change in the sensitivity of about 4% between molecular flow regime and viscous flow regime is significant for metrological use of the gauge. In this study, by using a DSMC method, pressure distribution in the connecting tube of the gauge was obtained under the pressure range from molecular flow regime to viscous flow regime with taking account of temperature distribution along the connecting tube. It was in good agreement with the pressure dependence of sensitivity obtained by static expansion system experimentally. Furthermore, influence of gas-surface interaction on the thermal transpiration was also discussed.

Language：English   Publishing type：Research paper (scientific journal)  

The Capacitance diaphragm gauge is one of the most important vacuum gauges in low and middle vacuum ranges. The difference of temperature between the sensor head and the vacuum chamber gives a non-linear sensitivity of the gauge due to thermal transpiration effect. This sensitivity depends not only on pressure but also gas species. It is supposed that under the same condition of gas-surface interaction, the sensitivity should be normalized by mean free path independently of gas species. However, the sensitivity normalized by mean free path also depends on gas species. In this study, by using DSMC method, the influence of gas-surface interaction on thermal transpiration was analyzed. In case of random reflection model, the sensitivity has non-linearity and depends on mean free path. On the other hand, in case of a perfectly elastic reflection model, the sensitivity is constant regardless mean free path. In case of complex reflection that is composed of random and elastic reflections, as increasing the elastic reflection component, the sensitivity decreases from that of random reflection to elastic reflection.

Language：English  

Silicon carbide epitaxial layer growth was carried out on both Si- and C-faces of the 6H-SiC Acheson seed crystals by a technique similar to that used for the sublimation growth of bulk single crystals of this material. High-resolution XRD (HRXRD) measurements showed the single crystalline structure for these grown layers. RHEED patterns confirmed that the grown layers are of single crystalline nature having (n×n) surface reconstruction. Raman spectroscopy showed the same polytype for the grown layers as that of the seed crystals. Atomic force and optical microscopy revealed smooth, uniform and mirror like surfaces for the grown layers. Step flow growth mechanism was observed on both Si- and C-faces of the seed crystal. The grown layers show similar characteristic features as that observed for the SiC layers grown by other techniques such as liquid phase epitaxy (LPE) and chemical vapor deposition (CVD). The technique used is a simple, viable and new alternative for growing SiC epitaxial layers.

DOI： 10.1016/S0167-577X(02)00783-8

Language：English  

The capacitance diaphragm gauge (CDG) is one of the most important vacuum gauges in low and medium vacuum ranges. CDG has a non-linear sensitivity below 100Pa because of the temperature difference between the sensor head and the vacuum chamber, which is called thermal transpiration. This sensitivity depends on gas species and pressure. In this study, by using a direct simulation Monte Carlo (DSMC) method, pressure distribution in the connecting tube of the gauge was obtained under the pressure range from molecular flow regime to viscous flow regime (10^-2-10²Pa) taking account of the temperature distribution along the connecting tube. Furthermore, the pressure dependence of the sensitivity of the CDG was derived from the pressure difference between the hot and cold ends, and found to be in good agreement with the pressure dependence of sensitivity obtained by an empirical equation. The influence of gas-surface interaction on the thermal transpiration was also analyzed.

DOI： 10.1016/S0042-207X(02)00212-9

Language：Japanese  

SiC Bulk Single Crystal Growth by Sublimation Method and Its In-situ Observation(<Special Issue>Science and Technology in Crystal Growth)
Silicon carbide (SiC) is the most promising material for high power, high frequency and low loss device applications. In order to realize SiC devices, it is necessary to improve the grown crystal quality. SiC bulk single crystal is grown by sublimation method, inside a closed carbon crucible. Because of the black box process, the optimization of sublimation process is difficult. From this point view the in situ X ray topography system was developed to observe the phenomena inside a crucible during the growth. The numerical simulation was also applied. From these observations, the heat and mass transfer in a crucible was discussed involving in the macroscopic crystal quality, such as crystal diameter, growing surface shape, and also in the microscopic crystal quality such as defect generations.

DOI： 10.19009/jjacg.29.5_431

Language：English   Publishing type：Research paper (scientific journal)  

The micropipe termination by using a W or Pt thin film was demonstrated. A SiC single crystal was grown on the modified-Lely seed with W or Pt mask, by the sublimation method. The optical micrograph made it clear that a micropipe contained in seed crystal was terminated at the metal deposited interface. The effect of metal mask thickness on the termination efficiency was also studied.

Language：English   Publishing type：Research paper (scientific journal)  

The numerical simulation of SiC sublimation growth was carried out. On the results of flux control growth with innerguide tube, the tube controls the thermal field inside a growth cavity, and makes it possible to grow single crystal without obstacle polycrystal. It was also cleared that the grown crystal shape strongly depends on the temperature distribution inside a growth cavity. On the results of in-process etching, it was pointed out that defects occurrence can be suppressed by taking care of temperature distribution on the initial growing surface. These results show that by controlling the thermal field inside a growth cavity, it is possible to control the macro and micro crystal quality such as grown crystal shape and defects, respectively.

Language：English   Publishing type：Research paper (scientific journal)  

Microwave plasma chemical vapor deposition was performed aiming at low temperature homoepitaxial growth of 4H-SiC thin films. The growth rate of the deposited film depended strongly on the SiH₄ flow rate, and a smooth surface could not obtained at high SiH₄ flow rate. The surface morphology was also affected by the C/Si ratio. A high C/Si ratio was required to obtain smooth SiC films. Single crystalline 4H-SiC film growth has been achieved at a temperature as low as 970°C by growing under very high C/Si ratio (C/Si = 175) with a very low SiH₄ flow rate (0.004sccm).

Language：English   Publishing type：Research paper (scientific journal)  

High quality 6H-SiC single crystal was grown using the modified Lely method under pressure-controlled low-growth-rate conditions. The grown crystal contained no micropipes and its etch pit density was 4 × 10³ cm^-2. The presence of a Pendellösung fringe as revealed by section topography showed that the grown crystal was composed of a single domain. The relation between etch pits and defects is also discussed.

Language：English   Publishing type：Research paper (scientific journal)  

The effect of the geometrical parameters of the inner structure of the crucible on the sublimation growth of bulk SiC was investigated. It was found that the gap between the seed crystal and the guide-tube was the important parameter for the single crystal growth separated from polycrystal. The growth rate ratio of the single/poly crystal increased up to 4. The broadening angle of the single crystal was controlled in the range of 0-30° by changing the taper angle of the guide-tube. The crystal quality in the periphery was improved compared with the crystal grown without the guide-tube. The growth process was discussed considering the flux flow of the sublimation gas.

Language：English  

Dislocation constraint in the growth of SiC crystal by the modified Lely method was studied. In SiC single crystal growth, the dislocations and defects generally propagate from the seed crystal surface. However, when the etch back on the seed crystal surface in the sublimation process was performed prior to growth, defects and dislocations propagation in the interface between the seed crystal and the grown crystal were reasonably suppressed. The switchover from the etch back to the growth could be performed without changing the heating condition during the initial process. We noticed that the density of the hollow defects called as micropipes in the grown crystal were decreased to 1/10 compared to that of the seed crystal used. We consider the etch back process of the seed crystal is an effective method for constraining the defects in the SiC crystal growth.

Language：English  

We have investigated two types of inclusions. They were a dendrite and a transparent inclusion, which have been seldom reported. The dendrite consisted of carbon, titanium and vanadium except for silicon. It should be carbide of titanium and vanadium. The titanium and vanadium might be incorporated from the source. By using a high purity source, it is possible to prevent generation of the dendrite. The transparent inclusion was observed in the SiC bulk crystal even in the growth with the chemical treated SiC source powder. A remarkable feature of the transparent inclusion was to have a small empty core. It was considered that the core might be a trace of Si droplet caused by C/Si ratio fluctuation of sublimated gas. Therefore, the C/Si ratio during the growth should be stabilized to prevent generation of the transparent inclusions.

DOI： 10.4028/www.scientific.net/msf.389-393.75

Language：English  

Dislocation constraint in the growth of SiC crystal by the modified Lely method was studied. In SiC single crystal growth, the dislocations and defects generally propagate from the seed crystal surface. However, when the etch back on the seed crystal surface in the sublimation process was performed prior to growth, defects and dislocation propagation in the interface between the seed crystal and the grown crystal were suppressed reasonably. The switchover from the etch back to the growth could be performed without changing heating condition during the initial process. We noticed that the density of the hollow defects called as micropipes in the grown crystal were decreased to 1/10 compared to that of the seed crystal used. We consider the etch back process of the seed crystal as an effective method for constraining the defects in the SiC crystal growth.

DOI： 10.1016/S0022-0248(01)01578-0

Language：English   Publishing type：Research paper (scientific journal)  

Language：Japanese  

Numerical Analysis of Thermal Transpiration Effect of a Diaphragm Gauge

Language：English  

New crucible design for SiC single crystal growth by sublimation
SiC bulk single crystal growth by sublimation was investigated. A new crucible design, double-walled crucible, was proposed, and its effect was confirmed numerically and experimentally. On the point of heat transfer in a growth cavity, double-walled crucible is better than conventional crucible. With a double-walled crucible, temperature of seed and source surfaces could be kept constant with better uniformity than that with a conventional crucible. It was deduced that a crystal growth rate could be kept constant with flat surface. Furthermore, in case of a double walled crucible, crystal enlarged rapidly with less inclusion. As the results, a double-walled crucible is useful to grow high quality SiC single crystal by sublimation.

Language：English   Publishing type：Research paper (scientific journal)  

The crystal growth of silicon carbide (SiC) was studied by in-situ observation using X-ray topographic technique. The growth was performed by a sublimation method (the modified Lely method). The generation and evolution of defects and dislocations were observed as topographs in a real-time display. Defects and dislocations analyzed by the in-situ technique were compared with the postprocess observations using optical microscopy and X-ray topography. Dislocations in the initial growth layer and typical large defects, such as micropipes, macrodefects and domain boundaries, were investigated. We showed the possibility that large defects are induced by the accumulation of dislocations in the initial growth layer. Moreover, we observed that inhomogeneous growth starting in parts on the seed surface during the initial growth results in new defects in the growing crystal. We discuss the importance of dislocation and nucleation control on the SiC seed crystal during the initial growth, on the basis of facts and findings obtained by the in-situ as well as postprocess observations.

DOI： 10.1016/S0022-0248(00)00958-1

Language：English   Publishing type：Research paper (scientific journal)  

Silicon carbide (SiC) single crystal growth was studied by the in-situ observation using x-ray topographic technique. Occurrence and dynamics of defects, dislocations were observed in a real time display and captured as topographic images during sublimation growth (modified Lely method) of SiC crystals. From the analysis of these topographic images, high-density of dislocations and typical large defects, such as micropipes, domain boundaries and macrodefects were investigated. On the basis of our in-situ observation and analysis, we argue that dislocation and nucleation control on the seed crystal during initial growth are of prime importance for producing high quality SiC crystals.

Language：English  

SiC epitaxial growth was carried out on 6H-SiC Acheson seed crystals in liquid phase using a closed carbon crucible. The growth was carried out in the temperature range of 1500-1700 °C. The geometrical configurations of seed crystals inside the crucible were specific, such that epitaxial layer growth occurred simultaneously on both faces of the same seed crystal under the same growth conditions. Growth rates as high as 20-30 μm/h have been achieved. The growth rate and surface morphologies observed after the growth indicated that the temperature gradient on the seed crystal faces plays a dominant role for the growth mechanism of the epitaxial layers. The convection within the solvent caused by the temperature gradient enhances the mass transport to the growing layer faces enhancing the growth rate and also results in a better surface morphology of the epitaxial grown layers.

DOI： 10.1016/S0022-0248(00)00733-8

Language：English   Publishing type：Research paper (scientific journal)  

Structural properties of beryllium implanted silicon carbide have been investigated by secondary ion mass spectrometry, Rutherford backscattering/channeling, and Raman spectroscopy. Strong redistribution of beryllium has been found after a post-implantation anneal step at temperatures between 1300 °C and 1700 °C. The use of a pre-anneal process at 1000 °C before the high-temperature treatment as well as graphite as a surface encapsulant do not efficiently suppress redistribution of Be in the SiC lattice. The crystalline state of the implanted and annealed material is well recovered after annealing at temperatures above 1400 °C.

Language：English   Publishing type：Research paper (scientific journal)  

Epitaxial growth of 6H-SiC was carried out on 6H-SiC Acheson seed crystals in the silicon melt using closed carbon crucible. The growth was carried out in the temperature range 1500-1700 °C. The geometry was specific one, such that epitaxial layer growth occurred simultaneously on both faces of seed crystal under similar growth conditions. We have measured the growth rate and studied the surface morphology of these grown layers. The temperature gradient within the melt seems to play a dominant role in the growth mechanism in liquid phase and also results in a better surface morphology of the grown layers.

Language：English   Publishing type：Research paper (scientific journal)  

Silicon carbide has been etched using a combination of high-dose ion implantation and wet chemical etching. Structural properties with respect to the remaining damage after etching have been studied using atomic force microscopy, Rutherford backscattering/channeling, and Raman spectroscopy. No significant deterioration of the crystal quality has been found after the etching process. Moreover, the as-etched surface is characterized by a lower roughness compared to virgin material. The results demonstrate that this etching method can be used for the fabrication of contacts on silicon carbide surfaces.

Language：English   Publishing type：Research paper (scientific journal)  

The growth rate of SiC bulk single crystal by sublimation was measured in real time by using the transmission X-ray technique. The growth rate obtained by transmission X-ray intensity corresponds to the growth rate measured by nitrogen marker. The growth rate increases as the growth temperature increases and as pressure decreases. While taking into account the pressure balance between the surrounding pressure and vapor pressures of seed and source, the growth rate can be calculated by mass flux from source to seed.

Language：English   Publishing type：Research paper (scientific journal)  

Numerical simulation of sublimation SiC bulk single crystal growth was performed. Electromagnetic and temperature fields in a growth furnace were analyzed numerically. The relation between grown crystal shape and temperature distribution in a growth cavity was discussed. It is pointed out that the crystal shape has a close relationship with temperature distribution. By modifying the crucible design and temperature distribution in a growth cavity, it is possible to enhance the enlargement of grown crystal, and also possible to keep grown surface flat.

Language：English   Publishing type：Research paper (scientific journal)  

The effect of growth pressure on the impurity incorporation as well as on the crystal quality was investigated in sublimation growth of a bulk SiC single crystal. The growth pressure was varied within the range of 1-100 Torr and it was found that many voids or precipitates were generated in the grown crystals and the Aluminum (Al) impurity incorporation increased during the Si-face growth when the growth pressure decreased. The pressure effect on the Al impurity incorporation with the change of step structure was discussed.

Language：English   Publishing type：Research paper (scientific journal)  

We investigated the rapid enlargement of SiC single crystal during physical vapor transport growth by enhancing the lateral growth. The degrees of enlargement of the single crystals grown on the newly developed graphite lid were larger than those of crystals grown on the conventional one. Using a cone-shaped platform, the polycrystals grown around the single crystal could assist the lateral growth of single crystal. There was no significant difference between the central region and the enlarged region as far as the micropipe density was considered. The dependence of the broadening angle (β) of the single crystal on the taper angle (θ) of the cone-shaped platform was also investigated and an optimum angle at a given growth condition was found.

Language：Japanese  

Development of Substrate Temperature Observation Equipment

Language：English  

Rapid enlargement of SiC single crystal using a cone-shaped platform
We investigated the enlargement of SiC single crystal during physical vapor transport growth by modifying the shape of graphite lid. The single crystals grown on the cone-shaped platform were larger in diameter than those grown on the conventional one. The enlargement of ingot is discussed in terms of the dual role of polycrystals during crystal growth: (i) it provides a platform for single crystal and (ii) an obstacle to the lateral growth of ingot. The dependence of the broadening angle (β) of single crystal on the taper angle (θ) of the cone-shaped platform was also investigated and an optimum angle at a given growth condition found.

DOI： 10.1016/S0022-0248(99)00754-X

Language：English  

We have developed an instrument for real-time observation of silicon carbide (SiC) crystal during the sublimation growth process by x-ray topography. It is constructed by combining an x-ray goniometer and a crystal-growth chamber. The vertical goniometer consists of three circles, an α circle for the x-ray source, a β circle for the detector, and a φ circle for the azimuthal rotation of the sample. The growing crystal boule is set at the center of the goniometer glued on a crucible lid. Transmission topographs are taken using an asymmetric (1011) reflection with the scattering angle 2 θ_B - β - α from the (0001)-oriented boule. A rotating-anode 18 kW generator with a molybdenum target is employed as the x-ray source. Topographs are observed by a direct imaging system using a charge-coupled device camera. Incident and scattered x-ray beams pass through beryllium windows mounted on the bottom and top flanges of the crystal-growth chamber, respectively. The crucibles are also designed for in situ measurements so that the x-ray beam path is separated from the source materials. The in situ topographs demonstrated the movement of micropipes and other defects during the crystal growth.

DOI： 10.1063/1.1150698

Language：English  

We have developed an instrument for in-situ X-ray topography during crystal growth of silicon carbide (SiC). A vertical X-ray goniometer is combined with a furnace for sublimation growth. A high-power X-ray source and a TV imaging system using a CCD camera make possible to display the behaviors of defects in SiC crystal inside crucible. For a demonstration of the developed instrument, we show the topographs of a SiC crystal at high temperature. The topographs show distinct deformations developing with increasing temperature.

Language：English  

We report here for the first time on the in-situ observations for SiC bulk single crystal growth by x-ray topographic technique. Occurrence and dynamic observation of the defects such as micropipes and domain boundaries during SiC crystal growth by the modified Lely method was investigated in a real time display. The in-situ observation was considered to contribute for optimizing the growth conditions and to interpret the mechanism of defects and dislocations formation.

Language：Japanese  

Language：Japanese  

Language：Japanese  

DOI： 10.1299/jsmemag.102.969_492_2

Language：English  

Defects in commercially available silicon carbide (SiC) wafers have been investigated by X-ray topography and optical microscopy. Dots appearing in transmission topographs are identified as a screw dislocation running through the [0001] direction by a comparative observation of the reflection topographs from the front and rear sides. In the peripheral region, these dots appear with high density and accompany large strain fields at the edge, which are related with the dislocations in the basal plane emanating from the dots and connecting them and large holes with diameters of about 10-20 μm opening at the epilayer surface. These large strain fields are considered to originate from the large Burgers vector associating with the screw dislocations.

Language：English  

X-ray topography system for in-situ observation of sublimation SiC single crystal growth has been developed. The feature of SiC single crystal growth inside a closed carbon crucible over 2200°C is captured in real time. The system will clarify the SiC growth mechanism, such as growth rate, defect generation and stress distribution in a growing crystal, depending on temperature, pressure and other parameters. These results will be useful to develop a high quality and large SiC single crystal wafer, and enhance the hard electronics technology.

Language：Japanese  

DOI： 10.1299/jsmemag.101.957_595_2

Language：English  

Temperature oscillation due to the oscillatory Marangoni flow was measured for a molten half-zone silicon column (10 mm high and 10 mm in diameter with a temperature difference of 150 K between the upper and lower solid-liquid interfaces) under microgravity by using fine thermocouples. The flow is in a hypercritical condition; that is, the Marangoni number is estimated to be over 10 000. The structure of the Marangoni instability is two-fold symmetry for the small aspect ratio (height/radius) Γ of 1 and one-fold symmetry for the melt with Γ of 2. The surface tension of molten silicon was measured by a sessile drop method in carefully controlled ambient atmospheres with various oxygen partial pressures from 4 × 10^-22 to 6 × 10^-19 MPa. These measurements showed that the surface tension and its temperature coefficient showed a marked dependence on oxygen partial pressure. Accordingly the effect of oxygen partial pressure on the Marangoni flow should be made clear. Moreover, Marangoni flow at the flat surface, which corresponds to the flow for the Czochralski growth system, should also be studied.

DOI： 10.1098/rsta.1998.0195

Language：English  

Temperature fluctuation measurements in a liquid bridge of molten silicon, which shows the Marangoni flow in highly super-critical condition, are performed in a half-zone configuration under microgravity on board a TR-IA-4 rocket and on the ground. In the microgravity experiment, two types of temperature oscillation are observed during the melting process of silicon and in the cylindrical half-zone melt. The former oscillation, which has a frequency of about 0.1 Hz during the melting process, has an antiphase correlation of temperature oscillation measured in thermocouples separated by 90° azimuthal angles. The latter oscillation in the cylindrical liquid bridge has no remarkable frequency; however, it tends to have the antiphase correlation in between thermocouples with 180° azimuthal angles. In the ground experiment, temperature fluctuations have a characteristic frequency of 0.2 Hz and there is an antiphase correlation of temperatures in thermocouples with 180° azimuthal angles by using the slender melt zone.

DOI： 10.1016/S0022-0248(97)00440-5

Language：Japanese  

DOI： 10.1299/jsmemag.100.945_868_2

Language：Japanese  

Simulation for Material Processing in Space
In space, it could be possible to make high quality, large and new functional materials. For the material processing such as melt growth of materilas for electrical devices and oxides, it is very important to understand and control the convective phenomena in melt. In this point of view, Marangoni convection in a liquid bridge which simulates the half floating zone was observed under microgravity conditions during parabolic filght. The experimental resutls was compared with that of numerical simulations. The developing processes of flow filed and temperature field were made clear. Furthermore, it coud be possible to estimate the pehnomena which might be happened as long time passed by numerical simulations. It means that numerical simulation is very usufel for developing the materila processing in space.

Language：Japanese  

3rd China-Japan Workshop on Microgravity Science

Language：English   Publishing type：Research paper (scientific journal)  

Oscillatory features of floating half zone convection were experimentally studied by using the drop shaft facility of Japan Microgravity Center which supported microgravity period of 10 s. Coordinated measurements including free surface deformation and oscillation, temperature and flow pattern in both 1-g and micro-g environment were obtained. The oscillatory frequency and amplitude in micro-g condition were lower and larger than the ones in 1-g condition, respectively. The results gave, at first time, the oscillatory features such as free surface wave in micro-g, coordinated measurements of more than two physical quantities in the micro-g, and transition of thermocapillary oscillatory convection from 1-g to micro-g.

DOI： 10.1016/S0017-9310(96)00309-2

Language：English  

The pure diffusion process has been often used to study the crystal growth of a binary alloy in the microgravity environment. In the present paper, a geometric parameter, the ratio of the maximum deviation distance of curved solidification and melting interfaces from the plane to the radius of the crystal rod, was adopted as a small parameter, and the analytical solution was obtained based on the perturbation theory. The radial segregation of a diffusion dominated process was obtained for cases of arbitrary Peclet number in a region of finite extension with both a curved solidification interface and a curved melting interface. Two types of boundary conditions at the melting interface were analyzed. Some special cases such as infinite extension in the longitudinal direction and special range of Peclet number were reduced from the general solution and discussed in detail.

DOI： 10.1016/S0022-0248(96)00386-7

Language：English  

Thermocapillary and Solutalcapillary Convection in Two Dimensional Open Cavity

Language：English   Publishing type：Research paper (scientific journal)  

Marangoni convection in a silicone oil liquid bridge under microgravity conditions during parabolic flight was observed. The developing process of axis-symmetric laminar Marangoni convection was studied experimentally and numerically. To reach a steady state of the temperature field, much more time was needed than to reach a steady state of the velocity field. The effects of initial temperature conditions inside a liquid bridge, heat transfer across the free surface, and temperature dependence of viscosity on both velocity and temperature field were studied numerically.

DOI： 10.1252/jcej.27.65

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1252/jcej.26.754

Language：English  

Momentum, with Heat and Mass Transfer Through Gas-Liquid Interface with Accelerated Interfacial Velocity
Effects of interfacial velocity on interfacial momentum, heat and mass transfer through a gas-liquid interface were quantitatively investigated. The rates of momentum, heat and mass transfer depend not only on the magnitude of the interfacial velocity but also on the change of acceleration in interfacial velocity. In addition, by considering the interfacial tension gradient to be the cause of interfacial acceleration, the effect of the interfacial tension gradient on interfacial velocity, interfacial momentum, heat and mass transfer were also quantitatively investigated. Both the interfacial velocity and the rates of momentum, heat and mass transfer depend not only on the magnitude of the interfacial tension gradient but also on the change of interfacial tension.

DOI： 10.1252/jcej.26.649

Language：English  

The effect of interfacial tension gradient on interphase momentum and mass transfer through a moving interface of single drops was studied theoretically. Approximate equations for interfacial velocity, drag coefficient and Sherwood number were proposed with taking account of the interfacial tension gradient. The results of this theoretical study showed good agreement with previous experimental results. (A)

Language：English  

The effect of interfacial velocity and interfacial tension gradient on momentum, heat and mass transfer through fluid-liquid interfaces was studied numerically. The effect of interfacial tension gradient on the interfacial velocity was clarified. The results obtained in this study can explain quantitatively the previous experimental results on the interfacial acceleration due to the interfacial tension gradient. Interfacial contamination and interfacial turbulent phenomena were respectively related to the enhancement and suppression of the mobility of interface. Effects of physical properties, bulk flow speed and Prandtl number on starting points of interfacial turbulence were also discussed.

Event date： 2019.3

Language：English   Presentation type：Symposium, workshop panel (public)  

Venue：Erding   Country：Guam  

Event date： 2018.11

Language：English   Presentation type：Oral presentation (general)  

Venue：岡山市   Country：Japan  

Event date： 2018.10

Language：English   Presentation type：Oral presentation (general)  

Venue：Kona(Hawaii）   Country：United States  

Event date： 2017.11

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：鹿児島大学   Country：Japan  

Three dimensionally scaled IGBTs that have a scaling factor of 3 (k=3) with respect to current commercial
products (k=1) were fabricated for the first time. The scaling was applied to the lateral and vertical dimensions as well as the gate voltage. A significant decrease in ON resistance, -- V_CEsat reduction from 1.70 to 1.26 V -- was experimentally confirmed for the 3D scaled IGBTs.

Event date： 2017.10

Language：English   Presentation type：Oral presentation (general)  

Venue：Changchun   Country：China  

Event date： 2017.9

Language：English   Presentation type：Oral presentation (general)  

Venue：Tokyo   Country：Japan  

Event date： 2017.9

Language：English   Presentation type：Oral presentation (general)  

Venue：Tokyo   Country：Japan  

Event date： 2017.7

Language：English   Presentation type：Oral presentation (general)  

Venue：Potsdam   Country：Germany  

Event date： 2017.7

Language：English   Presentation type：Symposium, workshop panel (public)  

Venue：Potsdam   Country：Germany  

Event date： 2017.5

Language：English   Presentation type：Oral presentation (general)  

Venue：Nuremberg   Country：Germany  

Event date： 2017.3

Language：English   Presentation type：Oral presentation (general)  

Venue：Nuremberg   Country：Germany  

Event date： 2021.10

Language：English   Presentation type：Oral presentation (general)  

Venue：オンライン開催   Country：France  

Event date： 2021.10

Language：English   Presentation type：Oral presentation (general)  

Venue：オンライン開催   Country：France  

Event date： 2021.5 - 2021.6

Language：English   Presentation type：Symposium, workshop panel (public)  

Venue：オンライン   Country：Japan  

Event date： 2021.4

Language：English   Presentation type：Oral presentation (general)  

Venue：オンライン   Country：China  

Event date： 2021.2

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：オンライン   Country：Japan  

Event date： 2021.2

Language：Others  

Country：Japan  

Event date： 2020.12

Language：Japanese   Presentation type：Symposium, workshop panel (public)  

Venue：オンライン   Country：Japan  

Event date： 2020.12

Language：Others  

Country：Japan  

Event date： 2020.12

Language：Japanese   Presentation type：Symposium, workshop panel (public)  

Venue：オンライン   Country：Japan  

Event date： 2020.11

Language：English   Presentation type：Oral presentation (general)  

Venue：オンライン   Country：China  

Event date： 2020.10

Language：English   Presentation type：Oral presentation (general)  

Venue：オンライン   Country：Greece  

Event date： 2020.9

Language：English   Presentation type：Oral presentation (general)  

Venue：オンライン   Country：Japan  

Event date： 2020.9

Language：Others  

Country：Japan  

Event date： 2020.9 - 2020.10

Language：English   Presentation type：Oral presentation (general)  

Venue：オンライン   Country：Japan  

Event date： 2020.9 - 2020.10

Language：Others  

Country：Japan  

Event date： 2020.9

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：オンライン   Country：Japan  

Event date： 2020.9

Language：Others  

Country：Japan  

Event date： 2020.9

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：オンライン   Country：Japan  

Event date： 2020.9

Language：English   Presentation type：Oral presentation (general)  

Venue：オンライン   Country：Austria  

Event date： 2020.9

Language：Others  

Country：Austria  

Dynamic Avalanche Free Super Junction-TCIGBT for High Power Density Operation

Event date： 2020.9

Language：Others  

Country：Austria  

Event date： 2020.9

Language：English   Presentation type：Oral presentation (general)  

Venue：オンライン   Country：Austria  

Event date： 2020.9

Language：English   Presentation type：Oral presentation (general)  

Venue：オンライン   Country：Austria  

Event date： 2020.3

Language：English   Presentation type：Oral presentation (general)  

Venue：オンライン   Country：United States  

Event date： 2020.3

Language：Others  

Country：United States  

Event date： 2019.12

Language：English   Presentation type：Oral presentation (general)  

Venue：San francisco   Country：United States  

Event date： 2019.11

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：仙台   Country：Japan  

Event date： 2019.11

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：仙台   Country：Japan  

Event date： 2019.10 - 2019.11

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：大阪   Country：Japan  

Event date： 2019.9 - 2019.10

Language：English  

Venue：京都   Country：Japan  

Event date： 2019.9

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：札幌   Country：Japan  

Event date： 2019.9

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：札幌   Country：Japan  

Event date： 2019.9

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：札幌   Country：Japan  

Event date： 2019.9

Language：English   Presentation type：Oral presentation (general)  

Venue：名古屋   Country：Japan  

Event date： 2019.9

Language：English  

Venue：名古屋   Country：Japan  

Event date： 2019.7 - 2019.8

Language：English   Presentation type：Oral presentation (general)  

Venue：Keystone   Country：United States  

Event date： 2019.7 - 2019.8

Language：English  

Venue：Keystone   Country：United States  

Event date： 2019.7 - 2019.8

Language：English   Presentation type：Oral presentation (general)  

Venue：Keystone   Country：United States  

Event date： 2019.5

Language：English  

Venue：Shanghai   Country：China  

In this work, 5V gate drive 3300V IGBTs, designed based on a scaling principle, have been demonstrated. Turn-off characteristics without noticeable degradation in the gate voltage waveforms were confirmed. Turn-off tail current of the scaled devices significantly decreased than conventional 15V-driven devices. As a result of both V_ce and turn-off loss reduction, 35&#37; improvement in E_off vs V_cesat relationship was achieved.

Event date： 2019.5

Language：English  

Venue：Shanghai   Country：China  

TCAD simulation has been recognized as a powerful design tool for insulated gate bipolar transistors (IGBTs). In this work, excellent agreement between 3D TCAD simulations and experimental current-voltage characteristics were obtained in the up to 1000 A/cm² region for IGBTs with scaled trench-gates. The results of 2D and 3D simulations are compared to discuss the difference in current-voltage characteristics and their physical origins. A method to evaluate the saturation current (J_Csat) using a 2D simulation is also presented with an appropriate correction.

Event date： 2019.5

Language：English   Presentation type：Oral presentation (general)  

Venue：Nuremberg   Country：Germany  

Event date： 2019.3

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：東京   Country：Japan  

ＣＺ炉内のＣＯガス濃度をガスクロマトグラフにより測定した。炉内の脱ガスによって発生するCOと、石英ルツボと黒鉛ルツボの反応に起因するCO、及び、Si融液に石英ルツボが溶解して発生するSiOガスと黒鉛部材の反応で発生するCO のそれぞれの寄与を分離して把握した。

Event date： 2019.3

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：東京   Country：Japan  

Event date： 2019.3

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：東京   Country：Japan  

Si絶縁ゲートバイポーラトランジスタ(Si-IGBT)は高耐圧パワー半導体デバイスとして今後の主流になると期待され、3Dスケーリング等の開発が進められている。さらに、Si-IGBTの性能向上にはキャリアライフタイム制御も重要である。
Si-IGBT製造には、周囲に空乏層を作り耐圧を高めるためにガードリングを形成する必要がある。このガードリングを形成するプロセスでは、1100℃、3 hourの高温ウエット酸化処理で約1 μmのマスク酸化膜を形成し、リソグラフィとエッチングでパターンを形成し、Bイオン注入を行う。続いて1100℃、20 hourの拡散処理を行なっている。本研究では、高温ウエット酸化処理プロセスにより、酸素がFZ-Si中に注入され、少数キャリアライフタイムが減少することを見出したので報告する。

Event date： 2018.12

Language：Japanese  

Venue：横須賀市   Country：Japan  

Event date： 2018.12

Language：English  

Venue：San Francisco   Country：United States  

Functional trench-gated 1200V-10A class Si-IGBTs, designed based on a three dimensional (3D) scaling concept, were fabricated, and 5V gate voltage switching operation has been demonstrated for the first time. 33&#37; reduction of turn-off loss and 100mV improvement of on-state voltage were achieved, while keeping 1.2kV forward blocking voltage.

Event date： 2018.11

Language：English  

Venue：岡山市   Country：Japan  

Event date： 2018.11

Language：English   Presentation type：Oral presentation (general)  

Venue：金沢市   Country：Japan  

Event date： 2018.11

Language：Others   Presentation type：Oral presentation (general)  

Venue：西安   Country：Colombia  

Event date： 2018.11

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：川崎市   Country：Japan  

Event date： 2018.10 - 2018.11

Language：English   Presentation type：Oral presentation (general)  

Venue：仙台市   Country：Japan  

Event date： 2018.10

Language：English   Presentation type：Oral presentation (general)  

Venue：Kona(Hawaii）   Country：United States  

Event date： 2018.9

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：名古屋市   Country：Japan  

Event date： 2018.9

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：名古屋市   Country：Japan  

Event date： 2018.9

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：名古屋市   Country：Japan  

Event date： 2018.9

Language：English  

Venue：Varna   Country：Bulgaria  

Event date： 2018.9

Language：English   Presentation type：Oral presentation (general)  

Venue：Dresden   Country：Germany  

The injection enhancement effect in IGBTs was experimentally verified by separately measuring emitter electron-and hole-currents for the first time. Finger contacts were employed as ladder-like periodic n+ and p+ emitters to allow the independent measurement of these currents. Both reducing the mesa width and increasing the cell pitch were found to increase electron injection from the emitter, demonstrating the injection enhancement effect. These experimental results agreed well with the simulation results.

Event date： 2018.8

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：横浜市   Country：Japan  

Event date： 2018.6

Language：English   Presentation type：Oral presentation (general)  

Venue：Honolulu   Country：United States  

A new methodology to evaluate the process temperature dependence of the minority carrier lifetime has been developed. A TEG layout with p+-stripes on an n-Si substrate was designed. When all the p+n junctions are made forward, the minority carrier diffusion current flows one dimensionally into the substrate. On the other hand, for making only the one center p+n junction forward, the current spreads laterally and flows cylindrically into the substrate. By the difference in the flow path of the minority carrier diffusion, we can successfully extract the minority carrier lifetime. We applied this methodology to the evaluation of the minority carrier lifetime depending on process temperatures and confirmed the lifetime degradation for high temperature process.

Event date： 2018.4

Language：English   Presentation type：Oral presentation (general)  

Venue：仙台市   Country：Japan  

Event date： 2018.3

Language：English   Presentation type：Oral presentation (general)  

Venue：Granada   Country：Spain  

Event date： 2018.3

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：早稲田大学（東京都）   Country：Japan  

Event date： 2018.3

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：早稲田大学（東京都）   Country：Japan  

分極接合による高濃度二次元正孔ガスの形成技術を利用したPチャネルFETのデバイス特性をシミュレーションで検討するに当たり、AlGaN/GaN界面に生じる二次元正孔／電子ガスを枯渇させるバックゲート電圧が実測と大きく乖離する現象が見られた。本講演ではAlGaN/GaN界面に界面準位を想定することで実測を一部よく再現する結果が得られたので報告する。

Event date： 2018.3

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：早稲田大学（東京都）   Country：Japan  

Event date： 2017.10

Language：English   Presentation type：Oral presentation (general)  

Venue：貴陽市   Country：China  

Event date： 2017.9

Language：English   Presentation type：Oral presentation (general)  

Venue：Sendai International Center（仙台市）   Country：Japan  

Event date： 2016.12

Language：English  

Venue：San Francisco   Country：United States  

Three dimensionally (3D) scaled IGBTs that have a scaling factor of 3 (k=3) with respect to current commercial products (k=1) were fabricated for the first time. The scaling was applied to the lateral and vertical dimensions as well as the gate voltage. A significant decrease in ON resistance, - Vce(sat) reduction from 1.70 to 1.26 V - was experimentally confirmed for the 3D scaled IGBTs.

Event date： 2016.3

Language：English  

Venue：Long Beach   Country：United States  

DC-link capacitors in power electronic converters are a major constraint on improvement of power density as well as reliability. Evaluation of the dc-link capacitors in terms of power loss, ageing, and failure rate will play an important role in design stages of the next-generation power converters. This paper proposes a new evaluation circuit for dc-link capacitors used in a high-power three-phase inverter, which is intended for testing power loss, failure rate, ageing, and so on. The evaluation circuit produces a practical ripple current waveform and a dc bias voltage into a capacitor under test, in which the ripple current is equivalent to that generated by the three-phase inverter on the dc link. The evaluation circuit employs a full-scale current-rating and downscaled voltage-rating inverter for producing the ripple current, so that the power rating of the evaluation circuit is much smaller than that of a full-scale current rating and full-scale voltage rating inverter.

Event date： 2015.11

Language：English  

Venue：Macau   Country：Macao  

For the future power electronics system, one of the key issues is to achieve more high power densities. At the moment, several types of silicon devices are widely used from the low voltage to high voltage ranges. To achieve more high power densities by size reduction and more high operating temperature, not only the device but also wafer material should be improved. The current status and future prospect of PE system with silicon technology will be discussed. Then, the role of compound semiconductor and its devices will be also discussed by comparison with silicon PE system.

Event date： 2015.10

Language：English  

Venue：New Orleans   Country：United States  

This paper gives an overview of GaN-based polarization-junction (PJ) technologies. PJ platform wafers have both high-density 2D hole gas (2DHG) and 2D electron gas (2DEG) respectively induced by negative and positive polarization charges in undoped GaN/AlGaN/GaN double heterostructures. On the platform, monolithic operations of GaN-based n-channel transistors and p-channel transistors have been demonstrated. Because of temperature independent properties of the 2DHG and 2DEG, the GaN devices can operate in wide temperature range. In addition, high voltage transistors and diode are also available on the platform by using polarization-superjunction concept.

Event date： 2015.5

Language：English  

Venue：San Diego   Country：United States  

We demonstrate fabrication a silicon on diamond structure at around room temperature using a plasma-activated bonding (PAB) method. Thin and flat silicon-dioxide (SiO₂) film was used as an activation layer for PAB. The SiO₂ film was prepared by a chemical vapor deposition and then a chemical mechanical polishing (CMP). The surface roughness after the CMP were average ∼1 nm rms at 300 nm thick. Thinning of the SiO₂ film was carried out using 2.5&#37;HF solution. We found that there are no significant change in the surface roughness after the thinning process. The roughness of SiO₂ less than or equal to 1 nm is required for success bonding at low-temperature with vacuum environment. The scanning electron microscope has shown seamless at the bonding interface that proves to good bonding result.

Event date： 2015.5

Language：English  

Venue：Nuremberg   Country：Germany  

Power converter efficiencies of 1200-V class Si-IGBT/SiC-SBD hybrid pairs and a SiCMOSFET/ SiC-SBD pair were theoretically compared at a switching frequency above the limit of human hearing (20 kHz). Si-IGBT losses were simulated by TCAD. SiC device losses were calculated by analytical minimum loss models. Calculated efficiencies of the full-SiC pair were slightly higher than that of the hybrid pairs at conventional current densities less than 200 A/cm². At a higher current density of 400 A/cm², the hybrid pairs have a potential of high performance which is comparable with the full-SiC efficiency.

Event date： 2015.5

Language：English  

Venue：Hong Kong   Country：China  

Polarization junction platforms have high-density 2D hole gas (2DHG) and 2D electron gas (2DEG) respectively induced by negative and positive polarization charges in undoped GaN/AlGaN/GaN double heterostructures. Sheet resistance measurements in a wide temperature range (6-460 K) revealed that 2DHG and 2DEG resistances were monotonically enhanced with the temperature reduction. On the platform, monolithic operations of GaN-based devices including high-voltage n-channel (N-ch) transistors, N-ch Schottky diodes, low-voltage N-ch transistors and p-channel transistors has been demonstrated.

Event date： 2014.9

Language：English  

Venue：Grenoble   Country：France  

A novel dicing technology that utilizes femtosecond pulsed lasers (FSPLs) is demonstrated as a high-speed and cost-effective dicing process for SiC wafers. The developed dicing process consists of cleavage groove formation on a SiC wafer surface by the FSPL, followed by chip separation by pressing a cleavage blade. The effective FSPL scan speed on the SiC surfaces was 33 mm/s. Kerf loss is negligible in the developed FSPL dicing process. In addition, the residual lattice strain in the FSPL-diced SiC chips was comparably small to that of the conventional mechanical process using diamond saws, due to the absence of the lattice heating effect in femtosecond-laser processes.

Event date： 2014.6

Language：English  

Venue：Waikoloa, HI   Country：United States  

Monolithic operation of GaN-based P-channel (Pch) and N-channel (Nch) heterojunction field effect transistors (HFETs) are demonstrated for the first time. The Pch and Nch HFETs were fabricated on a polarization junction platform with polarization induced 2D hole gas (2DHG) and 2D electron gas (2DEG). Because of temperature independent densities of the 2DHG and 2DEG, the HFETs can be operated in wide temperature range. Based on a measured 2DHG mobility, footprints of low-voltage Pch HFETs for gate drive applications were estimated by device simulation.

Event date： 2014.5

Language：English  

Venue：Hiroshima   Country：Japan  

In this paper, the novel normally-on type bidirectional switch, in which is comprised of SiC-JFET, SiC-SBD, and Si-IGBT is proposed for one of a protection method of the Matrix Converter (MC). When the MC becomes gate block situation, a diode clamp circuit or auxiliary circuits keeps inductive load current loop in a conventional MC utilized a bidirectional switch. We focus that the normally-on type SiC-JFET becomes turn-on state, when zero gate bias voltage and a SiC-devices have a good tolerance capability for short current than silicon devices. These characteristic of normally-on type SiC-JFET is used to replace diode clamp circuit in MC driver system. The experimentation based on indirect MC induction motor driver system was carried out. The experimental result of IM driver shows that the proposed bidirectional switch can overcome a generated inductive load current by IM. Finally, in order to design heat sink, the power loss of each devices of proposed switch was estimated by experimental results.

Event date： 2014.5

Language：English  

Venue：Hiroshima   Country：Japan  

A bi-directional isolated DC/DC converter for medium-voltage applications have been discussed for the next-generation electrical grid, such as smart girds. To realize the DC/DC converter for installing on a power distribution system, it should be achieved higher-efficiency and lower-volume. Higher switching frequency enables to reduce the volume of the transformer. However, it is difficult to realize the both higher-efficiency and lower-volume of the DC/DC converter, because it could not operate higher frequency with high power devices such as medium-voltage IGBTs. This paper discusses switching losses and operation limitations for the actual medium-voltage isolated DC/DC converter, in the case of using Si-IGBT. In addition, the experimental system rated at 2.5 kV, 200 kW, and 5kH of the DC/DC converter with a medium-frequency transformer is designed, and the experimental results are shown.

Event date： 2013.10

Language：English  

Venue：Columbus, OH   Country：United States  

Electrical properties of two-dimensional hole gas (2DHG) at GaN/Al _0.23Ga_0.77N heterointerface have been investigated. Existence of 2DHG at the interface is confirmed by capacitance-voltage and Hall Effect measurement. We have discussed transport mechanism of 2DHG by comparison with hole generated by conventional Mg impurity, based on experimental evaluations by X-ray diffraction, transmission electron microscope, atomic force microscope, secondary ion mass spectroscopy, and temperature dependence Hall Effect measurements.

Event date： 2013.10

Language：English  

Venue：Matsue   Country：Japan  

A 4.5kV-400A SiC-PiN diode and Si-IEGT hybrid pair module has been developed for realizing high switching frequency operations of medium-voltage power converters. The maximum switching frequency of the hybrid pair module is theoretically analyzed from viewpoints of cooling capacity of the heat sink and the minimum pulse width of a PWM signal. Operation tests of the hybrid pair module are implemented and 10 kHz operation has been successfully demonstrated.

Event date： 2013.9

Language：English  

Venue：Denver, CO   Country：United States  

Possibility of a 10 kHz switching frequency operation of a 4.5kV-400A SiC-PiN diode and Si-IEGT hybrid pair module has been investigated to drastically increase the switching frequency of medium-voltage power converters. For this purpose, the relation among the minimum pulsed width of the PWM signal, the modulation index, and the maximum switching frequency is analyzed based on the switching characteristics of the hybrid pair module. The analyzed data show that the 10 kHz switching frequency could be available with the hybrid pair module.

Event date： 2013.9

Language：English  

Venue：Denver, CO   Country：United States  

Possibility of a 10 kHz switching frequency operation of a 4.5kV-400A SiC-PiN diode and Si-IEGT hybrid pair module has been investigated to drastically increase the switching frequency of medium-voltage power converters. For this purpose, the relation among the minimum pulsed width of the PWM signal, the modulation index, and the maximum switching frequency is analyzed based on the switching characteristics of the hybrid pair module. The analyzed data show that the 10 kHz switching frequency could be available with the hybrid pair module.

Event date： 2013.9

Language：English  

Venue：Denver, CO   Country：United States  

The maximum switching frequency of a 4.5 kV-400 A SiC-PiN diode and Si-IEGT hybrid pair module has been analyzed from the viewpoints of cooling capacity of the hybrid pair module and the minimum pulse width of the PWM signal. In the developed hybrid pair module, a direct water cooling type heat sink is employed to enhance the cooling capacity. It found that the developed 4.5 kV-400 A hybrid pair module could be operate at 10 kHz PWM switching frequency with the peak current of 110 A and the dc voltage of 2.5 kV. In this operating condition, the power losses of the Si-IEGT and SiC-PiN diode in the hybrid pair module are 2380W and 100 W, respectively.

Event date： 2012.10

Language：English  

Venue：Honolulu, HI   Country：United States  

The state of the art of silicon carbide crystal growth modeling is explained from the two aspects. One is the technical problems of SiC bulk single crystal growth process by sublimation method. Numerical modeling can contribute on the reactor design and process condition optimization. Then the shape of SiC grown crystal (diameter and length) can be controlled by modifying the growth crucible design. Second one is the theoretical problem of SiC polytype control. By calculating the bulk crystal energy of each polytype, and surface energy of each possible surface during growth, it is pointed out that growin surface energy has effects on the polytype stability of SiC crystals.

Event date： 2012.9

Language：English  

Venue：Raleigh, NC   Country：United States  

A new 4.5 kV-400 A module using SiC-PiN diodes and Si-IEGTs hybrid pair has been developed. The hybrid pair module is designed to realize high-frequency switching operation of high power medium-voltage power converters (1-10MVA, voltage range 310kV). In order to realize a low switching loss operation of the hybrid pair module, a hard gate driving with low gate resistor has been employed. Switching characteristics of the hybrid pair are evaluated experimentally and compared with that of a conventional 4.5 kV Si-IEGT and Si-PiN diode pair (All Si). The results show that the reverse recovery loss of diode and the turn-on loss of the Si-IEGT are reduced up to 95&#37; and 60&#37;, respectively. As a result, the total switching loss (i.e. turn-on and turn-off losses of the Si-IEGT plus reverse recovery loss of the diode) can be reduced up to 49&#37; with the hybrid pair. The developed hybrid pair modules are applied to a prototype high power converter, and a high-frequency switching operation of 4 kHz has been successfully demonstrated.

Event date： 2012.6

Language：English  

Venue：Harbin   Country：China  

Silicon carbide(SiC) power devices have been developed and they are sold in markets. Many papers have dealt with inverter circuits that use SiC power devices to improving efficiency and realize high power density converters. However, the power converters that use SiC power devices have not become commercially available, because the reliability of the SiC-MOSFET under switching-operation has not been sufficiently discussed. This paper presents a non-destructive test circuit for SiC-MOSFETs, and the experimental results have confirmed the validity of the non-destructive test circuit for Si- and SiC-MOSFETs. Moreover, the experimental results presents the phenomenon just before destruction of the MOSFETs. The purpose of the non-destructive test circuit is to evaluate the extreme conditions under actual switching operation without the destruction of the power devices. This paper shows experimental results under short-circuit tests for Si super junction MOSFETs (SJ-MOSFETs), and SiC double-diffusion MOSFETs (DMOSFETs). These experimental results will be analyzed to improve the reliability of SiC power device. As a result, the short-circuit switching operation of the SiC-MOSFET is observed to be different from that of the Si-MOSFET.

Event date： 2011.10

Language：English  

Venue：Xi'an   Country：China  

As widely known, diamond has a higher break-down voltage than other semiconductor materials, 30 times than silicon and 3 times than silicon-carbide. Because of its superior property, diamond has a high potential of high voltage power devices. In addition diamond has unique properties, namely transport property of heavily doped material over 10 ²⁰ cm ^-3, high density exciton being stable even at room temperature, negative electron affinity with hydrogen terminated surface, etc. We have fabricated diamond devices using these properties, such as ultraviolet light emitting diodes, a new type of diode with high breakdown voltage and low ON resistance, high current density flow diode using heavily doped layers, and so on. In this key note lecture, we show the recent achievements of these electronic devices and discuss the potential of diamond semiconductor as a high voltage power device.

Event date： 2011.9

Language：English  

Venue：Cleveland, OH   Country：United States  

Crystal growth velocity of SiC in a process of physical vapor transport was studied on the basis of numerical calculation including the effect of compressibility, convection and buoyancy effects, flow coupling between argon gas and species of Si, Si ₂C and SiC ₂, and the Stefan effect. Calculation in a 2D configuration was performed to clarify the effect of pressure on growth velocity. The results revealed that convection plays a role in the measured values that growers interpret as growth velocity based on a diffusion process of argon gas and species of Si, Si ₂C and SiC ₂.

Event date： 2011.9

Language：English  

Venue：Cleveland, OH   Country：United States  

We investigated with ab initio calculations the 3C-, 6H-, 4H- and 2H-SiC polytypes. We discuss the geometry and the energetics of bulk and surface relaxed structures ((0001) Si face and the (000̄1) C face surfaces). The polytype stability is discussed regarding the bulk and surface effects.

Event date： 2011.8 - 2011.9

Language：English  

Venue：Birmingham   Country：United Kingdom  

In order to suppress overvoltage of power devices and noise voltages of inverters, it is essential to analyze the DC-side inductance of the inverter. This paper presents a design procedure of an optimum structure for a 10-kV, 400-kVA three-level inverter. Rather than using 3D-FEM software, the bus bar inductance for the medium voltage inverter is calculated based on a partial inductance method. An inductance map is useful for determining the relationship between the bus bar structure and the inductance value and for designing the low-inductance structure. In addition, the calculation results of the bus bar inductance correspond to the measurement results, confirming the validity of the proposed method.

Event date： 2010.8 - 2010.9

Language：English  

Venue：Oslo   Country：Norway  

We investigated numerically fluid dynamics and carbon transport in a 2 inches SiC solution growth with the presence of alternative magnetic fields. Buoyancy and Marangoni convection are taken into account. Our numerical results revealed that the magnetic field parameters have a strong impact on the melt convection. We also propose a solution to increase the mass transfer at the crystal growth front.

Event date： 2009.10

Language：English  

Venue：Nurnberg   Country：Germany  

Calculations of lattice constant of 4H-SiC and diamond have been carried out. Lattice constant of 4H-SiC trends to decrease when nitrogen concentration increases. On the other hand, lattice constant of 4H-SiC trends to increase when aluminum concentration increases. Lattice constant of boron and phosphorus doped diamond trends to increase when impurity concentration increases. The effect of phosphorus on diamond lattice constant is about six times larger than that of boron.

Event date： 2008.9

Language：English  

Venue：Barcelona   Country：Spain  

Previous simulation works and experiments on the loss of 4H-SiC floating junction Schottky barrier diodes (Super-SBDs) show that the loss is related to the doping concentration in the drift region and the pattern of the floating layer. The effect of the doping concentration for lowering the loss is characterized the breakdown voltage (V_bd) and the on-state resistances (R_onS) of the Super-SBDs based on Baliga's figure of Merit (BFOM). Experimental devices with two doping concentrations in the drift region are fabricated to investigate the static characteristics: V_bd and R_onS. The V_bd of the Super-SBDs is close to the simulation result, near 3000 V. However the tendency of the V_bd by the doping concentration is not similar to the simulation result. And the RonS are about 3.22 mΩcm² which is higher than that of simulation result. The doping concentration optimized in this study does not show significant lowering loss and the design of the floating layer in the termination region affect the low-loss static characteristics of the Super-SBD. In addition, adopting PiN structure with floating layer (Super-PiN) affects the low-loss dynamic characteristics, optimizing the doping concentration in the drift region. We conclude that the fabricated Super-SBDs with the floating layer in the termination region, the drift region with a doping concentration of 1.0×10¹⁶ cm^-3 and mesa-shaped termination structure, have excellent Vbd of 2990 V which is almost same as that of simulation result and RonS of 3.22 mΩcm².

Event date： 2007.5

Language：English  

Venue：Jeju Island   Country：Korea, Republic of  

Normally-off power MOSFET with low R_ons has been developed. IEMOSFET on 4H-SiC carbon-face wafer exhibits an extremely low R_ons of 1.8 mωcm² with a blocking voltage of 660 V. The effective channel mobility of this device is 90 cm²/Vs which corresponds to the channel resistance of 0.8 mωcm². A step-down converter was fabricated with the normally-off IEMOSFET and SBD, and the operation of 400 W DC motor drive was successfully observed at room temperature.

Event date： 2006.4

Language：English  

Venue：San Francisco, CA   Country：United States  

The effect of infrared absorption on SiC sublimation growth was numerically investigated. At first, absorption coefficient was estimated as function of doping concentration. Then temperature distribution inside a crucible was numerically analyzed with taking account of absorption in growing crystal. It was pointed out that temperature distribution in a growing crystal strongly depends on absorption coefficient, i.e. doping concentration. As increasing the absorption coefficient, the growth front temperature and temperature gradient inside a growing crystal increase. It might cause large thermal stress and affect the grown crystal quality. This agrees well with growth features in experiment. The growth condition should be determined with taking account of absorption coefficient, i.e. doping concentration.

Event date： 2006.4

Language：English  

Venue：San Francisco, CA   Country：United States  

Modeling and simulation of the SiC growth processes, Physical Vapor Transport (PVT), Chemical Vapor Deposition (CVD) and hybrid techniques, are sufficiently mature to be used as a training tool for engineers as well as a growth machine design tool, e.g. when building new process equipment or up-scaling old ones. It is possible (i) to simulate accurately temperature and deposition distributions, as well as doping (ii) to quantify the limiting phenomena, (iii) to understand the important role of different precursors in CVD and hydrogen additions in PVT. The first conclusion of this paper is the importance of the "effective" C/Si ratio during CVD epitaxy in hot-wall reactors and its capability to explain the doping concentrations. The second conclusion is the influence of the C/Si ratio in alternative bulk growth technique involving gas additions. Preliminary results show that fine tuning of H₂ or precursor additions allow a better control of concentrations of residual and intentional doping.

Event date： 2005.9

Language：English  

Venue：Pittsburgh, PA   Country：United States  

We perform rapid thermal annealing (RTA) on areas as large as 2-inch φ (diameter) at high temperature using the hybrid super RTA (HS-RTA) equipment. The HS-RTA equipment consists of an infrared annealing unit and a RF induction annealing unit in order to uniformly anneal over 2-inch φ susceptor. As a result of annealing by the HS-RTA equipment, the temperature is elevated from RT to peak temperature (∼1800°C) for less than 1 min, remain stable at annealing temperature for 30s and falls from peak temperature to 1000°C within less than 20s. The temperature distributions on a 2-inch φ susceptor are ±10°C, ±33°C and ±55°C at 1565°C, 1671°C and 1752°C, respectively. Phosphorus (P) ion implanted silicon carbide (SiC) samples are used to evaluate the performance of the HS-RTA equipment. The five implanted samples placed on the 2-inch φ susceptor are annealed for 30s at 1565°C, 1671°C and 1752°C. The mean sheet resistances of the 5 samples annealed at 1565°C, 1671°C and 1752°C are 92.6Ω/□, 82.6Ω/□ and 75.50/□, respectively. The sheet resistance uniformities are 9.9&#37;, 7.9&#37; and 9.3&#37;. The average roughness (R_a) is calculated from 10 μm square Atomic Force Microscopy (AFM) image. R_a values of the samples annealed at 1565°C, 1671°C and 1752°C are 2.399 nm, 2.408 nm and 3.282 nm, respectively.

Event date： 2005.9

Language：English  

Venue：Pittsburgh, PA   Country：United States  

From the engineering point of view, SiC hot-wall epitaxy is a very important process in SiC semiconductor processes. There are lots of experimental reports on SiC hot-wall epitaxy. They discussed the growth rate, surface morphology, doping concentration, etc. Recently, the effect of face polarity is also made clear. However, each report mentioned the particular results that strongly depend on the experimental conditions and reactor design. In addition, the discussion with inlet condition such as source gas C/Si ratio, not the depositing surface condition, leads to the confusion. In order to understand and try to design and optimize the hot-wall CVD reactor, a numerical approach is attempted. The authors have tried to make it clear that depositing surface condition might be a universal parameter of SiC CVD, and the numerical simulation could predict the growth rate, surface morphology and doping concentration by taking account of the depositing surface condition. In this study, at first, the recent progress of SiC hot-wall epitaxy in experiment is summarized. Then, the present status of its numerical modeling is explained.

Event date： 2005.9

Language：English  

Venue：Pittsburgh, PA   Country：United States  

4H-SiC floating junction Schottky barrier diodes (Super-SBDs) were fabricated. It was found that their properties are closest to the theoretical limitation, defined by the relationship between specific on-state resistance and breakdown voltage of 4H SiC-unipolar devices. They have a p-type floating layer designed as line-and-spacing. The specific on-state resistances of Super-SBDs with a few micrometers of spacing width were found to be nearly equal to those of conventional SBDs without p-type floating layer. The breakdown voltages of Super-SBDs were higher than those of conventional SBDs. Accordingly the properties of Super-SBDs have improved the trade-off between specific on-state resistance and breakdown voltage, and the highest value to date for Baliga's Figure of Merit (BFOM) has been obtained.

Event date： 2005.9

Language：English  

Venue：Bochum   Country：Germany  

Modeling and simulation of the SiC growth processes, Physical Vapor Transport (PVT) and Chemical Vapor Deposition (CVD), are sufficiently mature to be used as a training tool for engineers as well as a growth machine design tool, e.g. when building new process equipment or up-scaling old ones. It is possible to simulate accurately temperature and deposition distributions, as well as doping. The key of success would be the combined use of simulation, experiments and characterization in a "daily interaction". The different presented examples have the aim to show that this approach has the potential of a characterization tool which could be of great importance in the optimization of epitaxial structures used for the fabrication of SiC-based devices.

Event date： 2004.8 - 2004.9

Language：English  

Venue：Bologna   Country：Italy  

We report defects study in 4H-SiC bulk crystals grown by sublimation method on micropipe filled seed crystals oriented (0001) on-axis. The seed crystals of 1-3 inch in diameter were prepared from the large 4H-SiC bulk crystals. Before the sublimation growth, micropipes of the seed crystals were filled with epilayers grown by micropipe filling technique of CVD method. We confirmed about 95&#37; of micropipes perfectly disappeared in the grown crystal. The mechanism of the micropipe extinction was also defined by defect analysis.

Event date： 2004.8 - 2004.9

Language：English  

Venue：Bologna   Country：Italy  

Growth, etching, and doping features of SiC-CVD in a horizontal hot-wall reactor were numerically analyzed using the improved heterogeneous model. The improved model was able to explain the growth and etching features accurately. In addition, we propose the surface flux, surface carbon and silicon concentration, and its ratio as the universal parameter of the SiC-CVD process. Concerning doping features, the improved model showed that nitrogen and aluminum doping incorporation could be explained by the site competition model, while taking into account the amount of surface silicon and surface carbon, respectively.

Language：Others  

Language：Others  

Language：Others  

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Language：Japanese  

A method of estimating power loss of an aluminum electrolytic capacitor with square-wave current injection

Language：Others  

Language：Japanese  

GaN-based Monolithic Power Integrated Circuit Technology with Wide Operating Temperature

Language：Others  

Language：Others  

Language：Others