記述言語：その他   掲載種別：研究論文（学術雑誌）   出版者・発行元：Power Electronic Devices and Components  

This paper reports the mechanism of gate voltage spike in the turn-off operation by a digital gate control. In the previous work, it was clarified that the gate voltage spike Vg_spike was generated by parasitic inductance and a large gate current change due to the digital gate control. However, the main cause of resonance leading to Vg_spike generation has never been clear. Three types of IGBT modules, which have the same gate inductance and different input capacitance, were tested under three-step digital gate control. It was found that the Vg_spike was independent of input capacitance in IGBT. As for the stray capacitance in the digital gate driver, external capacitors Cex were connected in parallel with the gate driver, and the Vg_spike decreased with increasing Cex. Furthermore, the second vector of the digital control, which was applied for suppressing the overshoot in collector-emitter voltage by a small value, needed to be set as a large value to suppress the Vg_spike. From these results, output impedance of gate driver is a key factor for the Vg_spike, and the second vector must be optimized for not only the collector voltage overshoot but also Vg_spike suppression for safety operation.

DOI： 10.1016/j.pedc.2023.100054

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出版者・発行元：Japanese Journal of Applied Physics  

In silicon insulated gate bipolar transistors, the trench gate structure is used to achieve smaller cell size and lower ON resistance, and thereby reduces energy loss. However, the thermal process can cause large stress near the trench and sometimes degrades device performance. This study proposed a three-dimensional model of a silicon chip with trench structures to analyze the stress distribution induced by thermal process around the trench, the scribe line, and the bottom surface of the chip. The calculated stress is in good agreement with measurement by Raman spectroscopy. The mesa top has much higher stress than the scribe line and the bottom surface. The stress depends on oxide thickness and the size scaling may reduce the stress.

DOI： 10.35848/1347-4065/ad1e00

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出版者・発行元：Japanese Journal of Applied Physics  

The demand for grown-in defect-free wafers for high-performance silicon semiconductor devices is significantly increasing. To obtain defect-free crystals, the ratio v/G of the growth rate v to the temperature gradient G in the growth direction near the solid-liquid interface during crystal growth must be kept at a critical value ξ cri . Furthermore, ξ cri depends on the interface shape, which is interpreted as the change in the diffusion direction of point defects due to the change in the interface shape. In this study, we present a new interpretation based on simulations and experiments, in which ξ cri changes due to the effect of the diffusion direction of point defects when the solid-liquid interface shape is convex, as in the conventional interpretation, as well as the effect of thermal stress when it is concave.

DOI： 10.35848/1347-4065/ad2d79

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記述言語：日本語   出版者・発行元：一般社団法人 電気学会  

Surge voltage at IGBT turn-off switching was analyzed with dependence on cell design parameters. Although drift layer thinning is effective to improve trade-off characteristics between turn-off loss Eoff and on-state voltage Von, voltage surge is induced due to quick expanding depletion layer. Therefore, the surge voltage Vsurge has also trade-off relationship with the Von at the same Eoff condition. The origin of voltage surge was analyzed using TCAD simulation, and total amount of remained hole in the drift layer during turn-off switching is a key factor for the Vsurge. Narrow mesa structure and thick buffer layer are effective for improvement of trade-off characteristics between Vsurge and Von

DOI： 10.1541/ieejeiss.144.198

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出版者・発行元：Japanese Journal of Applied Physics  

Surge voltage at insulated gate bipolar transistor turn-off switching was analyzed with dependence on cell design parameters. Although drift layer thinning is effective in improving trade-off characteristics between turn-off loss E off and on-state voltage V on, voltage surge is induced due to the quickly expanding depletion layer. Therefore, the surge voltage V surge has also a trade-off relationship with V on at the same E off condition. The origin of the voltage surge was analyzed using TCAD simulation, and the total amount of remaining holes in the drift layer during turn-off switching is a key factor for the V surge. A narrow mesa structure and thick buffer layer are effective for the improvement of trade-off characteristics between V surge and V on. However, the optimum buffer layer thickness depends on the voltage-class due to the speed for punch through.

DOI： 10.35848/1347-4065/ad106d

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出版者・発行元：IEEE Electron Devices Technology and Manufacturing Conference: Strengthening the Globalization in Semiconductors, EDTM 2024  

SiC has high expectations as a next-generation power device material and device because of its excellent semiconductor properties. This report introduces power electronics application fields in which SiC is expected to be used. SiC wafer technology, which is the starting point of the supply chain for realizing this goal, is also introduced.

DOI： 10.1109/EDTM58488.2024.10512311

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掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE Open Journal of Power Electronics  

This paper proposes a solid-state circuit breaker comprising silicon carbide (SiC) MOSFETs and a SiC diode, based on the principle of avalanche voltage clamping. The key challenge in realizing a solid-state circuit breaker lies in reducing conduction loss. A parallel connection of power semiconductor devices is the suitable configuration that can meet these requirements. However, in such a configuration, the current balance during cutoff operation may be affected by the variation in the breakdown voltage characteristics of the power semiconductor devices. To address this issue, the proposed circuit breaker employs clamping with a SiC merged pin Schottky (MPS) diode, with high avalanche tolerance and robust characteristics under repetitive avalanche events. The effectiveness of the proposed solid-state circuit breaker is validated through experiments conducted in an unclamped inductive switching (UIS) test circuit using a 400-V, 50-A DC distribution system. Eventually, the demonstrations indicate that the SiC diode clamping method contributes to more compact implementations for solid-state circuit breakers.

DOI： 10.1109/OJPEL.2024.3365830

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掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE Access  

The health monitoring prediction of power devices is vital for power electronics applications such as renewable converters, electric vehicles, and machine drives. One significant failure mode in the power cycle degradation of Insulated Gate Bipolar Transistor (IGBT) modules is bond wire lift-off. This study uses the gate voltage waveform (Vge ) as an input to an artificial intelligence (AI) model with the Convolutional Neural Network (CNN). The CNN was demonstrated to accurately estimate the IGBT bond wire lift-off, categorizing it into four levels: no damage, light damage, medium damage, and heavy damage. The Digital Gate Driver (DGD) IC was implemented to generate the Vge and collect the data waveforms by two switching modes: Conventional Vector Control (CVC) and 2-step Vector Control (2-sVC). The experiment evaluated the accuracy of the four-level estimation in several aspects. These aspects include switching modes, the number of datasets, and parts of the waveform The results show that the CNN model achieved high accuracy in estimating the wire lift-off trend. The Vge waveform generated by the 2-sVC switching mode showed better estimation accuracy compared to the CVC mode. Furthermore, it also obtained an effective switching performance Eloss -Vce-surge Trade-off curve. Therefore, the DGD is suitable for application and useful for health monitoring and achieving effective switching performance.

DOI： 10.1109/ACCESS.2024.3427643

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掲載種別：研究論文（学術雑誌）   出版者・発行元：Microelectronics Reliability  

This paper investigates the reliability of a solid-state circuit breaker with a clamped SiC diode as avalanche voltage after repeated cutoff operations. In solid-state circuit breakers, a clamping element is connected in parallel with a power semiconductor switch to divert the cutoff current. The SiC merged PiN Schottky (MPS) diode is one of the candidates for clamping elements in solid-state circuit breakers because of its high avalanche tolerance and good robustness after the shocks. Reliability tests indicate that no significant electrical characteristics are found for both the SiC MOSFET and the SiC MPS diode in the proposed circuit breaker, even after more than 10,000 unclamped inductive switching (UIS) cycles. These results are based on a 400 V, 50 A DC distribution system with the UIS condition. The results show that the SiC MPS diode works well as a clamped element for the long-term reliability of the solid-state circuit breaker.

DOI： 10.1016/j.microrel.2023.115119

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記述言語：その他   掲載種別：研究論文（学術雑誌）   出版者・発行元：Power Electronic Devices and Components  

This paper aims to clarify the effect of asymmetric gate inductance Lg and emitter inductance Le inside power modules with two parallel-connected IGBTs on switching characteristics when a three-step digital gate driver is employed. Five types of IGBT modules with different Lg and Le were fabricated to implement double pulse tests by conventional gate driving and digital gate driving with three-step vectors. Under the conventional gate driving, the asymmetric Le introduced an imbalanced current during on-stage, and the asymmetric Lg introduced gate voltage spike Vg_spike and an imbalanced current during the turn-off interval. Large Lg introduced large Vg_spike. From the miller plateau in the turn-off, the current started to concentrate on the IGBT whose Lg is small. In the turn-on interval, the asymmetric Le made current share in two IGBTs become imbalanced, and the occurred large Vg_spike is positively corresponding to the difference of emitter current Ie flowing through two IGBTs. Under digital gate driving, it was found that the tradeoff between switching loss and voltage/current overshoots can be improved. And, the difference of Eoff between two IGBT chips, which results from asymmetric Le mainly, could be decreased more than that in conventional gate driving. In the turn-on interval, the large Vg_spike can be suppressed by a small vector number at the second step, and the difference of turn-on loss Eon could be also decreased. According to the above switching characteristics, the design considerations of power modules with parallel-connected IGBTs were proposed as the digital gate driver is applied.

DOI： 10.1016/j.pedc.2023.100047

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記述言語：その他   掲載種別：研究論文（学術雑誌）   出版者・発行元：Power Electronic Devices and Components  

This paper presents a new detection method of bond wire lift-off in Insulated Gate Bipolar Transistor (IGBT) power module. The bond wire lift-off is a major failure mode in power cycle degradation of the IGBT module, and many monitoring methods have been proposed and demonstrated for safety operation of power electronics systems in the previous works. In this study, we focus on the gate voltage waveform as an indicator to detect wire-lift for a simple and straightforward detection method. Due to the increase in parasitic inductance caused by bond wire lift-off, the turn-off switching waveform becomes modulated. The digital gate control (DGC) was employed to control the switching behavior to obtain precision for low-noise and high-performance. Furthermore, the DGC 2-step vector control (2-sVC) can enhance the sensitivity of bond wire lift-off failure detection by gate voltage waveform change. As feature quantities, the gate voltage spike peak, its amplitude and the timing shift were measured at various operating conditions. The DGC obtained larger feature quantities compared with conventional gate control. In particular, high-current conditions were found to be more favorable for achieving high sensitivity due to the high die/dt. From these results, the DGC is effective to achieve both the high sensitivity to detect bond wire lift-off by gate voltage waveform and maintaining the best switching performance.

DOI： 10.1016/j.pedc.2023.100052

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記述言語：その他   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE Transactions on Industry Applications  

This paper proposes a current limiting function for a self-sensing and self-triggering monolithically integrated SiC circuit breaker device. The proposed function provides the device not only with a fast-response current breaking operation but also with the current limiting operation, including supplying a constant current to the load and preventing the detection of inrush currents. This function is suitable for replacing mechanical conductors in initial charging circuits within rectifiers and safety equipment in case of overcurrent phenomena. The proposed method achieves certain constant currents through a simple variation of the gate-drive circuit with the adjustable parameters of an additional MOSFET. The mechanism of the current limiting function is verified using TCAD simulations based on certain conditions. Consequently, experimental results verified that the circuit breaker device with the current limiting function reduces the inrush current by up to 76.9% using a 500 VDC distribution circuit system.

DOI： 10.1109/TIA.2023.3288856

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記述言語：その他   掲載種別：研究論文（学術雑誌）   出版者・発行元：Microelectronics Reliability  

The bond wire lift-off is the one of main failures for insulated gate bipolar transistors (IGBT) power modules. The wire lift-off increases parasitic inductance LeE in the module and the gate voltage Vge waveform is modulated by LeE·dIe/dt. Therefore, the Vge waveform has the potential for an indicator of condition monitoring. The Digital gate control (DGC) can control switching behavior precisely for low-loss and low-noise switching. It is also effective for sensitivity enhancement of Vge waveform changed by the wire lift-off. This paper reports how the DGC 2-step vector control (2-sVC) can improve the wire lift-off failure detection sensitivity by Vge waveform. The experiment results showed that the Vge spike was generated by LeE·dIe/dt at the turn-off switching and the spike generation timing depended on the wire number. The DGC obtained the larger timing-shift Δtwire and the amplitude ΔVge-surge than those at the conventional gate control. In addition, the best vector condition improved the trade-off between turn-off loss and collector voltage overshoot compared with the conventional gate control. From these results, the DGC is effective to enhance the sensitivity of bond wire lift-off detection by Vge waveform maintaining the best switching performance.

DOI： 10.1016/j.microrel.2023.115067

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記述言語：その他   掲載種別：研究論文（学術雑誌）   出版者・発行元：Microelectronics Reliability  

A new sensor device is proposed for detection of power cycle degradation. Proposed sensor device is consisting of a Schottky-barrier MOSFET and the sensing principle is based on change of I-V characteristics by mechanical stress. Samples were fabricated by metal lift-off process and SiO2 gate insulator film deposition and the fundamental operation was evaluated by four-point bending test for mechanical stress applying. The fabricated device showed monotonically drain current change with number of stress cycles and about 5 times current change compared with initial current after 10,000 cycles of 4 N stress. Large current change by cyclic mechanical stress is attractive for a simple detection of power cycle degradation without expensive analog-circuits.

DOI： 10.1016/j.microrel.2023.115068

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記述言語：その他   掲載種別：研究論文（学術雑誌）   出版者・発行元：Japanese Journal of Applied Physics  

Thermally activated defect behaviors in nitrogen (N)-doped Czochralski silicon (Cz-Si) single crystals were investigated using deep level transient spectroscopy and quasi-steady-state photoconductance to confirm the crystals’ applicability in insulated gate bipolar transistors (IGBTs). The thermally activated defects, which were probably N-vacancy complexes and degraded the minority carrier lifetime, were detected with extremely low densities in N-doped Cz-Si compared with N-rich floating zone Si single crystals after heat treatments at 500 °C, resulting in a high remaining value of minority carrier lifetime. The difference was assumed to come from whether vacancies were released in the Si matrix during heat treatment. For the Cz-Si, vacancies were assumed to be strongly bound with oxygen atoms with concentrations of 1017 atoms cm−3. Therefore, vacancies were not released during heat treatment, resulting in low remaining N-vacancy complex densities. N-doped Cz-Si are potential materials for IGBTs because of their low densities from thermally activated defects.

DOI： 10.35848/1347-4065/ace011

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記述言語：その他   掲載種別：研究論文（学術雑誌）   出版者・発行元：Japanese Journal of Applied Physics  

Grown-in defect-free wafers are required in silicon semiconductor devices. A point defect concentration simulation was performed along with an experimental investigation, demonstrating a wide range of oxygen concentrations from 1.6 × 1017 to 9.1 × 1017 cm−3 in crystals. Thus, the effect of oxygen atoms in a Czochralski silicon single crystal with grown-in defect behavior was revealed. Consequently, the increasing vacancy concentration trapped by the oxygen atom (oxygen coefficient) was estimated as 4.61 × 10−5 per oxygen atom. Previously, for obtaining the oxygen coefficient, a regression equation assuming thermal equilibrium concentrations of vacancy (V) and interstitial Si (I) was applied to the experimental results. However, the interface shape, thermal stress, and hot-zone structure of the experimental level needed to be arranged; this affected the grown-in defect behavior. In this study, the oxygen coefficient and thermal equilibrium concentration of V and I were determined uniquely without arranging the situations experimental level.

DOI： 10.35848/1347-4065/acde27

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記述言語：その他   掲載種別：研究論文（学術雑誌）   出版者・発行元：Journal of Crystal Growth  

This study investigated the impact of the Marangoni effect of oxygen on the solid–liquid interface shape in the silicon single-crystal growth process by the transverse magnetic-field-applied Czochralski (Cz) method. To this end, the results of a 3D heat and mass transfer analysis were compared with the experimental results. The findings of the study revealed that the Marangoni effect of oxygen affected the solid–liquid interface shape predicted by the simulation. Moreover, with the introduction of this effect, both the solid–liquid interface shape and temperature distribution of the melt were found to be in good agreement with the experimental values.

DOI： 10.1016/j.jcrysgro.2023.127123

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記述言語：その他   掲載種別：研究論文（その他学術会議資料等）   出版者・発行元：7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023  

There are several thermal budget processes for Si-IGBT fabrication, which sometimes cause dislocation propagation. The dislocation propagation depends on temperature and time of the process. In this paper, we analyzed the dislocation propagation in Si wafer during Si-IGBT fabrication process. We also calculated the dislocation density during diffusion process with several temperatures and times, and we confirmed that the lower temperature process causes the smaller dislocation propagation which may carry out the good device performance.

DOI： 10.1109/EDTM55494.2023.10103031

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記述言語：その他   掲載種別：研究論文（学術雑誌）   出版者・発行元：Journal of Crystal Growth  

The effect of the thermal conductivity of a crucible in a silicon carbide physical vapor transport furnace on the dislocation distribution in crystal was investigated using numerical analysis. The numerical analysis includes stress and dislocation propagation calculations based on the Alexander–Haasen model. Modifying the thermal conductivity of the carbon crucible can reduce the dislocation density. It can also homogenize the temperature distribution in the radial distribution in the crystal. The density of dislocations could be further by reduced using a carbon crucible with low thermal conductivity.

DOI： 10.1016/j.jcrysgro.2022.126981

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記述言語：その他   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE Access  

This paper clarifies the effect of gate inductance $L_{g}$ inside IGBT modules on gate voltage spikes when a digital gate driver is employed. Three IGBT modules with different $L_{g}$ were fabricated to implement double pulse tests by conventional gate driving and digital control gate driving with three-step vectors. It was found that the tradeoff between switching loss and voltage/current overshoots can be improved by digital control, but a large gate voltage spike was generated when gate-driving vectors were changed. And the spike voltage $V_{g_{}spike}$ was positively correlated to the $L_{g}$. Although the $V_{g_{}spike}$ can also be suppressed by decreasing the difference of gate driving vectors between the first and the second steps, the improvement of the tradeoff is weakened. Therefore, it is required that the $L_{g}$ inside the IGBT modules should be reduced to suppress the $V_{g_{}spike}$ while improving the tradeoff by the digital gate driver at the same time. Furthermore, by analyzing the oscillation of the $V_{g_{}spike}$ , it indicates that there should be some other stray elements, which couple $L_{g}$ and the stray capacitance inside IGBT chips, affecting the $V_{g_{}spike}$.

DOI： 10.1109/access.2023.3237266

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：ICPE 2023-ECCE Asia - 11th International Conference on Power Electronics - ECCE Asia: Green World with Power Electronics  

This paper proposes a solid-state circuit breaker with avalanche robustness during cutoff operation using series-connection of SiC diodes. Solid-state circuit breakers need to consume energy generated by energy dissipation in the wiring inductance when the cutoff operation. The proposed solid-state circuit breaker improves the cutoff current tolerance by using SiC diodes connected in series to share the avalanche energy. Furthermore, the consuming energy by the solid-state circuit breaker is reduced by maintaining a higher clamping voltage than using single SiC diode during the interruption operation. Experimental results show that the proposed solid-state circuit breaker with two series-connection SiC diodes reduces the consumed avalanche energy by 34.3% compared to using single SiC diode under the same cutoff condition. The proposed solid-state circuit breaker is investigated based on a 400 VDC distribution system with unclamped inductive switching (UIS) condition up to 50 A cutoff current.

DOI： 10.23919/ICPE2023-ECCEAsia54778.2023.10213947

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Proceedings of the International Symposium on Power Semiconductor Devices and ICs  

Failure process by overvoltage stress in GaN-HEMTs is discussed by burst UIS waveforms and C-V characteristics shift. One of the critical disadvantages of GaN-HEMTs is its lack of the UIS withstanding capability, because there is no removal structure of holes, which generated by the avalanche breakdown. Although overvoltage margin for the GaN power converters has been discussed by dynamic breakdown voltage, failure process by overvoltage stress has not been discussed sufficiently. This paper shows that overvoltage stress generated local shunt path between drain and substrate, graduated dielectric breakdown and hole trap/de-trap were observed by repetitive overvoltage stress. These results verify catastrophic failure of GaN-HEMTs by overvoltage stress is ascribed to a percolation process activated by the high-vertical electric field in hetero-epitaxial layers.

DOI： 10.1109/ISPSD57135.2023.10147411

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記述言語：その他   掲載種別：研究論文（学術雑誌）   出版者・発行元：Microelectronics Reliability  

N parallel-connected SiC MOSFETs were investigated to apply to solid-state circuit breakers (SSCB), and it is an extension of a method that was proved valid by experiment of two parallel-connected SiC MOSFETs. The unclamped inductive switching (UIS) test was considered as the emergency interruption of SSCBs in this research. Because of the variations of breakdown voltage among SiC MOSFETs, the current flowing through devices is imbalanced during emergency interruption of SSCBs, which can drive some of the devices into thermal destruction prematurely. There are many compound cases for several SiC MOFETs with a certain maximum breakdown voltage variation. And the worst case, where the breakdown voltage of one device is assumed as the lowest, whereas the other devices have the same breakdown voltage, was extracted from the calculated results of four parallel-connected situation. In the worst case, it was found that the relation of breakdown voltage variations and current capacity is linear. Moreover, the distributions of breakdown voltage were taken as normal distributions. Using the worst case and distributions, a linear relation of breakdown voltage distributions and rated current of an SSCB could be concluded as a function of paralleled-connected numbers (N). Utilizing the function, the necessary breakdown voltage distributions and N of SiC MOSFETs can be evaluated for SSCBs meeting a certain yield ratio and current.

DOI： 10.1016/j.microrel.2022.114737

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記述言語：その他   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE Transactions on Semiconductor Manufacturing  

Nitrogen-doped silicon wafers manufactured using the Czochralski technique (Cz-Si) with an oxygen concentration (OI) of 2.5–5.6 × 1017 atoms cm-3 are heat treated to simulate the conventional and scaled manufacturing processes of insulated gate bipolar transistors (IGBTs). Subsequently, the oxygen precipitation, lifetime, and gate oxide integrity (GOI) of the Cz-Si wafers are evaluated. After the high-temperature heat treatment that simulates the conventional process, the lifetime of the Cz-Si with an OI of 5.6 × 1017 atoms cm-3 only degrades slightly even when oxide precipitates are not detected. In contrast, after the low-temperature heat treatment that simulates the scaled process, oxide precipitates are detected and the lifetime reduces substantially at an OI of 5.6 × 1017 atoms cm-3. The Cz-Si with OI values below 3.3 × 1017 atoms cm-3 are considered suitable materials for IGBTs because no oxide precipitate is formed, and the lifetime is not degraded after high-and low-temperature heat treatments. Upon using GOI evaluation, the nitrogen-doped Cz-Si wafers are found to exhibit a breakdown voltage equal to that of an annealed Cz-Si wafer conventionally used for IGBTs. Therefore, nitrogen-doped Cz-Si wafers with OI below 3.3 × 1017 atoms cm-3 are potential materials for conventional and scaled IGBTs.

DOI： 10.1109/TSM.2022.3199862

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE Transactions on Electron Devices  

Unclamped inductive switching (UIS) robustness of SiC devices with parallel-connected varistor was evaluated to design the cutoff current capability of solid-state circuit breakers (SSCBs). Because the operation of UIS tests is similar to that in the interruption of SSCBs, UIS tests of SiC devices without varistor and with a parallel-connected varistor were implemented. It was found that the cutoff current of SiC devices with the varistor was much larger than that without varistor. The effect of varistor on the increase of cutoff current depended on the device type and rating current. The cutoff current was 3-6 times higher for planar MOSFETs and 5-10 times higher for trench MOSFETs compared with no varistor condition. In contrast, the effect of varistor for JFET was small because the gate drive condition strongly affected the current switching time from SiC-JFET to varistor. The index of rating current for cutoff current capability was changed by parallel varistor connection because the destruction mechanism of SiC devices was changed because of the change in self-heating timing during the UIS.

DOI： 10.1109/TED.2022.3200637

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE Journal of the Electron Devices Society  

A new parameter optimization method using zoomed response surface (RS) is proposed for automatic design of low-voltage power MOSFET. Low-voltage MOSFET characteristics have been improved continuously considering with not only low power loss but also low cost to answer request to high-performance system. Complicated requirements lead long development schedule and low yield. Model-based design and machine learning are prospective method to answer the problem. However, reported methods require many simulation numbers (>1000) for training to obtain high accuracy, and it is difficult to optimize parameters considering the process margin at the same time. This article shows a simple design method using zoomed RS. Five parameters were automatically designed, taking account to process margin with simulation number of 130 only.

DOI： 10.1109/JEDS.2022.3187151

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE Journal of the Electron Devices Society  

Scaling design effects on surface buffer (SB) insulated gate bipolar transistor (IGBT) is analyzed not only for power loss reduction but also for switching controllability and robustness using TCAD simulation. Although the scaling design improves turn-off loss and on-state voltage drop V-ce(sat) trade-off due to injection enhancement (IE) effect, turn-on surge current is increased by the enhancement of negative gate capacitance due to thin gate oxide. Dual gate control improves turn-on switching controllability by hole current path control. Short circuit robustness is improved by the scaling design, because the saturation current is decreased with the scaling design due to pinch-off of the n-MOS channel. From these results, the scaling design is effective in improving the SB-IGBT characteristics including high robustness.

DOI： 10.1109/JEDS.2021.3129162

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記述言語：その他   掲載種別：研究論文（その他学術会議資料等）   出版者・発行元：2022 IEEE Energy Conversion Congress and Exposition, ECCE 2022  

This paper proposes a current limit feature for a multi-functional SiC circuit breaker device with a “dual thyristor” structure. The proposed feature provides the device not only with a fast-response current breaking operation but also with the current limiting function, including supplying a constant current to the load and preventing the detection of inrush currents. The proposed feature is suitable for replacing mechanical circuit breakers in initial charging circuits for the rectifiers and a safety equivalent in case of overcurrent accidents. The proposed method achieves various constant currents by simply varying the gate-drive circuit with adjustable parameters of an additional MOSFET. Experimental results verified that the device with the current limit feature reduces the inrush current to up to 22.6% of capacitive load condition using a 500 VDC circuit system.

DOI： 10.1109/ECCE50734.2022.9948054

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記述言語：その他   掲載種別：研究論文（その他学術会議資料等）   出版者・発行元：IEEE Workshop on Wide Bandgap Power Devices and Applications in Europe, WiPDA Europe 2022  

Unclamped inductive switching (UIS) robustness of SiC MOSFETs with parallel connected varistor was evaluated to design the cutoff current capability of solid-state circuit breakers. Because the operation of UIS tests is similar to that in the interruption of solid-state circuit breakers, UIS tests of SiC MOSFETs without varistor and with a parallel-connected varistor were implemented. It was found that the cutoff current of SiC MOSFETs with the varistor was 3 to 6 times larger than that without varistor. The index of rating current for cutoff current capability was changed by parallel varistor connection, because the destruction mechanism of SiC MOSFETs was changed because of the change in self-heating timing during the UIS. From dependence of cutoff current on rating current, load inductance and varistor voltage, it is verified that the cutoff current of SiC MOSFET with varistor was limited by saturation current and current filament.

DOI： 10.1109/WiPDAEurope55971.2022.9936060

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記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

掲載種別：研究論文（国際会議プロシーディングス）  

This paper presents the short circuit performance of a novel SiC circuit breaker device, which is based on the 'thyristor dual' functionality. The developed device structure is motivated with regard to manufacturing aspects and electrical requirements. Furthermore, the basic 'thyristor dual' operation is elaborated on the basis of quasi-static electrical measurements of a fabricated prototype. The proposed self-sensing and self-triggering devices make auxiliary circuitry like sensors and micro-controllers expendable and practically have no propagation delay. As a result, short circuit clearance within 122 ns at 800 V is demonstrated in experiments. Moreover, by utilisation of a third device terminal, a temporary current limiter functionality can be obtained. The scalability of the current limit value is discussed on the basis of measurements in time domain. The maximum current limit value achieved is 7.4 times higher than the trigger current level of the circuit breaker device. Additionally, the same circuit configuration which is used for the current limiting mode, allows to remotely reset the circuit breaker after it turned to blocking-state. This opens up a wide range of possibilities to enhance the circuit breaker with intelligent functionalities.

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記述言語：その他   掲載種別：研究論文（その他学術会議資料等）   出版者・発行元：Proceedings of the International Symposium on Power Semiconductor Devices and ICs  

This work presents the switching performance of a novel solid-state circuit breaker device suitable for DC-applications up to 800 V. These "dual thyristor"devices are manufactured employing a 4H-SiC JFET technology. With respect to scalability, the influence of specific design parameters on the quasi-static output characteristics are discussed along with corresponding fabrication aspects. In order to investigate the switching performance, clamped and unclamped inductive switching (CIS and UIS) experiments at up to 800 V are carried out. In case of CIS, current clearance is achieved within 642 ns after the self-sensed trigger event at 1.75 A. The UIS experiments reveal stable current handling capability during avalanche.

DOI： 10.1109/ISPSD49238.2022.9813628

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記述言語：英語   掲載種別：研究論文（その他学術会議資料等）   出版者・発行元：Proceedings of the International Symposium on Power Semiconductor Devices and ICs  

Design of trench gate and p-column position in Superjunction (SJ)-IGBTs are discussed to improve the trade-off characteristics between surge voltage/current and turn-off/-on losses. Power electronics systems require not only low power loss but also low EMI noise for high cost performance by system downsizing. Although SJ-IGBTs are attractive for low loss operation due to thin drift layer and fast removal of the excess carriers through the p- and n-columns at the turn-off operation, the switching trade-off characteristics of SJ-IGBTs compared with the conventional IGBT and the improvement design have not been discussed sufficiently. This paper shows better switching trade-off compared with a conventional IGBT can be obtained by the trench gate and p-column designs due to management of the gate capacitance and hole current flow, because negative gate capacitance influences on not only turn-on switching but also turn-off switching.

DOI： 10.1109/ISPSD49238.2022.9813643

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記述言語：その他   掲載種別：研究論文（その他学術会議資料等）   出版者・発行元：Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC  

This paper proposes a solid-state DC circuit breaker composed of SiC MOSFETs and a SiC diode, based on the principle of avalanche voltage clamping. To realize a solid-state DC circuit breaker, it is necessary to reduce the conduction loss and increase the breaking capability. A parallel connection of power semiconductor devices is the most suitable configuration that can meet these requirements. However, in such a configuration, the current balance during current interruption may be affected by the difference in the breakdown voltage characteristics of the power semiconductor devices. The proposed solid-state DC circuit breaker is clamped using a SiC merged pin Schottky diode with high avalanche tolerance and robust characteristics under repetitive avalanche events. Experimental results from an unclamped inductive switching test circuit with a 400-V DC distribution system show that the proposed solid-state DC circuit breaker can interrupt currents up to 50-A.

DOI： 10.1109/APEC43599.2022.9773380

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記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

掲載種別：研究論文（国際会議プロシーディングス）  

This paper aims to clarify the effect of parallel-connected varistor on unclamped inductive switching (UIS) robustness of SiC MOSFETs to improve the cut-off current capability of solid-state circuit breakers (SSCB). Because the operation of UIS tests is similar to that in the interruption of SSCB, UIS tests of SiC MOSFETs without varistor and with a parallel-connected varistor were implemented. It was found that the cut-off current of SiC MOSFETs with the varistor is much larger than that of SiC MOSFETs without varistor. The effect of varistor on increase of cut-off current depends on the MOS-gate type. The cut-off current is 3-5 times higher for planar-gate devices and 5-10 times higher for trench-gate devices compared with no varistor condition. To analyze mechanism of cut-off current increased by the varistor, the junction temperature in UIS tests with and without the varistor was estimated by simulation using experimental wave-forms. The simulation results show that the destruction mechanism of SiC MOSFETs is changed by varistor connection due to change of self-heating timing during the UIS.

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記述言語：その他   出版者・発行元：Japanese Journal of Applied Physics  

In this paper, the turn-on characteristics of the 1.2 kV Trench IGBT (TIGBT) and the 1.2 kV Trench Clustered IGBT (TCIGBT) are investigated through TCAD simulations and experiments. The TCIGBT shows much lower turn-on energy loss (E on) due to higher current gain than an equivalent TIGBT and the negative gate capacitance effect is effectively suppressed in the TCIGBT by its self-clamping feature and PMOS action. In addition, the impact of 3D scaling rules on the turn-on performance of TIGBT and TCIGBT is analyzed in detail. Simulation results show that scaling rules result in a significant reduction of E on in both TIGBT and TCIGBT. Furthermore, the experimental results indicate that TCIGBT technology is well suited for high current density operations with low power losses. Compared to the state-of-the-art IGBT technology, an 18% reduction of total power loss can be achieved by the TCIGBT operated at 300 A cm-2 and 175 °C.

DOI： 10.35848/1347-4065/ac40aa

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出版者・発行元：ETG-Fachbericht  

This paper aims to clarify the effect of parallel-connected varistor on unclamped inductive switching (UIS) robustness of SiC MOSFETs to improve the cut-off current capability of solid-state circuit breakers (SSCB). Because the operation of UIS tests is similar to that in the interruption of SSCB, UIS tests of SiC MOSFETs without varistor and with a parallel-connected varistor were implemented. It was found that the cut-off current of SiC MOSFETs with the varistor is much larger than that of SiC MOSFETs without varistor. The effect of varistor on increase of cut-off current depends on the MOS-gate type. The cut-off current is 3-5 times higher for planar-gate devices and 5-10 times higher for trench-gate devices compared with no varistor condition. To analyze mechanism of cut-off current increased by the varistor, the junction temperature in UIS tests with and without the varistor was estimated by simulation using experimental wave-forms. The simulation results show that the destruction mechanism of SiC MOSFETs is changed by varistor connection due to change of self-heating timing during the UIS.

Scopus

出版者・発行元：24th European Conference on Power Electronics and Applications, EPE 2022 ECCE Europe  

This paper presents the short circuit performance of a novel SiC circuit breaker device, which is based on the 'thyristor dual' functionality. The developed device structure is motivated with regard to manufacturing aspects and electrical requirements. Furthermore, the basic 'thyristor dual' operation is elaborated on the basis of quasi-static electrical measurements of a fabricated prototype. The proposed self-sensing and self-triggering devices make auxiliary circuitry like sensors and micro-controllers expendable and practically have no propagation delay. As a result, short circuit clearance within 122 ns at 800 V is demonstrated in experiments. Moreover, by utilisation of a third device terminal, a temporary current limiter functionality can be obtained. The scalability of the current limit value is discussed on the basis of measurements in time domain. The maximum current limit value achieved is 7.4 times higher than the trigger current level of the circuit breaker device. Additionally, the same circuit configuration which is used for the current limiting mode, allows to remotely reset the circuit breaker after it turned to blocking-state. This opens up a wide range of possibilities to enhance the circuit breaker with intelligent functionalities.

Scopus

Web of Science

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1016/j.microrel.2021.114237

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1016/j.microrel.2021.114270

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： doi:10.23919/SISPAD49475.2020.9241627

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/JEDS.2021.3079396

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1016/j.jcrysgro.2021.126236

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/LED.2021.3075657

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/LED.2021.3075657

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： doi:10.35848/1347-4065/abc1d0

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.35848/1347-4065/abe801

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.35848/1347-4065/abebc1

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.23919/ISPSD50666.2021.9452240

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/EDTM50988.2021.9420922

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.35848/1347-4065/abe801

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/TPEL.2020.3014560

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/tpel.2020.3014560

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1016/j.jcrysgro.2020.126015

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： doi:10.1016/j.jcrysgro.2020.126015

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：日本語   掲載種別：研究論文（学術雑誌）  

DOI： https://doi.org/10.35848/1347-4065/abebc1

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/IEDM13553.2020.9371909

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/LED.2020.3034898

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/led.2020.3034898

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1016/j.microrel.2020.113776

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.35848/1347-4065/abc1d0

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.35848/1347-4065/abc1d0

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/ted.2020.3007594

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/TED.2020.3007594

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.23919/SISPAD49475.2020.9241627

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/ISPSD46842.2020.9170118

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/ISPSD46842.2020.9170129

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/ISPSD46842.2020.9170035

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/TED.2020.3002510

記述言語：その他   掲載種別：研究論文（その他学術会議資料等）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/TED.2020.2999874

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/TED.2020.3002510

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/TED.2020.2999874

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/LED.2020.2991927

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/LED.2020.3000239

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/LED.2020.3000239

記述言語：英語   掲載種別：研究論文（学術雑誌）  

This paper discusses the edge termination design of high-voltage insulated gate bipolar transistors with large current turn-off switching operation. We discovered that the phenomena of current crowding and impact ionization act as separated heat sources and induce one local hot spot that causes thermal destruction in the edge termination during the turn-off switching period. Optimizing the backside hole injection efficiency and relaxing the electric field of the surface pn junction edge at the edge termination region prevent the above problems. These concepts benefit the dynamic ruggedness under hard-switching conditions. This paper presents our novel edge termination design that achieves robust turn-off capability without deteriorating other performances of the device.

DOI： 10.1016/j.microrel.2020.113635

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/APEC39645.2020.9124293

記述言語：その他   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/TED.2020.2990387

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/TED.2020.2990387

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/TSM.2020.2972369

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1016/j.jcrysgro.2020.125594

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.35848/1347-4065/ab7414

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.4028/www.scientific.net/MSF.1004.1010

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1016/j.jcrysgro.2019.125404

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1016/j.jcrysgro.2019.125405

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/IEDM19573.2019.8993596

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/TED.2019.2941710

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/ASICON47005.2019.8983633

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1016/j.microrel.2019.113417

記述言語：英語  

DOI： 10.1016/j.jcrysgro.2019.04.018

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.7567/1347-4065/ab1c78

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1541/ieejjia.8.480

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ispsd.2019.8757640

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ispsd.2019.8757626

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.7567/1347-4065/aafd90

記述言語：英語  

DOI： 10.7567/1347-4065/aafd90

記述言語：英語  

DOI： 10.1109/ICMTS.2019.8730922

記述言語：英語  

DOI： 10.1016/j.jcrysgro.2018.11.017

記述言語：英語  

DOI： 10.1109/IEDM.2018.8614491

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

記述言語：英語  

DOI： 10.1109/VLSIC.2018.8502399

記述言語：英語  

DOI： 10.1109/ESSDERC.2018.8486870

記述言語：英語  

DOI： 10.1016/j.jcrysgro.2018.07.020

記述言語：英語  

DOI： 10.1016/j.microrel.2018.07.023

記述言語：英語  

DOI： 10.1016/j.jcrysgro.2018.02.034

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1049/iet-pel.2017.0376

記述言語：英語  

DOI： 10.1016/j.microrel.2018.02.012

記述言語：英語  

DOI： 10.1016/j.jcrysgro.2018.01.020

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ASICON.2017.8252681

記述言語：英語  

DOI： 10.1109/SBMicro.2017.7990846

記述言語：英語  

DOI： 10.1109/IEDM.2016.7838390

記述言語：英語  

DOI： 10.1016/j.microrel.2016.07.049

記述言語：英語  

DOI： 10.1109/APEC.2016.7468295

記述言語：英語  

DOI： 10.1002/crat.201500344

記述言語：英語  

Design and Analysis of a New Evaluation Circuit for Capacitors Used in a High-Power Three-Phase Inverter
DC-link capacitors in power electronic converters are a major constraint on improvement of power density as well as reliability. Evaluation of the dc-link capacitors in terms of power loss, ageing, and failure rate will play an important role in design stages of the next-generation power converters. This paper proposes a new evaluation circuit for dc-link capacitors used in a high-power three-phase inverter, which is intended for testing power loss, failure rate, ageing, and so on. The evaluation circuit produces a practical ripple current waveform and a dc bias voltage into a capacitor under test, in which the ripple current is equivalent to that generated by the three-phase inverter on the dc link. The evaluation circuit employs a full-scale current-rating and downscaled voltage-rating inverter for producing the ripple current, so that the power rating of the evaluation circuit is much smaller than that of a full-scale current-rating and full-scale voltage-rating inverter. Theoretical analysis and simulated results verify the effectiveness of new evaluation circuit.

DOI： 10.1109/TIE.2015.2511097

記述言語：日本語  

記述言語：英語  

DOI： 10.1109/CSICS.2015.7314489

記述言語：英語  

DOI： 10.1109/ECTC.2015.7159590

記述言語：英語  

DOI： 10.1109/ISPSD.2015.7123463

記述言語：英語  

Theoretical Loss analysis of power converters with 1200 v class Si-IGBT and SiC-MOSFET
Power converter efficiencies of 1200-V class Si-IGBT/SiC-SBD hybrid pairs and a SiCMOSFET/ SiC-SBD pair were theoretically compared at a switching frequency above the limit of human hearing (20 kHz). Si-IGBT losses were simulated by TCAD. SiC device losses were calculated by analytical minimum loss models. Calculated efficiencies of the full-SiC pair were slightly higher than that of the hybrid pairs at conventional current densities less than 200 A/cm². At a higher current density of 400 A/cm², the hybrid pairs have a potential of high performance which is comparable with the full-SiC efficiency.

記述言語：英語  

High-speed dicing of SiC wafers by femtosecond pulsed laser
A novel dicing technology that utilizes femtosecond pulsed lasers (FSPLs) is demonstrated as a high-speed and cost-effective dicing process for SiC wafers. The developed dicing process consists of cleavage groove formation on a SiC wafer surface by the FSPL, followed by chip separation by pressing a cleavage blade. The effective FSPL scan speed on the SiC surfaces was 33 mm/s. Kerf loss is negligible in the developed FSPL dicing process. In addition, the residual lattice strain in the FSPL-diced SiC chips was comparably small to that of the conventional mechanical process using diamond saws, due to the absence of the lattice heating effect in femtosecond-laser processes.

DOI： 10.4028/www.scientific.net/MSF.821-823.524

記述言語：英語  

DOI： 10.7567/JJAP.53.069202

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/IPEC.2014.6869568

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1063/1.4872242

記述言語：英語  

DOI： 10.1109/IPEC.2014.6869671

記述言語：英語  

DOI： 10.1016/j.jcrysgro.2013.03.036

記述言語：英語  

Impact of semiconductor on diamond structure for power supply on chip applications
In this study, we assessed a semiconductor (silicon or GaN)-on-diamond (SeOD) structure and compared it with a conventional silicon on insulator (SOI) structure, i.e., diamond, for power-supply-on-chip (power-SoC) applications by numerical simulations. The SeOD structure has thermal advantages over the conventional SOI structure without degrading electrical characteristics even using a thin diamond film (0.3 μm).

DOI： 10.7567/JJAP.53.04EP16

記述言語：英語  

DOI： 10.1063/1.4828996

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.1109/ECCE.2013.6646893

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.7567/APEX.6.091002

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

記述言語：英語  

DOI： 10.1016/j.jcrysgro.2011.11.019

記述言語：英語  

DOI： 10.1016/j.jcrysgro.2011.09.061

記述言語：英語  

DOI： 10.1016/j.jcrysgro.2011.11.052

記述言語：日本語  

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

記述言語：日本語  

記述言語：英語  

DOI： 10.1016/j.jcrysgro.2012.01.023

記述言語：英語  

DOI： 10.1021/cr200257z

記述言語：英語  

DOI： 10.1021/cg201684e

記述言語：日本語  

記述言語：英語  

DOI： 10.1016/j.jcrysgro.2011.03.059

記述言語：英語  

Numerical investigation of the growth rate enhancement of SiC crystal growth from silicon melts
Numerical study has been applied to analyze the high temperature solution growth process for bulk silicon carbide (SiC) crystal growth. A twodimensional axisymmetric model for 2-in. SiC crystal growth was used for this study. The purpose of this paper is to investigate the possible approaches to enhance the growth rate in this process. In particular, we studied the effect of an AC magnetic field on the carbon transport to the crystal growth interface. The results revealed that the carbon flux to the growing crystal is strongly affected by the coil position and the applied frequency. If these two process parameters are properly chosen, we show that the carbon flux at the growing front, and thus the growth rate of SiC, can be enhanced.

DOI： 10.1143/JJAP.50.035603

記述言語：英語  

DOI： 10.1016/j.jcrysgro.2010.10.022

記述言語：英語  

DOI： 10.1016/j.jcrysgro.2010.08.032

記述言語：英語  

DOI： 10.1016/j.jcrysgro.2010.02.027

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.4028/www.scientific.net/MSF.615-617.655

記述言語：日本語  

記述言語：英語  

DOI： 10.1016/j.jcrysgro.2008.09.105

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.4028/3-908453-11-9.907

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.4028/3-908453-11-9

記述言語：英語  

DOI： 10.1109/TED.2008.926666

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1143/JJAP.46.5342

記述言語：英語  

DOI： 10.1016/j.jcrysgro.2006.12.022

記述言語：英語  

DOI： 10.1016/j.jcrysgro.2006.12.018

記述言語：英語  

DOI： 10.1103/PhysRevB.75.115321

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

DOI： 10.4028/www.scientific.net/MSF.527-529.803

記述言語：英語   掲載種別：研究論文（その他学術会議資料等）  

記述言語：英語  

DOI： 10.1002/cvde.200606469

記述言語：日本語  

記述言語：日本語  

DOI： 10.19009/jjacg.33.5_403

記述言語：英語  

DOI： 10.1149/1.2170546

記述言語：英語  

DOI： 10.1016/j.mee.2005.10.033

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語  

DOI： 10.1016/j.jcrysgro.2004.11.071

記述言語：英語  

DOI： 10.1016/j.jcrysgro.2004.11.072

記述言語：日本語  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語  

DOI： 10.1063/1.1591062

記述言語：英語  

DOI： 10.1016/S0022-0248(03)01177-1

記述言語：日本語  

昇華法によるSiC単結晶成長は,2000℃を超える黒鉛るつぼで閉じられた閉鎖空間でのブラックボックスプロセスであり,これまで経験則に基づく技術開発が行われてきた.そのため,大口径化・高品質化に対して解決すべき技術課題が多数残されている.今回,数値解析を結晶成長炉内の可視化技術として適用し,実際の昇華法による結晶成長時の温度・昇華ガス濃度・応力分布の解析を行い,SiC単結晶品質の向上に資してきたので,その結果を報告する.

記述言語：英語  

Gallium nitride (GaN) initial nucleation kinetics by the influence of SiC(0 0 0 1)_Si surface structure has been investigated. The Ga induced √3×√3R30° and 3×3 surface reconstructions are found to be more efficacious for GaN growth. During the initial stage of GaN/4H-SiC(0 0 0 1)_Si growth by molecular-beam epitaxy, coherent polygon islands grow wide (∼40 nm) along the lateral directions. These coherent islands develop 2D growth through early coalescence as evidenced by the in situ reflection high-energy electron diffraction observation. The control of Ga-adatom migration and the adsorption of 1/3 and 1 monolayer (ML) of Ga-adatom govern the surface morphology of the GaN layers. The bulk surfaces of (1 × 1) and (2 × 1) introduces incoherent nuclei, resulting in a delay of GaN coalescence, exhibits rough growth front and poor surface morphology.

DOI： 10.1016/S0039-6028(03)00016-5

記述言語：英語   掲載種別：研究論文（学術雑誌）  

The Capacitance diaphragm gauge (CDG) is one of the most important vacuum gauges in low and middle vacuum ranges. The difference of temperature between the sensor head and the vacuum chamber gives a non-linear sensitivity of the gauge depending on the pressure due to thermal transpiration effect. Change in the sensitivity of about 4% between molecular flow regime and viscous flow regime is significant for metrological use of the gauge. In this study, by using a DSMC method, pressure distribution in the connecting tube of the gauge was obtained under the pressure range from molecular flow regime to viscous flow regime with taking account of temperature distribution along the connecting tube. It was in good agreement with the pressure dependence of sensitivity obtained by static expansion system experimentally. Furthermore, influence of gas-surface interaction on the thermal transpiration was also discussed.

記述言語：英語   掲載種別：研究論文（学術雑誌）  

The Capacitance diaphragm gauge is one of the most important vacuum gauges in low and middle vacuum ranges. The difference of temperature between the sensor head and the vacuum chamber gives a non-linear sensitivity of the gauge due to thermal transpiration effect. This sensitivity depends not only on pressure but also gas species. It is supposed that under the same condition of gas-surface interaction, the sensitivity should be normalized by mean free path independently of gas species. However, the sensitivity normalized by mean free path also depends on gas species. In this study, by using DSMC method, the influence of gas-surface interaction on thermal transpiration was analyzed. In case of random reflection model, the sensitivity has non-linearity and depends on mean free path. On the other hand, in case of a perfectly elastic reflection model, the sensitivity is constant regardless mean free path. In case of complex reflection that is composed of random and elastic reflections, as increasing the elastic reflection component, the sensitivity decreases from that of random reflection to elastic reflection.

記述言語：英語  

DOI： 10.1016/S0167-577X(02)00783-8

記述言語：英語  

DOI： 10.1016/S0042-207X(02)00212-9

記述言語：日本語  

Silicon carbide (SiC) is the most promising material for high power, high frequency and low loss device applications. In order to realize SiC devices, it is necessary to improve the grown crystal quality. SiC bulk single crystal is grown by sublimation method, inside a closed carbon crucible. Because of the black box process, the optimization of sublimation process is difficult. From this point view the in situ X ray topography system was developed to observe the phenomena inside a crucible during the growth. The numerical simulation was also applied. From these observations, the heat and mass transfer in a crucible was discussed involving in the macroscopic crystal quality, such as crystal diameter, growing surface shape, and also in the microscopic crystal quality such as defect generations.

DOI： 10.19009/jjacg.29.5_431

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Microwave plasma chemical vapor deposition was performed aiming at low temperature homoepitaxial growth of 4H-SiC thin films. The growth rate of the deposited film depended strongly on the SiH₄ flow rate, and a smooth surface could not obtained at high SiH₄ flow rate. The surface morphology was also affected by the C/Si ratio. A high C/Si ratio was required to obtain smooth SiC films. Single crystalline 4H-SiC film growth has been achieved at a temperature as low as 970°C by growing under very high C/Si ratio (C/Si = 175) with a very low SiH₄ flow rate (0.004sccm).

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語  

記述言語：英語  

DOI： 10.4028/www.scientific.net/msf.389-393.75

記述言語：英語  

DOI： 10.1016/S0022-0248(01)01578-0

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：日本語  

記述言語：英語  

New crucible design for SiC single crystal growth by sublimation
SiC bulk single crystal growth by sublimation was investigated. A new crucible design, double-walled crucible, was proposed, and its effect was confirmed numerically and experimentally. On the point of heat transfer in a growth cavity, double-walled crucible is better than conventional crucible. With a double-walled crucible, temperature of seed and source surfaces could be kept constant with better uniformity than that with a conventional crucible. It was deduced that a crystal growth rate could be kept constant with flat surface. Furthermore, in case of a double walled crucible, crystal enlarged rapidly with less inclusion. As the results, a double-walled crucible is useful to grow high quality SiC single crystal by sublimation.

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1016/S0022-0248(00)00958-1

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語  

DOI： 10.1016/S0022-0248(00)00733-8

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：日本語  

記述言語：英語  

Rapid enlargement of SiC single crystal using a cone-shaped platform
We investigated the enlargement of SiC single crystal during physical vapor transport growth by modifying the shape of graphite lid. The single crystals grown on the cone-shaped platform were larger in diameter than those grown on the conventional one. The enlargement of ingot is discussed in terms of the dual role of polycrystals during crystal growth: (i) it provides a platform for single crystal and (ii) an obstacle to the lateral growth of ingot. The dependence of the broadening angle (β) of single crystal on the taper angle (θ) of the cone-shaped platform was also investigated and an optimum angle at a given growth condition found.

DOI： 10.1016/S0022-0248(99)00754-X

記述言語：英語  

DOI： 10.1063/1.1150698

記述言語：英語  

記述言語：英語  

記述言語：日本語  

記述言語：日本語  

記述言語：日本語  

DOI： 10.1299/jsmemag.102.969_492_2

記述言語：英語  

記述言語：英語  

記述言語：日本語  

DOI： 10.1299/jsmemag.101.957_595_2

記述言語：英語  

DOI： 10.1098/rsta.1998.0195

記述言語：英語  

DOI： 10.1016/S0022-0248(97)00440-5

記述言語：日本語  

DOI： 10.1299/jsmemag.100.945_868_2

記述言語：日本語  

In space, it could be possible to make high quality, large and new functional materials. For the material processing such as melt growth of materilas for electrical devices and oxides, it is very important to understand and control the convective phenomena in melt. In this point of view, Marangoni convection in a liquid bridge which simulates the half floating zone was observed under microgravity conditions during parabolic filght. The experimental resutls was compared with that of numerical simulations. The developing processes of flow filed and temperature field were made clear. Furthermore, it coud be possible to estimate the pehnomena which might be happened as long time passed by numerical simulations. It means that numerical simulation is very usufel for developing the materila processing in space.

記述言語：日本語  

3rd China-Japan Workshop on Microgravity Science

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1016/S0017-9310(96)00309-2

記述言語：英語  

DOI： 10.1016/S0022-0248(96)00386-7

記述言語：英語  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1252/jcej.27.65

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1252/jcej.26.754

記述言語：英語  

Momentum, with Heat and Mass Transfer Through Gas-Liquid Interface with Accelerated Interfacial Velocity
Effects of interfacial velocity on interfacial momentum, heat and mass transfer through a gas-liquid interface were quantitatively investigated. The rates of momentum, heat and mass transfer depend not only on the magnitude of the interfacial velocity but also on the change of acceleration in interfacial velocity. In addition, by considering the interfacial tension gradient to be the cause of interfacial acceleration, the effect of the interfacial tension gradient on interfacial velocity, interfacial momentum, heat and mass transfer were also quantitatively investigated. Both the interfacial velocity and the rates of momentum, heat and mass transfer depend not only on the magnitude of the interfacial tension gradient but also on the change of interfacial tension.

DOI： 10.1252/jcej.26.649

記述言語：英語  

記述言語：英語  

開催年月日： 2019年3月

記述言語：英語   会議種別：シンポジウム・ワークショップ パネル（公募）  

国名：グアム  

開催年月日： 2018年11月

記述言語：英語   会議種別：口頭発表（一般）  

国名：日本国  

開催年月日： 2018年10月

記述言語：英語   会議種別：口頭発表（一般）  

国名：アメリカ合衆国  

開催年月日： 2017年11月

記述言語：日本語   会議種別：口頭発表（一般）  

開催地：鹿児島大学   国名：日本国  

Three dimensionally scaled IGBTs that have a scaling factor of 3 (k=3) with respect to current commercial products (k=1) were fabricated for the first time. The scaling was applied to the lateral and vertical dimensions as well as the gate voltage. A significant decrease in ON resistance, -- V_CEsat reduction from 1.70 to 1.26 V -- was experimentally confirmed for the 3D scaled IGBTs.

開催年月日： 2017年10月

記述言語：英語   会議種別：口頭発表（一般）  

国名：中華人民共和国  

開催年月日： 2017年9月

記述言語：英語   会議種別：口頭発表（一般）  

国名：日本国  

開催年月日： 2017年9月

記述言語：英語   会議種別：口頭発表（一般）  

国名：日本国  

開催年月日： 2017年7月

記述言語：英語   会議種別：口頭発表（一般）  

国名：ドイツ連邦共和国  

開催年月日： 2017年7月

記述言語：英語   会議種別：シンポジウム・ワークショップ パネル（公募）  

国名：ドイツ連邦共和国  

開催年月日： 2017年5月

記述言語：英語   会議種別：口頭発表（一般）  

国名：ドイツ連邦共和国  

開催年月日： 2017年3月

記述言語：英語   会議種別：口頭発表（一般）  

国名：ドイツ連邦共和国  

開催年月日： 2021年10月

記述言語：英語   会議種別：口頭発表（一般）  

国名：フランス共和国  

開催年月日： 2021年10月

記述言語：英語   会議種別：口頭発表（一般）  

国名：フランス共和国  

開催年月日： 2021年5月 - 2021年6月

記述言語：英語   会議種別：シンポジウム・ワークショップ パネル（公募）  

国名：日本国  

開催年月日： 2021年4月

記述言語：英語   会議種別：口頭発表（一般）  

国名：中華人民共和国  

開催年月日： 2021年2月

記述言語：日本語   会議種別：口頭発表（一般）  

開催地：オンライン   国名：日本国  

開催年月日： 2021年2月

記述言語：その他  

国名：日本国  

開催年月日： 2020年12月

記述言語：日本語   会議種別：シンポジウム・ワークショップ パネル（公募）  

開催地：オンライン   国名：日本国  

開催年月日： 2020年12月

記述言語：その他  

国名：日本国  

開催年月日： 2020年12月

記述言語：日本語   会議種別：シンポジウム・ワークショップ パネル（公募）  

開催地：オンライン   国名：日本国  

開催年月日： 2020年11月

記述言語：英語   会議種別：口頭発表（一般）  

国名：中華人民共和国  

開催年月日： 2020年10月

記述言語：英語   会議種別：口頭発表（一般）  

国名：ギリシャ共和国  

開催年月日： 2020年9月

記述言語：英語   会議種別：口頭発表（一般）  

国名：日本国  

開催年月日： 2020年9月

記述言語：その他  

国名：日本国  

開催年月日： 2020年9月 - 2020年10月

記述言語：英語   会議種別：口頭発表（一般）  

国名：日本国  

開催年月日： 2020年9月 - 2020年10月

記述言語：その他  

国名：日本国  

開催年月日： 2020年9月

記述言語：日本語   会議種別：口頭発表（一般）  

開催地：オンライン   国名：日本国  

開催年月日： 2020年9月

記述言語：その他  

国名：日本国  

開催年月日： 2020年9月

記述言語：日本語   会議種別：口頭発表（一般）  

開催地：オンライン   国名：日本国  

開催年月日： 2020年9月

記述言語：英語   会議種別：口頭発表（一般）  

国名：オーストリア共和国  

開催年月日： 2020年9月

記述言語：その他  

国名：オーストリア共和国  

Dynamic Avalanche Free Super Junction-TCIGBT for High Power Density Operation

開催年月日： 2020年9月

記述言語：その他  

国名：オーストリア共和国  

開催年月日： 2020年9月

記述言語：英語   会議種別：口頭発表（一般）  

国名：オーストリア共和国  

開催年月日： 2020年9月

記述言語：英語   会議種別：口頭発表（一般）  

国名：オーストリア共和国  

開催年月日： 2020年3月

記述言語：英語   会議種別：口頭発表（一般）  

国名：アメリカ合衆国  

開催年月日： 2020年3月

記述言語：その他  

国名：アメリカ合衆国  

開催年月日： 2019年12月

記述言語：英語   会議種別：口頭発表（一般）  

国名：アメリカ合衆国  

開催年月日： 2019年11月

記述言語：日本語   会議種別：口頭発表（一般）  

開催地：仙台   国名：日本国  

開催年月日： 2019年11月

記述言語：日本語   会議種別：口頭発表（一般）  

開催地：仙台   国名：日本国  

開催年月日： 2019年10月 - 2019年11月

記述言語：日本語   会議種別：口頭発表（一般）  

開催地：大阪   国名：日本国  

開催年月日： 2019年9月 - 2019年10月

記述言語：英語  

国名：日本国  

開催年月日： 2019年9月

記述言語：日本語   会議種別：口頭発表（一般）  

開催地：札幌   国名：日本国  

開催年月日： 2019年9月

記述言語：日本語   会議種別：口頭発表（一般）  

開催地：札幌   国名：日本国  

開催年月日： 2019年9月

記述言語：日本語   会議種別：口頭発表（一般）  

開催地：札幌   国名：日本国  

開催年月日： 2019年9月

記述言語：英語   会議種別：口頭発表（一般）  

国名：日本国  

開催年月日： 2019年9月

記述言語：英語  

国名：日本国  

開催年月日： 2019年7月 - 2019年8月

記述言語：英語   会議種別：口頭発表（一般）  

国名：アメリカ合衆国  

開催年月日： 2019年7月 - 2019年8月

記述言語：英語  

国名：アメリカ合衆国  

開催年月日： 2019年7月 - 2019年8月

記述言語：英語   会議種別：口頭発表（一般）  

国名：アメリカ合衆国  

開催年月日： 2019年5月

記述言語：英語  

国名：中華人民共和国  

開催年月日： 2019年5月

記述言語：英語  

国名：中華人民共和国  

開催年月日： 2019年5月

記述言語：英語   会議種別：口頭発表（一般）  

国名：ドイツ連邦共和国  

開催年月日： 2019年3月

記述言語：日本語   会議種別：口頭発表（一般）  

開催地：東京   国名：日本国  

ＣＺ炉内のＣＯガス濃度をガスクロマトグラフにより測定した。炉内の脱ガスによって発生するCOと、石英ルツボと黒鉛ルツボの反応に起因するCO、及び、Si融液に石英ルツボが溶解して発生するSiOガスと黒鉛部材の反応で発生するCO のそれぞれの寄与を分離して把握した。

開催年月日： 2019年3月

記述言語：日本語   会議種別：口頭発表（一般）  

開催地：東京   国名：日本国  

開催年月日： 2019年3月

記述言語：日本語   会議種別：口頭発表（一般）  

開催地：東京   国名：日本国  

Si絶縁ゲートバイポーラトランジスタ(Si-IGBT)は高耐圧パワー半導体デバイスとして今後の主流になると期待され、3Dスケーリング等の開発が進められている。さらに、Si-IGBTの性能向上にはキャリアライフタイム制御も重要である。 Si-IGBT製造には、周囲に空乏層を作り耐圧を高めるためにガードリングを形成する必要がある。このガードリングを形成するプロセスでは、1100℃、3 hourの高温ウエット酸化処理で約1 μmのマスク酸化膜を形成し、リソグラフィとエッチングでパターンを形成し、Bイオン注入を行う。続いて1100℃、20 hourの拡散処理を行なっている。本研究では、高温ウエット酸化処理プロセスにより、酸素がFZ-Si中に注入され、少数キャリアライフタイムが減少することを見出したので報告する。

開催年月日： 2018年12月

記述言語：日本語  

開催地：横須賀市   国名：日本国  

開催年月日： 2018年12月

記述言語：英語  

国名：アメリカ合衆国  

開催年月日： 2018年11月

記述言語：英語  

国名：日本国  

開催年月日： 2018年11月

記述言語：英語   会議種別：口頭発表（一般）  

国名：日本国  

開催年月日： 2018年11月

記述言語：その他   会議種別：口頭発表（一般）  

開催地：西安   国名：コロンビア共和国  

開催年月日： 2018年11月

記述言語：日本語   会議種別：口頭発表（一般）  

開催地：川崎市   国名：日本国  

開催年月日： 2018年10月 - 2018年11月

記述言語：英語   会議種別：口頭発表（一般）  

国名：日本国  

開催年月日： 2018年10月

記述言語：英語   会議種別：口頭発表（一般）  

国名：アメリカ合衆国  

開催年月日： 2018年9月

記述言語：日本語   会議種別：口頭発表（一般）  

開催地：名古屋市   国名：日本国  

開催年月日： 2018年9月

記述言語：日本語   会議種別：口頭発表（一般）  

開催地：名古屋市   国名：日本国  

開催年月日： 2018年9月

記述言語：日本語   会議種別：口頭発表（一般）  

開催地：名古屋市   国名：日本国  

開催年月日： 2018年9月

記述言語：英語  

国名：ブルガリア共和国  

開催年月日： 2018年9月

記述言語：英語   会議種別：口頭発表（一般）  

国名：ドイツ連邦共和国  

開催年月日： 2018年8月

記述言語：日本語   会議種別：口頭発表（一般）  

開催地：横浜市   国名：日本国  

開催年月日： 2018年6月

記述言語：英語   会議種別：口頭発表（一般）  

国名：アメリカ合衆国  

開催年月日： 2018年4月

記述言語：英語   会議種別：口頭発表（一般）  

国名：日本国  

開催年月日： 2018年3月

記述言語：英語   会議種別：口頭発表（一般）  

国名：スペイン  

開催年月日： 2018年3月

記述言語：日本語   会議種別：口頭発表（一般）  

開催地：早稲田大学（東京都）   国名：日本国  

開催年月日： 2018年3月

記述言語：日本語   会議種別：口頭発表（一般）  

開催地：早稲田大学（東京都）   国名：日本国  

分極接合による高濃度二次元正孔ガスの形成技術を利用したPチャネルFETのデバイス特性をシミュレーションで検討するに当たり、AlGaN/GaN界面に生じる二次元正孔／電子ガスを枯渇させるバックゲート電圧が実測と大きく乖離する現象が見られた。本講演ではAlGaN/GaN界面に界面準位を想定することで実測を一部よく再現する結果が得られたので報告する。

開催年月日： 2018年3月

記述言語：日本語   会議種別：口頭発表（一般）  

開催地：早稲田大学（東京都）   国名：日本国  

開催年月日： 2017年10月

記述言語：英語   会議種別：口頭発表（一般）  

国名：中華人民共和国  

開催年月日： 2017年9月

記述言語：英語   会議種別：口頭発表（一般）  

国名：日本国  

開催年月日： 2016年12月

記述言語：英語  

国名：アメリカ合衆国  

開催年月日： 2016年3月

記述言語：英語  

国名：アメリカ合衆国  

開催年月日： 2015年11月

記述言語：英語  

国名：マカオ(澳門)特別行政区  

開催年月日： 2015年10月

記述言語：英語  

国名：アメリカ合衆国  

開催年月日： 2015年5月

記述言語：英語  

国名：アメリカ合衆国  

開催年月日： 2015年5月

記述言語：英語  

国名：ドイツ連邦共和国  

開催年月日： 2015年5月

記述言語：英語  

国名：中華人民共和国  

開催年月日： 2014年9月

記述言語：英語  

国名：フランス共和国  

開催年月日： 2014年6月

記述言語：英語  

国名：アメリカ合衆国  

開催年月日： 2014年5月

記述言語：英語  

国名：日本国  

開催年月日： 2014年5月

記述言語：英語  

国名：日本国  

開催年月日： 2013年10月

記述言語：英語  

国名：アメリカ合衆国  

開催年月日： 2013年10月

記述言語：英語  

国名：日本国  

開催年月日： 2013年9月

記述言語：英語  

国名：アメリカ合衆国  

開催年月日： 2013年9月

記述言語：英語  

国名：アメリカ合衆国  

開催年月日： 2013年9月

記述言語：英語  

国名：アメリカ合衆国  

開催年月日： 2012年10月

記述言語：英語  

国名：アメリカ合衆国  

開催年月日： 2012年9月

記述言語：英語  

国名：アメリカ合衆国  

開催年月日： 2012年6月

記述言語：英語  

国名：中華人民共和国  

開催年月日： 2011年10月

記述言語：英語  

国名：中華人民共和国  

開催年月日： 2011年9月

記述言語：英語  

国名：アメリカ合衆国  

開催年月日： 2011年9月

記述言語：英語  

国名：アメリカ合衆国  

開催年月日： 2011年8月 - 2011年9月

記述言語：英語  

国名：グレートブリテン・北アイルランド連合王国(英国)  

開催年月日： 2010年8月 - 2010年9月

記述言語：英語  

国名：ノルウェー王国  

開催年月日： 2009年10月

記述言語：英語  

国名：ドイツ連邦共和国  

開催年月日： 2008年9月

記述言語：英語  

国名：スペイン  

開催年月日： 2007年5月

記述言語：英語  

国名：大韓民国  

開催年月日： 2006年4月

記述言語：英語  

国名：アメリカ合衆国  

開催年月日： 2006年4月

記述言語：英語  

国名：アメリカ合衆国  

開催年月日： 2005年9月

記述言語：英語  

国名：アメリカ合衆国  

開催年月日： 2005年9月

記述言語：英語  

国名：アメリカ合衆国  

開催年月日： 2005年9月

記述言語：英語  

国名：アメリカ合衆国  

開催年月日： 2005年9月

記述言語：英語  

国名：ドイツ連邦共和国  

開催年月日： 2004年8月 - 2004年9月

記述言語：英語  

国名：イタリア共和国  

開催年月日： 2004年8月 - 2004年9月

記述言語：英語  

国名：イタリア共和国  

記述言語：その他  

記述言語：その他  

記述言語：その他  

記述言語：その他  

記述言語：日本語  

記述言語：その他  

記述言語：日本語  

記述言語：その他  

記述言語：その他  

記述言語：その他  

記述言語：その他  

記述言語：その他  

記述言語：その他  

記述言語：その他  

記述言語：その他  

記述言語：その他  

記述言語：その他  

記述言語：その他  

記述言語：その他  

記述言語：英語  

DOI： 10.4028/www.scientific.net/MSF.717-720.25

記述言語：英語  

SiC Bulk Single Crystal Growth by Sublimation Method : Use of Numerical Simulation

記述言語：英語  

記述言語：英語  

Experimental Results of Oscillatory Marangoni Convection in a Liquid Bridge under Normal Gravity