Kyushu University Academic Staff Educational and Research Activities Database
Researcher information (To researchers) Need Help? How to update
Inoue Koji Last modified date:2021.06.08



Graduate School
Undergraduate School
Other Organization
Administration Post
Other


E-Mail *Since the e-mail address is not displayed in Internet Explorer, please use another web browser:Google Chrome, safari.
Homepage
https://kyushu-u.pure.elsevier.com/en/persons/inoue-koji
 Reseacher Profiling Tool Kyushu University Pure
https://sites.google.com/view/kojiinoue-en/
Phone
092-802-3793
Fax
092-802-3786
Academic Degree
Engineering
Country of degree conferring institution (Overseas)
No
Field of Specialization
Computer Architecture, Low-Power VLSI
Total Priod of education and research career in the foreign country
00years00months
Outline Activities
In next social infrastructures based on advanced information technology, microprocessor systems will deeply infiltrate into our daily lives, for example, electric government, electric money, ubiquitous computing, and so on. To achieve steady social environment, we explore architectural supports for high-performance, low-energy, secure computing. We also design real VLSI chips to evaluate our ideas.
Research
Research Interests
  • Next-Generation Computer System Architecture
    keyword : Processor, Multi-Core, Many-Core, Memory Architecture, SOC, HIgh-Performance, Low-Power, Dependable
    2004.09The aim of our reserch is to explore architectural supports for high-performance, low-energy, secure computing. We also design VLSI chips to evaluate our ideas..
Current and Past Project
  • We develop dynamic optimization techniques to achieve high-performance and low-energy consumption at the same time. Our approach monitors memory-access behavior, and attempts to eliminate unnecessary operations.
  • In next social infrastructures based on advanced information technology, microprocessor systems will deeply infiltrate into our daily lives, for example, electric government, electric money, ubiquitous computing, and so on. To achieve steady social environment, microprocessors have to solve at least two issues: improvement in the safety and reduction of more energy. In this study, we propose a novel processor system to solve the computer-virus problem, and analyze an existing trade-off between safety and energy consumption. Our processor system exploits program-execution behavior as a confidential key to achieve on-line program certification.
Academic Activities
Books
1. V. Moshnyaga and K. Inoue, Low-Power Electronics Design (Low-Power Cache Design: Chap. 25), CRC PRESS, 2004.01.
Papers
1. Koki Ishida, Ilkwon Byun, Ikki Nagaoka, Kousuke Fukumitsu, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Jangwoo Kim, and Koji Inoue, Superconductor Computing for Neural Networks, IEEE Micro, Volume 41, Issue 3, 2021.06.
Presentations
1. Koki Ishida, Ilkwon Byun, Ikki Nagaoka, Kousuke Fukumitsu, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Jangwoo Kim, and Koji Inoue, SuperNPU: An Extremely Fast Neural Processing Unit Using Superconducting Logic Devices, IEEE/ACM International Symposium on Microarchitecture (MICRO), 2020.10, Superconductor single-flux-quantum (SFQ) logic family has been recognized as a highly promising solution for the post-Moore's era, thanks to its ultra-fast and low-power switching characteristics. Therefore, researchers have made a tremendous amount of effort in various aspects to promote the technology and automate its circuit design process (e.g., low-cost fabrication, design tool development). However, there has been no progress in designing a convincing SFQ-based architectural unit due to the architects' lack of understanding of the technology's potentials and limitations at the architecture level. In this paper, we present how to architect an SFQ-based architectural unit by providing design principles with an extreme-performance neural processing unit (NPU). To achieve the goal, we first implement an architecture-level simulator to model an SFQ-based NPU accurately. We validate this model using our die-level prototypes, design tools, and logic cell library. This simulator accurately measures the NPU's performance, power consumption, area, and cooling overheads. Next, driven by the modeling, we identify key architectural challenges for designing a performance-effective SFQ-based NPU (e.g., expensive on-chip data movements and buffering). Lastly, we present SuperNPU, our example SFQ-based NPU architecture, which effectively resolves the challenges. Our evaluation shows that the proposed design outperforms a conventional state-of-the-art NPU by 23 times. With free cooling provided as done in quantum computing, the performance per chip power increases up to 490 times. Our methodology can also be applied to other architecture designs with SFQ-friendly characteristics..
2. 稲富 雄一, Tapasya Patki, Inoue Koji, Mutsumi Aoyagi, Barry Rountree, Martin Schulz, David Lowenthal, Yasutaka Wada, Keiichiro Fukazawa, Masatsugu Ueda, Masaaki Kondo, Ikuo Miyoshi, Analyzing and Mitigating the Impact of Manufacturing Variability in Power-Constrained Supercomputing, The International Conference for High Performance Computing, Networking, Storage and Analysis , 2015.11.