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Yamamoto Keisuke Last modified date：2024.04.19

Associate Professor / Department of Advanced Energy Science and Engineering
Faculty of Engineering Sciences


Graduate School
Department of Interdisciplinary Engineering Sciences
Interdisciplinary Graduate School of Engineering Sciences
Department of Applied Science for Electronics and Materials
Interdisciplinary Graduate School of Engineering Sciences
Undergraduate School
School of Engineering
Other Organization
Global Innovation Center


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Homepage
https://kyushu-u.elsevierpure.com/en/persons/keisuke-yamamoto
　Reseacher Profiling Tool　Kyushu University Pure
https://www.gic.kyushu-u.ac.jp/functionaldevices/index_e.htm
Faculty of Engineering Sciences/Global Innovation Center, Advanced Project Division: Functional Devices. .
http://www.tj.kyushu-u.ac.jp/leading/en/index.html
Advanced Graduate Program in Global Strategy for Green Asia .
Academic Degree
Ph. D. (Engineering)
Country of degree conferring institution (Overseas)
No
Field of Specialization
semiconductor engineering
ORCID(Open Researcher and Contributor ID)
0000-0001-8730-598X
Total Priod of education and research career in the foreign country
00years03months
Research
Research Interests
  • Ge applied novel devices
    keyword : Ge spin MOSFET, flexible Ge TFT, Ge-on-Insulator
    2019.04.
  • SiGe process technology and evaluation
    keyword : SiGe, contact, strain, defect
    2019.12.
  • Fundamental research for SiC power devices
    keyword : 3C-SiC, gate stack, Ohmic contact, FET
    2011.10.
  • Fundamental research for Ge-CMOS devices
    keyword : Ge channel, Ge-on-Insulator, high-k/Ge, metal gate, metal/Ge contact, metal S/D
    2010.04.
Academic Activities
Papers
 Show All Papers >>
1. , [URL].
2. , [URL].
3. , [URL].
4. Kenta Moto, Keisuke Yamamoto, Toshifumi Imajo, Takashi Suemasu, Hiroshi Nakashima, Kaoru Toko, Sn concentration effects on polycrystalline GeSn thin film transistors, IEEE Electron Device Letters, 10.1109/LED.2021.3119014, 2021.12, [URL].
5. Keisuke Yamamoto, Dong Wang, Hiroshi Nakashima, (Invited) Fabrication of Ge-on-Insulator By Epitaxial Growth and Ion-Implanted Exfoliation for Electronics and Opt-Electronics Applications, ECS Transactions, 10.1149/10404.0157ecst, 104, 4, 157-166, 2021.10, [URL].
6. Keisuke Yamamoto, Dong Wang, Hiroshi Nakashima, (Invited) Schottky Barrier Height Control at Metal/Ge Interface by Insertion of Nitrogen Contained Amorphous Layer, ECS Transactions, 10.1149/10204.0063ecst, 102, 4, 63-71, 2021.05, [URL].
7. Hiroshi Nakashima, Wei-Chen Wen, Keisuke Yamamoto, Dong Wang, Border-Trap Characterization for Ge Gate Stacks with Thin GeOX layer Using Deep-Level Transient Spectroscopy, ECS Transactions, 10.1149/09805.0395ecst, 98, 5, 395-404, 2020.10, [URL].
8. , [URL].
9. Keisuke Yamamoto, Kohei Nakae, Hiroshi Akamine, Dong Wang, Hiroshi Nakashima, Md. M Alam, Kentarou Sawano, Zhongying Xue, Miao Zhang, and Zengfeng Di, Conduction Type Control of Ge-on-Insulator: Combination of Smart-CutTM and Defect Elimination, ECS Transactions, 10.1149/09301.0073ecst, 93, 1, 73-77, 2019.10, [URL].
10. Keisuke Yamamoto, Ryutaro Noguchi, Masatoshi Mitsuhara, Minoru Nishida, Toru Hara, Dong Wang, Hiroshi Nakashima , Wide range control of Schottky barrier heights at metal/Ge interfaces with nitrogen-contained amorphous interlayers formed during ZrN sputter deposition, Semiconductor Science and Technology, 10.1088/1361-6641/aae4bd, 33, 11, 114011, 2018.10.
11. Keisuke Yamamoto, Hayato Okamoto, Dong Wang, Hiroshi Nakashima, Fabrication of asymmetric Ge Schottky tunneling source n-channel field-effect transistor and its characterization of tunneling conduction, Materials Science in Semiconductor Processing, 10.1016/j.mssp.2016.09.024, 70, 1, 283-287, 2016.10, [URL].
12. Keisuke Yamamoto, Ryutaro Noguchi, Mitsuhara Masatoshi, Minoru Nishida, Toru Hara, Dong Wang, Hiroshi Nakashima, Electrical and structural properties of group-4 transition-metal nitride (TiN, ZrN, and HfN) contacts on Ge, Journal of Applied Physics, 10.1063/1.4930573, 118, 11, 115701-1-115701-12, 2015.09, [URL].
13. Keisuke Yamamoto, Mitsuhara Masatoshi, Keisuke Hiidome, Ryutaro Noguchi, Minoru Nishida, DONG WANG, Hiroshi Nakashima, Role of an interlayer at a TiN/Ge contact to alleviate the intrinsic Fermi-level pinning position toward the conduction band edge
, Applied Physics Letters, 10.1063/1.4870510, 104, 14, 132109-1-132109-5, 2014.04, [URL].
14. Yamamoto Keisuke, DONG WANG, Hiroshi Nakashima, Fabrication of Metal-Nitride/Si Contacts with Low Electron Barrier Height, ECS Transactions, 10.1149/05809.0053ecst, 58, 9, 53, 2013.10, [URL].
15. Yamamoto Keisuke, Takahiro Sada, DONG WANG, Hiroshi Nakashima, Dramatic enhancement of low electric-field hole mobility in metal source/drain Ge p-channel metal-oxide-semiconductor field-effect transistors by introduction of Al and Hf into SiO2/GeO2 gate stack, Applied Physics Letters, 10.1063/1.4821546, 103, 12, 122106, 2013.09, [URL].
16. K. Yamamoto, K. Harada, H. Yang, D. Wang, H. Nakashima, Fabrication of TiN/Ge Contact with Extremely Low Electron Barrier Height, Japanese Journal of Applied Physics, 10.1143/JJAP.51.070208, 51, 7, 070208, 2012.07, [URL].
17. K. Yamamoto, T. Yamanaka, K. Harada, T. Sada, K. Sakamoto, S. Kojima, H. Yang, D. Wang, H. Nakashima, Schottky Source/Drain Ge Metal-Oxide-Semiconductor Field-Effect Transistors with Directly Contacted TiN/Ge and HfGe/Ge Structures, Applied Physics Express, 10.1143/APEX.5.051301, 5, 5, 051301, 2012.05, [URL].
18. K. Yamamoto, T. Yamanaka, R. Ueno, K. Hirayama, H. Yang, D. Wang, H. Nakashima, Source/drain junction fabrication for Ge metal-oxide-semiconductor field-effect transistors, Thin Solid Films, 10.1016/j.tsf.2011.10.047, 520, 8, 3382, 2012.02, [URL].
19. K. Yamamoto, R. Ueno, T. Yamanaka, K. Hirayama, H. Yang, D. Wang, H. Nakashima, High-Performance Ge Metal-Oxide-Semiconductor Field-Effect Transistors with a Gate Stack Fabricated by Ultrathin SiO2/GeO2 Bilayer Passivation, Applied Physics Express, 10.1143/APEX.4.051301, 4, 5, 051301, 2011.04, [URL].
Presentations
 Show All Presentations >>
1. H. Kuwazuru, D. Wang, and K. Yamamoto, Fabrication of a Ge gate stack using plasma irradiation and low-temperature annealing for Ge applications, 14th International WorkShop on New Group IV Semiconductor Nanoelectronics, 2023.12.
2. K. Yamamoto, W.-C. Wen, D. Wang, and H. Nakashima, Electrical and Structural Characterization of Thermally Oxidized Yttrium Oxide on Germanium, 14th International WorkShop on New Group IV Semiconductor Nanoelectronics, 2023.12.
3. L. Huang, K. Moto, K. Igura, T. Ishiyama, K. Toko, D. Wang, K. Yamamoto, Inversion Mode n-channel TFT Fabricated on Solid-Phase Crystallized Polycrystalline Ge at Low Temperature Improved by Metal Induced Dopant Activation, 14th International WorkShop on New Group IV Semiconductor Nanoelectronics, 2023.12.
4. H. Kuwazuru, D. Wang, K. Yamamoto , Low Temperature (~210 °C) Fabrication of Ge MOS Capacitor using Plasma Oxidation and Oxi-Nitridation for the Interlayer Formation, 2023 International Workshop on DIELECTRIC THIN FILMS FOR FUTURE ELECTRON DEVICES: SCIENCE AND TECHNOLOGY, 2023.10.
5. K. Yamamoto, D. Wang, R. Loo, C. Porret, J. Cho, K. Dessein, V. Depauw, Fabrication and Electrical Characterization of Ge-on-Insulator based on Ge-on-Nothing Technology, 2023 International Workshop on DIELECTRIC THIN FILMS FOR FUTURE ELECTRON DEVICES: SCIENCE AND TECHNOLOGY, 2023.10, Ge-on-Insulator (GOI) is considered to be a necessary structure for novel Ge-based devices. This paper proposes an alternative approach for fabricating GOI based on the Ge-on-Nothing (GeON) template. In this approach, a regular macropore array is formed by lithography and dry etching. These pores close and merge upon annealing, forming a suspended monocrystalline Ge membrane on one buried void. GOI is fabricated by direct bonding of GeON on Si carrier substrates, using an oxide bonding interface, and subsequent detachment. The fabricated GOI shows uniform physical properties as demonstrated using micro-photoluminescence measurements. Its electrical characteristics and cross-sectional structure are superior to those of Smart-CutTM GOI. To demonstrate its application potential, back-gate GOI capacitors and MOSFETs are fabricated. Their characteristics nicely agree with the theoretically calculated one and show typical MOSFET operations, respectively, which indicates promising Ge crystallinity. This method, therefore, shows the potential to provide high-quality GOI for advanced Ge application devices..
6. L. Huang, K. Moto, T. Ishiyama, K. Toko, D. Wang, and K. Yamamoto, Inversion Mode n-channel TFT on Polycrystalline Ge Formed by Solid-Phase Crystallization, 2023 International Conference on Solid State Device and Materials (SSDM 2023), 2023.09.
7. K. Moto, K. Toko, T. Takayama, T. Ishiyama, K. Yamamoto, Various Metal Contacts on Polycrystalline Ge with Amorphous Interlayer Formed by ZrN Sputter-Deposition, 2023 International Conference on Solid State Device and Materials (SSDM 2023), 2023.09.
8. K. Yamamoto, W.-C. Wen, D. Wang, and H. Nakashima, Thermally oxidized Yttrium Oxide on Germanium for n-MOS Capacitor and Field-Effect Transistor, 244th ECS meeting, 2023.10, Germanium (Ge) has many exciting material characteristics, such as high carrier mobility and narrow bandgap in the near-infrared range. Thus it is suitable for various applications. A high-quality insulating film on Ge is required to apply Ge to novel electronic devices successfully. It is well known that GeO2 on Ge has good electrical characteristics as a gate insulator or interlayer (IL), similar to SiO2 on Si [1]. Unlike SiO2, however, GeO2 is thermodynamically unstable under atmospheric pressure at typical oxidation temperatures (~400 °C) and volatilizes as GeO [2,3]. Several methods have been developed to suppress GeO volatilization from the surface. For example, transition metals such as yttrium (Y) have been introduced into GeO2. Yttrium (Y)-doped GeO2 has excellent thermal, chemical, and electrical characteristics. In the capacitance–voltage measurement, it shows a low interface state density (Dit) and a narrow hysteresis corresponding to the border trap (BT) density (Nbt) of gate insulators [4]. Based on the above studies, we focused on metal Y deposition with subsequent thermal oxidation as an efficient alternative method to deposit Y-oxide as a gate insulator on Ge. This method has been studied to deposit Y2O3 as a gate insulator on Si [5]. Moreover, metal oxidation has been used to form various gate insulators on Ge, such as Al [6] and Hf [7]. In this study, we expect a capping layer of Y and oxidized Y to suppress GeO volatilization and stabilize the interface. We fabricated and evaluated metal-oxide-semiconductor (MOS) capacitors and MOS field-effect transistors (FETs) with either a thermally oxidized Y or a thermally oxidized Ge oxide layer. The structural analysis found that the insulator was divided into three layers: Y2O3, YGeO3, and GeOx from the top. The oxidation temperature affected only the thickness of the bottom GeOx layer. We found that the Y-oxide gate stack had better electrical characteristics and a lower Dit and Nbt than the thermally oxidized GeOx insulator. In contrast, the Dit–energy distribution and Nbt temperature dependence of the Y-oxide gate insulator were similar to those of the GeOx gate insulator. We examined these observations, including the structural analysis results. We found that thermally oxidized Y had a distinct advantage over thermally oxidized Ge oxide: the possibility of controlling the structure and electrical characteristics of the Ge gate stack, such as the GeOx thickness and the BT signal origin..
9. K. Moto, K. Toko, T. Takayama, T. Ishiyama, and K. Yamamoto, Control of schottky barrier height at metal/polycrystalline Ge interfaces with fermi-level pinning alleviation, International Conference on Silicon Epitaxy and Heterostructures and International SiGe Technology and Device Meeting 2023 (ISTDM-ICSI 2023), 2023.05.
10. K. Yamamoto, D. Wang, R. Loo, C. Porret, J. Cho, K. Dessein, and V. Depauw, Evaluation of the physical properties of Ge-on-insulator based on Ge-on-Nothing and layer transfer, International Conference on Silicon Epitaxy and Heterostructures and International SiGe Technology and Device Meeting 2023 (ISTDM-ICSI 2023), 2023.05.
11. H. Kuwazuru, S. Nasu, D. Wang, and K. Yamamoto, Study on the Performance of Metal S/D Ge n-MOSFET with Recessed Channel Structure, 13th International WorkShop on New Group IV Semiconductor Nanoelectronics, 2023.01.
12. L. Huang, K. Moto, T. Ishiyama, K. Toko, D. Wang, and K. Yamamoto, Inversion Mode n-channel TFT on Polycrystalline Ge Formed by Solid-Phase Crystallization, 13th International WorkShop on New Group IV Semiconductor Nanoelectronics, 2023.01.
13. K. Yamamoto, D. Wang, R. Loo, C. Porret, J. Cho, K. Dessein, and V. Depauw, Ge-on-Insulator from Ge-on-Nothing and Layer Transfer, 13th International WorkShop on New Group IV Semiconductor Nanoelectronics, 2023.01.
14. K. Moto, K. Toko, T. Takayama, T. Imajo, K. Yamamoto , First Demonstration of Rectifying Schottky Contact on Polycrystalline P-Type Ge Using ZrN Electrode, 2022 International Conference on Solid State Device and Materials (SSDM 2022), 2022.09.
15. W.-C. Wen, K. Yamamoto, D. Wang, H. Nakashima, Fabrication and Characterization of Ge n-MOS and n-MOSFET with Thermally Oxidized Yttrium Gate Insulator, 9th International Symposium on Control of Semiconductor Interfaces (ISCSI-IX), 2022.09.
16. T. Takayama, K. Moto, K. Yamamoto, T. Imajo, K. Toko, Fabrication and evaluation of polycrystalline Ge-based thin-film transistors on glass, The 5th International Union of Materials Research Societies International Conference of Young Researchers on Advanced Materials (IUMRS-ICYRAM 2022), 2022.08.
17. S. Nasu, T. Matsuo, K. Yamamoto, D. Wang, Fabrication of Ge MOSFET at low temperature (~250°C) for spintronics application, The 5th International Union of Materials Research Societies International Conference of Young Researchers on Advanced Materials (IUMRS-ICYRAM 2022), 2022.08.
18. K. Yamamoto, T. Matsuo, D. Wang, K. Moto, K. Toko, H. Nakashima, Novel group IV semiconductor materials and devices for beyond Si technology, The 5th International Union of Materials Research Societies International Conference of Young Researchers on Advanced Materials (IUMRS-ICYRAM 2022), 2022.08.
19. Keisuke Yamamoto, Dong Wang, Hiroshi Nakashima, Shigeomi Hishiki, Hiroki Uratani, Yoshiki Sakaida, Keisuke Kawamura , Achievement of High Channel Mobility of 3C-SiC n-MOSFET with the Gate Stack Formed at Low Temperature, 2021 International Workshop on DIELECTRIC THIN FILMS FOR FUTURE ELECTRON DEVICES: SCIENCE AND TECHNOLOGY, 2021.11.
20. Keisuke Yamamoto, Dong Wang, Hiroshi Nakashima, Fabrication of Ge-on-Insulator By Epitaxial Growth and Ion-Implanted Exfoliation for Electronics and Opt-Electronics Applications, 240th ECS meeting, 2021.10.
21. Kenta Moto, Keisuke Yamamoto, Toshifumi Imajo, Takashi Suemasu, Hiroshi Nakashima, Kaoru Toko , Sn Doping Effects on Polycrystalline Germanium Thin-Film Transistors on Glass, 2021 International Conference on Solid State Device and Materials (SSDM 2021), 2021.09.
22. Keisuke Yamamoto, Kento Iseri, Dong Wang, Hiroshi Nakashima, Low-Temperature Fabrication of Ge MOS Capacitor with Wet Oxidized Yttrium Interlayer, 2021 International Conference on Solid State Device and Materials (SSDM 2021), 2021.09.
23. Keisuke Yamamoto, Dong Wang, Hiroshi Nakashima, Schottky Barrier Height Control at Metal/Ge Interface by Insertion of Nitrogen Contained Amorphous Layer, 239th ECS meeting, 2021.05.
24. Kenta Moto, Keisuke Yamamoto, Takashi Suemasu, Hiroshi Nakashima, Kaoru Toko , Sn Doping Effects in Solid-Phase Crystallized Ge Thin-Film Transistors, PRiME 2020, 2020.10.
25. Hiroshi Nakashima, Wei-Chen Wen, Keisuke Yamamoto, Dong Wang, Border-Trap Characterization for Ge Gate Stacks with Thin GeOX layer Using Deep-Level Transient Spectroscopy, PRiME 2020, 2020.10.
26. Noboru Shimizu, Keisuke Yamamoto, Dong Wang, Hiroshi Nakashima, Isotropic Wet Etching and Improving Surface Flatness of Ge for Etchback Ge-on-Insulator Fabrication, PRiME 2020, 2020.10.
27. Hiroki Kanakogi, Wei-Chen Wen, Keisuke Yamamoto, Dong Wang, Hiroshi Nakashima, Thermally Oxidized Yttrium and Scandium Gate Dielectrics on Germanium with High Interfacial and Film Qualities, 2020 International Conference on Solid State Device and Materials (SSDM 2020), 2020.09.
28. Wei-Chen Wen, Keisuke Yamamoto, Dong Wang, Hiroshi Nakashima, Study on Position of Border Traps in Al2O3/GeOX/p-Ge Gate Stacks Using Deep-Level Transient Spectroscopy, 8th International Symposium on Control of Semiconductor Interfaces (ISCSI-VIII), 2019.11.
29. Kento Iseri, Wei-Chen Wen, Keisuke Yamamoto, Dong Wang, Hiroshi Nakashima , Low temperature (oC) Fabrication of Ge MOS Structure for Advanced Electronic Devices, 2019 International Conference on Solid State Device and Materials (SSDM 2019), 2019.09.
30. Ryusei Oka, Keisuke Yamamoto, Dong Wang, Hiroshi Nakashima, Sigeomi Hishiki, Keisuke Kawamura, Demonstration of n-MOSFET operation and charge analysis of SiO2/Al2O3 gate dielectric on (111) oriented 3C-SiC, 2019 International Conference on Solid State Device and Materials (SSDM 2019), 2019.09.
31. K. Yamamoto, K. Nakae, H. Akamine, D. Wang, H. Nakashima, Md. M. Alam, K. Sawano, Z. Xue, M. Zhang, Z. Di , Conduction Type Control of Ge-on-Insulator: Combination of Smart-Cut and Defect Elimination, 2nd Joint ISTDM / ICSI 2019 Conference 10th International SiGe Technology and Device Meeting (ISTDM) 12th International Conference on Silicon Epitaxy and Heterostructures, 2019.06.
32. Keisuke Yamamoto, Kentaro Akiyama, Kento Iseri, Wei-Chen Wen, Dong Wang, Hiroshi Nakashima , Fabrication of Ge MOS Capacitor with Metal Yttrium Oxidation, 12th International WorkShop on New Group IV Semiconductor Nanoelectronics, 2018.12.
33. K. Yamamoto, K. Nakae, D. Wang, H. Nakashima, Z. Xue, M. Zhang, Z. Di, Ambipolar operation of asymmetric Ge Schottky tunneling source field-effect transistor fabricated on Ge-on-Insulator, 2018 International Conference on Solid State Device and Materials (SSDM 2018), 2018.09.
34. K. Yamamoto, D. Wang, H. Nakashima, S. Hishiki, K. Kawamura, Impact of Al2O3 interlayer for metal-oxide-semiconductor capacitor on (111) oriented 3C-SiC for electronic device application, 2018 International Conference on Solid State Device and Materials (SSDM 2018), 2018.09.
35. Keisuke Yamamoto, Hayato Okamoto, DONG WANG, Hiroshi Nakashima, Achievement of Ultralow Contact Resistivity of Metal/Ge Contacts with Zr-N-Ge Amorphous Interlayer, 10th International Workshop on New Group IV Semiconductor Nanoelectronics and JSPS Core-to Core Program Joint Seminar "Atomically Controlled Processing for Ultralarge Scale Integration", 2017.02.
36. Hayato Okamoto, Keisuke Yamamoto, Dong Wang, Hiroshi Nakashima, Achievement of Ultralow Contact Resistivity of Metal/Ge Contacts with Zr-N-Ge Amorphous Interlayer, 2016 International Conference on Solid State Device and Materials (SSDM 2016), 2016.09.
37. Keisuke Yamamoto, Hayato Okamoto, DONG WANG, Hiroshi Nakashima, Characterization of Ge Tunnel FET with Metal/Ge Junction, 7th International Symposium on Control of Semiconductor Interfaces / International SiGe Technology and Device Meeting, 2016.06, [URL].
38. Keisuke Yamamoto, Ryutaro Noguchi, Masatoshi Mitsuhara, Minoru Nishida, Toru Hara, Dong Wang, Hiroshi Nakashima, Barrier Height Modulation for Metal/Ge Contacts with Nitrogen-Contained Amorphous Interlayers, 9th International Conference on Silicon Epitaxy and Heterostructures (ICSI-9), 2015.05, [URL].
39. Yamamoto Keisuke, DONG WANG, Hiroshi Nakashima, Fermi level pinning alleviation at the TiN, ZrN, and HfN/Ge interfaces, 7th International Silicon-Germanium Technology and Device Meeting (ISTDM 2014), 2014.06, [URL].
40. Keisuke Yamamoto, WANG DONG, Nakashima Hiroshi, Noguchi Ryutaro, Nishida Minoru, Mitsuhara Masatoshi, Hara Toru, Electrical Properties of Metal/Ge contacts with Nitrogen-Contained Amorphous Interlayers, 8th International Workshop on New Group IV Semiconductor Nanoelectronics and JSPS Core-to Core Program Joint Seminar "Atomically Controlled Processing for Ultralarge Scale Integration", 2014.01.
41. Keisuke Yamamoto, WANG DONG, Nakashima Hiroshi, Fabrication of Metal-Nitride/Ge Contacts with Extremely Low Electron Barrier Height and Its Clarification of the Physical Origin, 7th International Workshop on New Group IV Semiconductor Nanoelectronics and JSPS Core-to Core Program Joint Seminar "Atomically Controlled Processing for Ultralarge Scale Integration", 2014.01.
42. Yamamoto Keisuke, DONG WANG, Hiroshi Nakashima, Fabrication of Metal-Nitride/Si Contactswith Low Electron Barrier Height, 224th ECS Meeting, 2013.10, [URL].
43. Yamamoto Keisuke, Takahiro Sada, DONG WANG, Hiroshi Nakashima, Metal Source/Drain Ge p-MOSFET with HfGe/Ge Contact, 8th International Conference on Silicon Epitaxy and Heterostructures(ICSI-8) 2013, 2013.06.
44. Yamamoto Keisuke, Asakawa Kojiro, DONG WANG, Hiroshi Nakashima, Fabrication of TiN/Si Contact with Low Electron Barrier Height and Its Application to Back-Gate MOSFET, 6th International Symposium on Control of Semiconductor Interfaces (ISCSI-VI) 2013, 2013.06.
Membership in Academic Society
  • The Electrochemical Society
  • The Japan Society of Applied Physics
Educational
Other Educational Activities
  • 2022.09.


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