九州大学 研究者情報
発表一覧
西澤 伸一(にしざわ しんいち) データ更新日:2021.10.27

教授 /  応用力学研究所 附属自然エネルギー統合利用センター 新エネルギーシステム工学分野


学会発表等
1. Z. Lou, K. Wada, W. Saito, S.-I. Nishizawa, Investigations on Acceptable Breakdown Voltage Variation of Parallel-Connected SiC MOSFETs Applied in Solid-State Circuit Breakers, ESREF 2021 : 32th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, 2021, 2021.10.
2. M. Sagara, K. Wada, S.-I. Nishizawa, W. Saito, Avalanche Current Balancing Using Parallel Connection of SiC-JFETs with Cascode Connection, ESREF 2021 : 32th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, 2021, 2021.10.
3. Wataru Saito, Shin-Ichi Nishizawa, Power Loss Reduction of Low-Voltage Power MOSFET by Combination of Assist Gate Structure and Gate Control Technology, ISPSD2021, 2021.06.
4. M. Watanabe, N. Shigyo , T. Hoshii , K. Furukawa , K. Kakushima , K. Satoh , T. Matsudai , T. Saraya, T. Takakura, I. Muneta, H. Wakabayashi , A. Nakajima, S. Nishizawa, K. Tsutsui, T. Hiramoto, H. Ohashi , H. Iwai, Accurate TCAD Simulation of Trench-Gate IGBTs and Its Application to Prediction of Carrier Lifetime Requirements for Future Scaled Devices, 5th IEEE Electron Devices Technology and Manufacturing Conference (EDTM 2021), 2021.04.
5. 西澤伸一, 新世代Si-IGBTを支えるウェハ・プロセス技術, 日本学術振興会第145委員会  第171回研究会, 2021.02.
6. Lou Zaiqi,齋藤渉,西澤伸一 , DCブレーカ応用のための並列SiC-MOSFET耐圧ばらつき許容範囲の検討
, 電気学会,電子デバイス/半導体電力変換合同研究会, 2020.12.
7. 小川大地,齋藤渉,西澤伸一 , 60-150 V 系フィールドプレートパワー MOSFET の損失低減に向けた設計指針, 電気学会,電子デバイス/半導体電力変換合同研究会, 2020.12.
8. Peng Luo, Sankara Narayanan Ekkanath Madathil, Shin Ichi Nishizawa, Wataru Saito, High dV/dt controllability of 1.2kV TCIGBT through dynamic avalanche elimination, 2020 International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, PCIM Asia 2020, 2020.11.
9. Taro Takamori, Keiji Wada, Wataru Saito and Shin-ichi Nishizawa, Gate drive circuit for current balancing of parallel-connected SiC-JFETs under avalanche mode, 31st EUROPEAN SYMPOSIUM ON RELIABILITY OF ELECTRON DEVICES, FAILURE PHYSICS AND ANALYSIS (ESREF), 2020.10.
10. Lou Zaiqi,齋藤渉,西澤伸一, DCブレーカ応用のための並列SiC-MOSFET耐圧ばらつき許容範囲に関する研究, 第28回電気情報通信学会九州支部学生講演会, 2020.09.
11. 小川大地,齋藤渉,西澤伸一, 低耐圧フィールドプレートパワーMOSFETの損失低減に向けた設計指針と性能限界, 第28回電気情報通信学会九州支部学生講演会, 2020.09.
12. Zaiqi Lou, Wataru Saito, Shin-ichi Nishizawa, Investigation of Acceptable Breakdown Voltage Variation for Parallel-Connected SiC-MOSFET during UIS Test, International Conference on Solid State Devices and Materials (SSDM), 2020.09.
13. Wataru Saito; Shin-ichi Nishizawa, High Switching Controllability Trench Gate Design in Si-IGBTs, 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2020.09.
14. Peng Luo; Sankara Narayanan Ekkanath Madathil; Shin-ichi Nishizawa; Wataru Saito, Dynamic Avalanche Free Super Junction-TCIGBT for High Power Density Operation, 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2020.09.
15. Ryohei Sato, Koichi Kakimoto, Wataru Saito, Shin Ichi Nishizawa, Dislocation Propagation in Si 300 mm Wafer during High Thermal Budget Process and Its Optimization, 32nd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2020, 2020.09.
16. N. Shigyo, M. Watanabe, K. Kakushima, T. Hoshii, K. Furukawa, A. Nakajima, K. Satoh, T. Matsudai, T. Saraya, T. Takakura, K. Itou, M. Fukui, S. Suzuki, K. Takeuchi, I. Muneta, H. Wakabayashi, S. Nishizawa, K. Tsutsui, T. Hiramoto, H. Ohashi, Modeling and simulation of Si IGBTs, 2020 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2020, 2020.09.
17. Peng Luo, Sankara Narayanan Ekkanath Madathil, Shin-ichi Nishizawa, Wataru Saito, High dV/dt Controllability of 1.2kV Si-TCIGBT for High Flexibility Design with Ultra-low Loss Operation, 2020 IEEE Applied Power Electronics Conference and Exposition (APEC), 2020.03.
18. Shin-ichi Nishizawa, Recent Silicon wafer R&D trend as future PE key technology, The 2nd International Workshop on New Generation Power Electronics and Systems, 2020.01.
19. Peng Luo, Sankara Narayanan Ekkanath Madathil, Shin-ich Nishizawa, Wataru Saito, Dynamic avalanche free design in 1.2kV Si-IGBTs for ultra high current density operation, 65th Annual IEEE International Electron Devices Meeting, IEDM 2019, 2019.12.
20. 西澤 伸一, 原田 博文, 宮村 佳児, シリコン結晶成長における温度勾配と成長速度の関係, 第48回結晶成長国内会議(JCCG-48), 2019.11.
21. 佐藤 亮平, 高倉 俊彦, 伊藤 一夫, 更屋 拓哉, 平本 俊郎, 柿本 浩一, 西澤 伸一, デバイスプロセスの高温熱負荷工程におけるSi基板中の転位挙動に関する数値計算, 電気学会 電子デバイス/半導体電力変換合同研究会, 2019.11.
22. 更屋 拓哉, 伊藤 一夫, 福井 宗利, 鈴木 慎一, 竹内 潔, 附田 正則, 沼沢 陽一郎, 佐藤 克己, 末代 知子, 齋藤 渉, 角嶋 邦之, 星井 拓也, 古川 和由, 渡辺 正裕, 執行 直之, 若林 整, 筒井 一生, 岩井 洋, 小椋 厚志, 西澤 伸一, 大村 一郎, 大橋 弘通, 平本 俊郎, 5Vゲート駆動による3300VスケーリングIGBTの動作実装, 電気学会 電子デバイス/半導体電力変換合同研究会, 2019.11.
23. 劉 鑫, 原田 博文, 宮村 佳児, 韓学峰, 中野 智, 西澤 伸一, 柿本 浩一, CZシリコン結晶引き上げ過程における酸素偏析のモデル化, 第48回結晶成長国内会議(JCCG-48), 2019.10.
24. Munetoshi Fukui, Takuya Saraya, Kazuo Ito, Toshihiko Takakura, Shinichi Suzuki, Kiyoshi Takeuchi, Kuniyuki Kakushima, Takuya Hoshii, Kazuo Tsutsui, Hiroshi Iwai, Shin-ichi Nishizawa, Ichiro Omura, Toshiro Hiramoto, Impact of structural parameter scaling on on-state voltage in 1200V scaled IGBTs, SSDM, 2019.09.
25. Takuya Saraya, Kazuo Ito, Toshihiko Takakura, Munetoshi Fukui, Shinichi Suzuki, Kiyoshi Takeuchi, Kuniyuki Kakushima, Takuya Hoshii, Kazuo Tsutsui, Hiroshi Iwai, Shin-ichi Nishizawa, Ichiro Omura, Toshiro Hiramoto, Turn-off loss improvement by IGBT scaling, SSDM, 2019.09.
26. 劉 鑫, 原田 博文, 宮村 佳児, 韓学峰, 中野 智, 西澤 伸一, 柿本 浩一, CZシリコン結晶引き上げ過程における酸素と炭素の偏析のモデル化, 第80回応用物理学会秋季学術講演会, 2019.09.
27. 西澤 伸一, 原田 博文, 宮村 佳児, 結晶成長速度が固液界面形状および結晶内温度分布に及ぼす影響, 第80回応用物理学会秋季学術講演会, 2019.09.
28. 佐藤 亮平, 高倉 俊彦, 伊藤 一夫, 更屋 拓哉, 平本 俊郎, 柿本 浩一, 西澤 伸一, 熱負荷工程におけるSi基板中の転位挙動に関する数値計算, 第80回応用物理学会秋季学術講演会, 2019.09.
29. 沖田 寛昌, 星井 拓也, 松橋 泰平, Indraneel Sanyal, Yu-Chin Chen, Ying-Hao Ju, 中島 昭, 西澤 伸一, 大橋 弘通, 角嶋 邦之, 若林 整, Jen-Inn Chyi, 筒井 一生, TEGを用いたAlGaN/GaNヘテロ成長の2DEG側界面電荷への影響, 第80回応用物理学会秋季学術講演会, 2019.09.
30. Mitsuhiko Sagara, Keiji Wada, Shin-ichi Nishizawa, Evaluation of SiC-MOSFET by repetitive UIS tests for solid state circuit breaker, International Conference on Silicon Carbide and Related Materials 2019, 2019.09.
31. Xin Liu, Hirofumi Harada, Yoshiji Miyamura, Xue-Feng Han, Satoshi Nakano, Shin-ichi Nishizawa, and Koichi Kakimoto, Transient Global Modeling of CZ-Si crystal growth: Segregation of O & C during Pulling, ICCGE19, 2019.08.
32. Shin-ichi Nishizawa, EFFECTS OF GROWTH RATE ON MELT/CRYSTAL INTERFACE SHAPE AND TEMPERATURE DISTRIBUTION IN GROWING CRYSTAL, ICCGE19, 2019.07.
33. Yoshiji Miyamura, Hirofumi Harada, Satoshi Nakano, Shin-ichi Nishizawa, Koichi Kakimoto, CO concentration in Cz furnace, ICCGE19, 2019.07.
34. Xin Liu, Hirofumi Harada, Yoshiji Miyamura, Xue-Feng Han, Satoshi Nakano, Shin-ichi Nishizawa, and Koichi Kakimoto, Transient Global Modeling for the Pulling Process of CZ-Si Crystal Growth: Principles, Formulation and Implementation, ICCGE19, 2019.07.
35. Takuya Saraya, Kazuo Itou, Toshihiko Takakura, Munetoshi Fukui, Shinichi Suzuki, Kiyoshi Takeuchi, Masanori Tsukuda, Yohichiroh Numasawa, Katsumi Satoh, Tomoko Matsudai, Wataru Saito, Kuniyuki Kakushima, Takuya Hoshii, Kazuyoshi Furukawa, Masahiro Watanabe, Naoyuki Shigyo, Hitoshi Wakabayashi, Kazuo Tsutsui, Hiroshi Iwai, Atsushi Ogura, Shin Ichi Nishizawa, Ichiro Omura, Hiromichi Ohashi, Toshiro Hiramoto, 3300V Scaled IGBTs Driven by 5V Gate Voltage, 31st International Symposium on Power Semiconductor Devices and ICs, ISPSD 2019, 2019.05, [URL], In this work, 5V gate drive 3300V IGBTs, designed based on a scaling principle, have been demonstrated. Turn-off characteristics without noticeable degradation in the gate voltage waveforms were confirmed. Turn-off tail current of the scaled devices significantly decreased than conventional 15V-driven devices. As a result of both Vce and turn-off loss reduction, 35% improvement in Eoff vs Vcesat relationship was achieved..
36. Masahiro Watanabe, Naoyuki Shigyo, Takuya Hoshii, Kazuyoshi Furukawa, Kuniyuki Kakushima, Katsumi Satoh, Tomoko Matsudai, Takuya Saraya, Toshihiro Takakura, Kazuo Itou, Munetoshi Fukui, Shinichi Suzuki, Kiyoshi Takeuchi, Iriya Muneta, Hitoshi Wakabayashi, Akira Nakajima, Shin Ichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, Hiromichi Ohashi, Hiroshi Iwai, Impact of three-dimensional current flow on accurate TCAD simulation for trench-gate IGBTs, 31st International Symposium on Power Semiconductor Devices and ICs, ISPSD 2019, 2019.05, [URL], TCAD simulation has been recognized as a powerful design tool for insulated gate bipolar transistors (IGBTs). In this work, excellent agreement between 3D TCAD simulations and experimental current-voltage characteristics were obtained in the up to 1000 A/cm2 region for IGBTs with scaled trench-gates. The results of 2D and 3D simulations are compared to discuss the difference in current-voltage characteristics and their physical origins. A method to evaluate the saturation current (JCsat) using a 2D simulation is also presented with an appropriate correction..
37. Nobuyuki Shishido, Masanori Tsukuda, Shin-ichi Nishizawa, Trend in Thermal Resistance of Advanced Power Modules, PCIM Europe, 2019.05.
38. 宮村 佳児, 原田 博文, 中野 智, 西澤 伸一, 柿本 浩一, CZ炉内のCO濃度, 第66回応用物理学会春季学術講演会, 2019.03, CZ炉内のCOガス濃度をガスクロマトグラフにより測定した。炉内の脱ガスによって発生するCOと、石英ルツボと黒鉛ルツボの反応に起因するCO、及び、Si融液に石英ルツボが溶解して発生するSiOガスと黒鉛部材の反応で発生するCO のそれぞれの寄与を分離して把握した。.
39. 小林 弘人, 横川 凌, 木下 晃輔, 沼沢 陽一郎, 小椋 厚志, 西澤 伸一, 更屋 拓哉, 伊藤 一夫, 高倉 俊彦, 鈴木 慎一, 福井 宗利, 竹内 潔, 平本 俊郎, Si-IGBTプロセスによるFZ-Siの少数キャリアライフタイムへの影響評価, 第66回応用物理学会春季学術講演会, 2019.03, Si絶縁ゲートバイポーラトランジスタ(Si-IGBT)は高耐圧パワー半導体デバイスとして今後の主流になると期待され、3Dスケーリング等の開発が進められている。さらに、Si-IGBTの性能向上にはキャリアライフタイム制御も重要である。
Si-IGBT製造には、周囲に空乏層を作り耐圧を高めるためにガードリングを形成する必要がある。このガードリングを形成するプロセスでは、1100℃、3 hourの高温ウエット酸化処理で約1 μmのマスク酸化膜を形成し、リソグラフィとエッチングでパターンを形成し、Bイオン注入を行う。続いて1100℃、20 hourの拡散処理を行なっている。本研究では、高温ウエット酸化処理プロセスにより、酸素がFZ-Si中に注入され、少数キャリアライフタイムが減少することを見出したので報告する。.
40. 柿本 浩一, Liu Xin, 中野 智, 宮村 佳児, 原田 博文, 西澤 伸一, 不均一横磁場下のSi-CZ結晶成長における酸素移動現象の理解, 第66回応用物理学会春季学術講演会, 2019.03.
41. Shin-ichi Nishizawa, WBG road map activies in NPERC-J, WBG Roadmap Workshop, 2019.03.
42. T. Saraya, K. Itou, T. Takakura, M. Fukui, S. Suzuki, K. Takeuchi, M. Tsukuda, Y. Numasawa, K. Satoh, T. Matsudai, W. Saito, K. Kakushima, T. Hoshii, K. Furukawa, M. Watanabe, N. Shigyo, K. Tsutsui, H. Iwai, A. Ogura, Shinichi Nishizawa, I. Omura, H. Ohashi, T. Hiramoto, Demonstration of 1200V Scaled IGBTs Driven by 5V Gate Voltage with Superiorly Low Switching Loss, 64th Annual IEEE International Electron Devices Meeting, IEDM 2018, 2018.12, [URL], Functional trench-gated 1200V-10A class Si-IGBTs, designed based on a three dimensional (3D) scaling concept, were fabricated, and 5V gate voltage switching operation has been demonstrated for the first time. 33% reduction of turn-off loss and 100mV improvement of on-state voltage were achieved, while keeping 1.2kV forward blocking voltage..
43. 中川 聰子, 南 俊郎, 石川 高志, 西澤 伸一, パワーデバイス用シリコンウェーハのイオン注入欠陥評価, 第6回パワーデバイス用シリコンおよび関連半導体材料に関する研究会, 2018.12.
44. Takuya Hoshii, Shuma Tsuruta, Akira Nakajima, Shin-ichi Nishizawa, Hiromichi Ohashi, Kuniyuki Kakushima, Hitoshi Wakabayashi, Kazuo Tsutsui, Performance Prediction of Scaled p-channel GaN MOSFET on Polarization Junction Platform, The International Workshop on Nitride Semiconductors 2018 (IWN 2018), 2018.11.
45. 相良光彦, 和田圭二, 西澤伸一, SiCパワーデバイスを対象とした繰り返しUIS試験による特性評価, 電気学会電子デバイス・半導体電力変換合同研究会, 2018.11.
46. Xin Liu, Hirofumi Harada, Yoshiji Miyamura, Xue-Feng Han, Satoshi Nakano, Shin-ichi Nishizawa, and Koichi Kakimoto, Numerical analyses and experimental validations on transport and control of carbon in in Czochralski silicon crystal growth, 第47回結晶成長国内会議(JCCG-47), 2018.11.
47. 刘鑫, 原田博文, 宫村佳儿, 韩学峰, 中野智, 西泽伸一, 柿本浩一, 提拉法单晶硅生长系统中碳杂质输运与控制的数值模拟与实验验证, 14th China SoG Silicon and PV Power Conference, 2018.11.
48. Xin Liu, Hirofumi Harada, Yoshiji Miyamura, Xue-Feng Han, Satoshi Nakano, Shin-ichi Nishizawa, and Koichi Kakimoto, Numerical analyses and experimental validations on transport and control of carbon in CZ-Si crystal growth, The Forum on the Science and Technology of Silicon Materials 2018, 2018.11.
49. Shin-ichi Nishizawa, Future Power Devices and Semiconductor Wafer Materials, The Forum on the Science and Technology of Silicon Materials 2018, 2018.11.
50. Hirofumi Harada, Yoshiji Miyamura, Xue-Feng Han, Satoshi Nakano, Shin-ichi Nishizawa, Xin Liu, Numerical Analyses and Experimental Validations on Transport and Control of Carbon in Czochralski Silicon Crystal Growth, International Workshop on Modeling in Crystal Growth9 (IWMCG9), 2018.10.
51. Shin-ichi Nishizawa, Frederic Mercier, Effect of Nitrogen / Aluminum on Silicon Carbide Poly-type Stability, International Workshop on Modeling in Crystal Growth9 (IWMCG9), 2018.10.
52. T. Hoshii, K. Furukawa, K. Kakushima, M. Watanabe, N. Shigvo, T. Saraya, T. Takakura, K. Ltou, M. Fukui, S. Suzuki, K. Takeuchi, I. Muneta, H. Wakabayashi, Shinichi Nishizawa, K. Tsutsui, T. Hiramoto, H. Ohashi, H. Lwai, Verification of the injection enhancement effect in IGBTs by measuring the electron and hole currents separately, 48th European Solid-State Device Research Conference, ESSDERC 2018, 2018.09, [URL], The injection enhancement effect in IGBTs was experimentally verified by separately measuring emitter electron-and hole-currents for the first time. Finger contacts were employed as ladder-like periodic n+ and p+ emitters to allow the independent measurement of these currents. Both reducing the mesa width and increasing the cell pitch were found to increase electron injection from the emitter, demonstrating the injection enhancement effect. These experimental results agreed well with the simulation results..
53. Xin Liu, Hirofumi Harada, Yoshiji Miyamura, Xue-Feng Han, Satoshi Nakano, Shin-ichi Nishizawa, and Koichi Kakimoto, Numerical analyses and experimental validations on transport and control of carbon in CZ-Si crystal growth, the Sixth European Conference on Crystal Growth (ECCG6), 2018.09.
54. 中川 聰子, 南 俊郎, 石川 高志, 西澤 伸一, シリコンウェーハにおけるボロンイオン注入ダメージのCL評価, 第79回応用物理学会秋季学術講演会, 2018.09.
55. 鶴田 脩真, 星井 拓也, 中島 昭, 西澤 伸一, 大橋 弘通, 角嶋 邦之, 若林 整, 筒井 一生, AlGaN/GaN 界面準位が分極接合基板上 p-MOSFET の電流特性に与える影響, 第79回応用物理学会秋季学術講演会, 2018.09.
56. 小林 弘人, 横川 凌, 木下 晃輔, 沼沢 陽一郎, 小掠 厚志, 西澤 伸一, 更屋 拓也, 伊藤 一夫, 高倉 俊彦, 鈴木 慎一, 福井 宗利, 竹内 潔, 平本 俊郎, Si-IGBTプロセスによるFZ-Siの少数キャリアライフタイムへの影響評価, 第79回応用物理学会秋季学術講演会, 2018.09.
57. 相良 光彦, 和田 圭二, 西澤 伸一, 繰り返しUIS試験におけるSiCスイッチング素子の劣化評価, 電気学会産業応用部門大会(JIASC2018), 2018.08.
58. K. Kakushima, T. Hoshii, M. Watanabe, N. Shizyo, K. Furukawa, T. Saraya, T. Takakura, K. Itou, M. Fukui, S. Suzuki, K. Takeuchi, I. Muneta, H. Wakabayashi, Y. Numasawa, A. Ogura, Shinichi Nishizawa, K. Tsutsui, T. Hiramoto, H. Ohashi, H. Iwai, New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment, 32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018, 2018.06, [URL], A new methodology to evaluate the process temperature dependence of the minority carrier lifetime has been developed. A TEG layout with p+-stripes on an n-Si substrate was designed. When all the p+n junctions are made forward, the minority carrier diffusion current flows one dimensionally into the substrate. On the other hand, for making only the one center p+n junction forward, the current spreads laterally and flows cylindrically into the substrate. By the difference in the flow path of the minority carrier diffusion, we can successfully extract the minority carrier lifetime. We applied this methodology to the evaluation of the minority carrier lifetime depending on process temperatures and confirmed the lifetime degradation for high temperature process..
59. Koichi Kakimoto, Satosi Nakano, Yoshiji Miyamura, Hirofumi Harada, Xin Liu, Xuefeng Han, and Shin-ichi Nishizawa, Silicon crystal growth of solar cells: Lessons learned from the pasts, 10th International Workshop on Crystalline Silicon for Solar Cells, 2018.04.
60. 小林弘人, 横川凌, 鈴木貴博, 沼沢陽一郎, 小椋厚志, 西澤伸一, 更屋拓哉, 伊藤一夫, 高倉俊彦, 鈴木慎一, 福井宗利, 竹内潔, 平本俊郎, Si-IGBTプロセスによるFz-Siの少数キャリアライフタイムへの影響評価, 第65回応用物理学会春季学術講演会, 2018.03.
61. H. Iwai, K. Kakushima, T. Hoshii, K. Tsutsui, A. Nakajima, S. Nishizawa, H. Wakabayashi, I. Muneta, K. Sato, T. Matsudai, W. Saito, T. Saraya, K. Itou, M. Fukui, S. Suzuki, M. Kobayashi, T. Takakura, T. Hiramoto, A. Ogura, Y. Numasawa, I. Omura, H. Ohashi, 3D scaling of Si-IGBT, EUROSOI-ULIS 2018, 2018.03.
62. 柿本 浩一, 宮村 佳児, 原田 博文, Xin Liu, Han Xuefeng, 中野 智, 西澤 伸一, 高効率シリコン太陽電池用単結晶育成と評価の温故知新, 第65回応用物理学会 春季学術講演会, 2018.03.
63. 星井 拓也, 高山 留美, 鶴田 脩真, 中島 昭, 西澤 伸一, 大橋 弘通, 角嶋 邦之, 若林 整, 筒井 一生, 分極接合基板のAlGaN/GaN界面における界面準位, 第65回応用物理学会 春季学術講演会, 2018.03, 分極接合による高濃度二次元正孔ガスの形成技術を利用したPチャネルFETのデバイス特性をシミュレーションで検討するに当たり、AlGaN/GaN界面に生じる二次元正孔/電子ガスを枯渇させるバックゲート電圧が実測と大きく乖離する現象が見られた。本講演ではAlGaN/GaN界面に界面準位を想定することで実測を一部よく再現する結果が得られたので報告する。.
64. 筒井一生, 角嶋邦之, 星井拓也, 中島昭, 西澤伸一, 若井整, 宗田伊理也, 佐藤克己, 末代知子, 齋藤渉, 更屋拓哉, 伊藤一夫, 福井宗利, 鈴木慎一, 小林正治, 高倉俊彦, 平本俊郎, 小椋厚志, 沼沢陽一郎, 大村一郎, 大橋弘通, 岩井洋, 三次元スケーリングによるIGBTのVCEsat低減の実験的検証, 電気学会電子デバイス・半導体電力変換合同研究会, 2017.11, Three dimensionally scaled IGBTs that have a scaling factor of 3 (k=3) with respect to current commercial
products (k=1) were fabricated for the first time. The scaling was applied to the lateral and vertical dimensions as well as the gate voltage. A significant decrease in ON resistance, -- VCEsat reduction from 1.70 to 1.26 V -- was experimentally confirmed for the 3D scaled IGBTs..
65. Shin-ichi Nishizawa, Silicon Carbide Single Crystal Growth by Sublimation and its Poly-type Control, The 7th Asian Conference On Crystal Growth and Crystal Technology, 2017.10.
66. K. Tsutsui, K. Kakushima, T. Hoshii, A. Nakajima, S. Nishizawa, H. Wakabayashi, I. Muneta, K. Sato, T. Matsudai, W. Saito, T. Saraya, K. Itou, M. Fukui, S. Suzuki, M. Kobayashi, T. Takakura, T. Hiramoto, A. Ogura, Y. Numasawa, I. Omura, H. Ohashi, H. Iwai, 3D Scaling for Insulated Gate Bipolar Transistors (IGBTs) with Low Vce(sat), 2017 IEEE 12th International Conference on ASIC (ASICON), 2017.10.
67. Shin-ichi Nishizawa, WBG Roadmap-Lead Application, The 5th NPERC-J Workshop "Wide bandgap devices and lead applications", 2017.09.
68. Shin-ichi Nishizawa, Power Electronics Application of Widebadngap Semiconductor with its superior properties, German-Japanese Symposium "Regional Innovation and Cluster Collaborations", 2017.09.
69. K. Kakushima, T. Hoshii, K. Tsutsui, A. Nakajima, S. Nishizawa, H. Wakabayashi, I. Muneta, K. Sato, T. Matsudai, W. Saito, T. Saraya, K. Itou, M. Fukui, S. Suzuki, M. Kobayashi, T. akakura, T. Hiramoto, A. Ogura, Y. Numasawa, I. Omura, H. Ohashi, H. Iwai, Demonstration of Reduction in Vce(sat) of IGBT based on a 3D Scaling Principle, International Conference on Solid State Devices and Materials (SSDM), 2017.09.
70. Shin-ichi Nishizawa, Improvement of Si Materials and Processes for Si power devices, 7th International Workshop on Crystal Growth Technology, 2017.07.
71. Shin-ichi Nishizawa, Traning and educating crystal growth technology, 7th International Workshop on Crystal Growth Technology, 2017.07.
72. Kazunori Hasegawa, Ichiro Omura, Shin-ichi Nishizawa, An Evaluation Circuit for DC-Link Capacitors Used in a Single-Phase PWM Inverter, PCIM Europe, 2017.05.
73. Shin-ichi Nishizawa, WBG Roadmap-Lead Applications, CLINT-WPE Workshop:Cooperation with Japan Wide Bandgap Lead Applications & Advanced Requirements, 2017.03.
74. K. Kakushima, T. Hoshii, K. Tsutsui, A. Nakajima, Shinichi Nishizawa, H. Wakabayashi, I. Muneta, K. Sato, T. Matsudai, W. Saito, T. Saraya, K. Itou, M. Fukui, S. Suzuki, M. Kobayashi, T. Takakura, T. Hiramoto, A. Ogura, Y. Numasawa, I. Omura, H. Ohashi, H. Iwai, Experimental verification of a 3D scaling principle for low V ce(sat) IGBT, 62nd IEEE International Electron Devices Meeting, IEDM 2016, 2016.12, [URL], Three dimensionally (3D) scaled IGBTs that have a scaling factor of 3 (k=3) with respect to current commercial products (k=1) were fabricated for the first time. The scaling was applied to the lateral and vertical dimensions as well as the gate voltage. A significant decrease in ON resistance, - Vce(sat) reduction from 1.70 to 1.26 V - was experimentally confirmed for the 3D scaled IGBTs..
75. Kazunori Hasegawa, Ichiro Omura, Shinichi Nishizawa, A new evaluation circuit with a low-voltage inverter intended for capacitors used in a high-power three-phase inverter, 31st Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2016, 2016.03, [URL], DC-link capacitors in power electronic converters are a major constraint on improvement of power density as well as reliability. Evaluation of the dc-link capacitors in terms of power loss, ageing, and failure rate will play an important role in design stages of the next-generation power converters. This paper proposes a new evaluation circuit for dc-link capacitors used in a high-power three-phase inverter, which is intended for testing power loss, failure rate, ageing, and so on. The evaluation circuit produces a practical ripple current waveform and a dc bias voltage into a capacitor under test, in which the ripple current is equivalent to that generated by the three-phase inverter on the dc link. The evaluation circuit employs a full-scale current-rating and downscaled voltage-rating inverter for producing the ripple current, so that the power rating of the evaluation circuit is much smaller than that of a full-scale current rating and full-scale voltage rating inverter..
76. Shinichi Nishizawa, Wafer requirement for future power devices, 35th IEEE Region 10 Conference, TENCON 2015, 2015.11, [URL], For the future power electronics system, one of the key issues is to achieve more high power densities. At the moment, several types of silicon devices are widely used from the low voltage to high voltage ranges. To achieve more high power densities by size reduction and more high operating temperature, not only the device but also wafer material should be improved. The current status and future prospect of PE system with silicon technology will be discussed. Then, the role of compound semiconductor and its devices will be also discussed by comparison with silicon PE system..
77. Akira Nakajima, Shinichi Nishizawa, Shunsuke Kubota, Rei Kayanuma, Kazuo Tsutsui, Hiromichi Ohashi, Kuniyuki Kakushima, Hitoshi Wakabayashi, Hiroshi Iwai, An Overview of GaN-Based Monolithic Power Integrated Circuit Technology on Polarization-Junction Platform, 37th IEEE International Symposium on Workload Characterization, IISWC 2015, 2015.10, [URL], This paper gives an overview of GaN-based polarization-junction (PJ) technologies. PJ platform wafers have both high-density 2D hole gas (2DHG) and 2D electron gas (2DEG) respectively induced by negative and positive polarization charges in undoped GaN/AlGaN/GaN double heterostructures. On the platform, monolithic operations of GaN-based n-channel transistors and p-channel transistors have been demonstrated. Because of temperature independent properties of the 2DHG and 2DEG, the GaN devices can operate in wide temperature range. In addition, high voltage transistors and diode are also available on the platform by using polarization-superjunction concept..
78. Sethavut Duangchan, Yusuke Uchikawa, Yusuke Koishikawa, Baba Akiyoshi, Kentaro Nakagawa, Satoshi Matsumoto, Masataka Hasegawa, Shinichi Nishizawa, The silicon on diamond structure by low-temperature bonding technique, 2015 65th IEEE Electronic Components and Technology Conference, ECTC 2015, 2015.05, [URL], We demonstrate fabrication a silicon on diamond structure at around room temperature using a plasma-activated bonding (PAB) method. Thin and flat silicon-dioxide (SiO2) film was used as an activation layer for PAB. The SiO2 film was prepared by a chemical vapor deposition and then a chemical mechanical polishing (CMP). The surface roughness after the CMP were average ∼1 nm rms at 300 nm thick. Thinning of the SiO2 film was carried out using 2.5%HF solution. We found that there are no significant change in the surface roughness after the thinning process. The roughness of SiO2 less than or equal to 1 nm is required for success bonding at low-temperature with vacuum environment. The scanning electron microscope has shown seamless at the bonding interface that proves to good bonding result..
79. Akira Nakajima, Wataru Saito, Shinichi Nishizawa, Hiromichi Ohashi, Theoretical Loss analysis of power converters with 1200 v class Si-IGBT and SiC-MOSFET, 2015 International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, PCIM Europe 2015, 2015.05, Power converter efficiencies of 1200-V class Si-IGBT/SiC-SBD hybrid pairs and a SiCMOSFET/ SiC-SBD pair were theoretically compared at a switching frequency above the limit of human hearing (20 kHz). Si-IGBT losses were simulated by TCAD. SiC device losses were calculated by analytical minimum loss models. Calculated efficiencies of the full-SiC pair were slightly higher than that of the hybrid pairs at conventional current densities less than 200 A/cm2. At a higher current density of 400 A/cm2, the hybrid pairs have a potential of high performance which is comparable with the full-SiC efficiency..
80. Akira Nakajima, Shinichi Nishizawa, Hiromichi Ohashi, Rei Kayanuma, Kazuo Tsutsui, Shunsuke Kubota, Kuniyuki Kakushima, Hitoshi Wakabayashi, Hiroshi Iwai, GaN-based monolithic power integrated circuit technology with wide operating temperature on polarization-junction platform, 27th IEEE International Symposium on Power Semiconductor Devices and IC's, ISPSD 2015, 2015.05, [URL], Polarization junction platforms have high-density 2D hole gas (2DHG) and 2D electron gas (2DEG) respectively induced by negative and positive polarization charges in undoped GaN/AlGaN/GaN double heterostructures. Sheet resistance measurements in a wide temperature range (6-460 K) revealed that 2DHG and 2DEG resistances were monotonically enhanced with the temperature reduction. On the platform, monolithic operations of GaN-based devices including high-voltage n-channel (N-ch) transistors, N-ch Schottky diodes, low-voltage N-ch transistors and p-channel transistors has been demonstrated..
81. Akira Nakajima, Yosuke Tateishi, Hiroshi Murakami, Hidetomo Takahashi, Michiharu Ota, Ryoji Kosugi, Takeshi Mitani, Shinichi Nishizawa, Hiromichi Ohashi, High-speed dicing of SiC wafers by femtosecond pulsed laser, European Conference on Silicon Carbide and Related Materials, ECSCRM 2014, 2014.09, [URL], A novel dicing technology that utilizes femtosecond pulsed lasers (FSPLs) is demonstrated as a high-speed and cost-effective dicing process for SiC wafers. The developed dicing process consists of cleavage groove formation on a SiC wafer surface by the FSPL, followed by chip separation by pressing a cleavage blade. The effective FSPL scan speed on the SiC surfaces was 33 mm/s. Kerf loss is negligible in the developed FSPL dicing process. In addition, the residual lattice strain in the FSPL-diced SiC chips was comparably small to that of the conventional mechanical process using diamond saws, due to the absence of the lattice heating effect in femtosecond-laser processes..
82. Akira Nakajima, Shinichi Nishizawa, Hiromichi Ohashi, Hiroaki Yonezawa, Kazuo Tsutsui, Kuniyuki Kakushima, Hitoshi Wakabayashi, Hiroshi Iwai, One-chip operation of GaN-based P-channel and N-channel heterojunction field effect transistors, 26th International Symposium on Power Semiconductor Devices and ICs, ISPSD 2014, 2014.06, Monolithic operation of GaN-based P-channel (Pch) and N-channel (Nch) heterojunction field effect transistors (HFETs) are demonstrated for the first time. The Pch and Nch HFETs were fabricated on a polarization junction platform with polarization induced 2D hole gas (2DHG) and 2D electron gas (2DEG). Because of temperature independent densities of the 2DHG and 2DEG, the HFETs can be operated in wide temperature range. Based on a measured 2DHG mobility, footprints of low-voltage Pch HFETs for gate drive applications were estimated by device simulation..
83. Kyungmin Sung, Ryuji Iijima, Shinichi Nishizawa, Isami Norigoe, Hiromichi Ohashi, Experimental investigation of normally-on type bidirectional switch for indirect Matrix Converters, 7th International Power Electronics Conference, IPEC-Hiroshima - ECCE Asia 2014, 2014.05, In this paper, the novel normally-on type bidirectional switch, in which is comprised of SiC-JFET, SiC-SBD, and Si-IGBT is proposed for one of a protection method of the Matrix Converter (MC). When the MC becomes gate block situation, a diode clamp circuit or auxiliary circuits keeps inductive load current loop in a conventional MC utilized a bidirectional switch. We focus that the normally-on type SiC-JFET becomes turn-on state, when zero gate bias voltage and a SiC-devices have a good tolerance capability for short current than silicon devices. These characteristic of normally-on type SiC-JFET is used to replace diode clamp circuit in MC driver system. The experimentation based on indirect MC induction motor driver system was carried out. The experimental result of IM driver shows that the proposed bidirectional switch can overcome a generated inductive load current by IM. Finally, in order to design heat sink, the power loss of each devices of proposed switch was estimated by experimental results..
84. Yuji Matsuoka, Keiji Wada, Mizuki Nakahara, Kazuto Takao, Kyungmin Sung, Hiromichi Ohashi, Shinichi Nishizawa, 2.5kV, 200kW bi-directional isolated DC/DC converter for medium-voltage applications, 7th International Power Electronics Conference, IPEC-Hiroshima - ECCE Asia 2014, 2014.01, [URL], A bi-directional isolated DC/DC converter for medium-voltage applications have been discussed for the next-generation electrical grid, such as smart girds. To realize the DC/DC converter for installing on a power distribution system, it should be achieved higher-efficiency and lower-volume. Higher switching frequency enables to reduce the volume of the transformer. However, it is difficult to realize the both higher-efficiency and lower-volume of the DC/DC converter, because it could not operate higher frequency with high power devices such as medium-voltage IGBTs. This paper discusses switching losses and operation limitations for the actual medium-voltage isolated DC/DC converter, in the case of using Si-IGBT. In addition, the experimental system rated at 2.5 kV, 200 kW, and 5kH of the DC/DC converter with a medium-frequency transformer is designed, and the experimental results are shown..
85. Kazuto Takao, Keiji Wada, Kyungmin Sung, Yuji Mastuoka, Yasunori Tanaka, Shinichi Nishizawa, Takeo Kanai, Takashi Shinohe, Hiromichi Ohashi, 4.5 kV - 400 A SiC-PiN diode and Si-IEGT hybrid pair module for high switching frequency operation, 2013 2nd International Conference on Electric Power Equipment - Switching Technology, ICEPE-ST 2013, 2013.10, A 4.5kV-400A SiC-PiN diode and Si-IEGT hybrid pair module has been developed for realizing high switching frequency operations of medium-voltage power converters. The maximum switching frequency of the hybrid pair module is theoretically analyzed from viewpoints of cooling capacity of the heat sink and the minimum pulse width of a PWM signal. Operation tests of the hybrid pair module are implemented and 10 kHz operation has been successfully demonstrated..
86. Pucheng Liu, Kuniyuki Kakushima, Hiroshi Iwai, Akira Nakajima, Toshiharu Makino, Masahiro Ogura, Shinichi Nishizawa, Hiromichi Ohashi, Characterization of two-dimensional hole gas at GaN/AlGaN heterointerface, 1st IEEE Workshop on Wide Bandgap Power Devices and Applications, WiPDA 2013, 2013.10, Electrical properties of two-dimensional hole gas (2DHG) at GaN/Al 0.23Ga0.77N heterointerface have been investigated. Existence of 2DHG at the interface is confirmed by capacitance-voltage and Hall Effect measurement. We have discussed transport mechanism of 2DHG by comparison with hole generated by conventional Mg impurity, based on experimental evaluations by X-ray diffraction, transmission electron microscope, atomic force microscope, secondary ion mass spectroscopy, and temperature dependence Hall Effect measurements..
87. Kazuto Takao, Keiji Wada, Kyungmin Sung, Yuji Mastuoka, Yasunori Tanaka, Shinichi Nishizawa, Chiharu Ota, Takeo Kanai, Takashi Shinohe, Hiromichi Ohashi, Experimental evaluation of 10kHz switching operation of 4.5kV-400A SiC-PiN diode and Si-IEGT hybrid pair module, 5th Annual IEEE Energy Conversion Congress and Exhibition, ECCE 2013, 2013.09, Possibility of a 10 kHz switching frequency operation of a 4.5kV-400A SiC-PiN diode and Si-IEGT hybrid pair module has been investigated to drastically increase the switching frequency of medium-voltage power converters. For this purpose, the relation among the minimum pulsed width of the PWM signal, the modulation index, and the maximum switching frequency is analyzed based on the switching characteristics of the hybrid pair module. The analyzed data show that the 10 kHz switching frequency could be available with the hybrid pair module..
88. Kazuto Takao, Keiji Wada, Kyungmin Sung, Yuji Mastuoka, Yasunori Tanaka, Shinichi Nishizawa, Chiharu Ota, Takeo Kanai, Takashi Shinohe, Hiromichi Ohashi, Maximum switching frequency characterization of 4.5kV-400A SiC-PiN diode and Si-IEGT hybrid pair power module, 5th Annual IEEE Energy Conversion Congress and Exhibition, ECCE 2013, 2013.09, The maximum switching frequency of a 4.5 kV-400 A SiC-PiN diode and Si-IEGT hybrid pair module has been analyzed from the viewpoints of cooling capacity of the hybrid pair module and the minimum pulse width of the PWM signal. In the developed hybrid pair module, a direct water cooling type heat sink is employed to enhance the cooling capacity. It found that the developed 4.5 kV-400 A hybrid pair module could be operate at 10 kHz PWM switching frequency with the peak current of 110 A and the dc voltage of 2.5 kV. In this operating condition, the power losses of the Si-IEGT and SiC-PiN diode in the hybrid pair module are 2380W and 100 W, respectively..
89. Kazuto Takao, Keiji Wada, Kyungmin Sung, Yuji Mastuoka, Yasunori Tanaka, Shinichi Nishizawa, Chiharu Ota, Takeo Kanai, Takashi Shinohe, Hiromichi Ohashi, Experimental evaluation of 10kHz switching operation of 4.5kV-400A SiC-PiN diode and Si-IEGT hybrid pair module, 5th Annual IEEE Energy Conversion Congress and Exhibition, ECCE 2013, 2013.09, [URL], Possibility of a 10 kHz switching frequency operation of a 4.5kV-400A SiC-PiN diode and Si-IEGT hybrid pair module has been investigated to drastically increase the switching frequency of medium-voltage power converters. For this purpose, the relation among the minimum pulsed width of the PWM signal, the modulation index, and the maximum switching frequency is analyzed based on the switching characteristics of the hybrid pair module. The analyzed data show that the 10 kHz switching frequency could be available with the hybrid pair module..
90. Shinichi Nishizawa, Silicon carbide bulk crystal growth modeling from atomic scale to reactor scale, 2nd Symposium on Gallium Nitride (GaN) and Silicon Carbide (SiC) Power Technologies - ECS Fall 2012 Meeting, 2012.10, The state of the art of silicon carbide crystal growth modeling is explained from the two aspects. One is the technical problems of SiC bulk single crystal growth process by sublimation method. Numerical modeling can contribute on the reactor design and process condition optimization. Then the shape of SiC grown crystal (diameter and length) can be controlled by modifying the growth crucible design. Second one is the theoretical problem of SiC polytype control. By calculating the bulk crystal energy of each polytype, and surface energy of each possible surface during growth, it is pointed out that growin surface energy has effects on the polytype stability of SiC crystals..
91. Kazuto Takao, Keiji Wada, Kyungmin Sung, Yuji Mastuoka, Yasunori Tanaka, Shinichi Nishizawa, Chiharu Ota, Takeo Kanai, Takashi Shinohe, Hiromichi Ohashi, 4.5kV-400A modules using SiC-PiN diodes and Si-IEGTs hybrid pair for high power medium-voltage power converters, 4th Annual IEEE Energy Conversion Congress and Exposition, ECCE 2012, 2012.09, A new 4.5 kV-400 A module using SiC-PiN diodes and Si-IEGTs hybrid pair has been developed. The hybrid pair module is designed to realize high-frequency switching operation of high power medium-voltage power converters (1-10MVA, voltage range 310kV). In order to realize a low switching loss operation of the hybrid pair module, a hard gate driving with low gate resistor has been employed. Switching characteristics of the hybrid pair are evaluated experimentally and compared with that of a conventional 4.5 kV Si-IEGT and Si-PiN diode pair (All Si). The results show that the reverse recovery loss of diode and the turn-on loss of the Si-IEGT are reduced up to 95% and 60%, respectively. As a result, the total switching loss (i.e. turn-on and turn-off losses of the Si-IEGT plus reverse recovery loss of the diode) can be reduced up to 49% with the hybrid pair. The developed hybrid pair modules are applied to a prototype high power converter, and a high-frequency switching operation of 4 kHz has been successfully demonstrated..
92. Keiji Wada, Shinichi Nishizawa, Hiromichi Ohashi, Design and implementation of a non-destructive test circuit for SiC-MOSFETs, 2012 IEEE 7th International Power Electronics and Motion Control Conference - ECCE Asia, IPEMC 2012, 2012.06, Silicon carbide(SiC) power devices have been developed and they are sold in markets. Many papers have dealt with inverter circuits that use SiC power devices to improving efficiency and realize high power density converters. However, the power converters that use SiC power devices have not become commercially available, because the reliability of the SiC-MOSFET under switching-operation has not been sufficiently discussed. This paper presents a non-destructive test circuit for SiC-MOSFETs, and the experimental results have confirmed the validity of the non-destructive test circuit for Si- and SiC-MOSFETs. Moreover, the experimental results presents the phenomenon just before destruction of the MOSFETs. The purpose of the non-destructive test circuit is to evaluate the extreme conditions under actual switching operation without the destruction of the power devices. This paper shows experimental results under short-circuit tests for Si super junction MOSFETs (SJ-MOSFETs), and SiC double-diffusion MOSFETs (DMOSFETs). These experimental results will be analyzed to improve the reliability of SiC power device. As a result, the short-circuit switching operation of the SiC-MOSFET is observed to be different from that of the Si-MOSFET..
93. S. Yamasaki, T. Matsumoto, K. Oyama, H. Kato, M. Ogura, D. Takeuchi, T. Makino, Shinichi Nishizawa, H. Oohash, H. Okushi, Diamond power devices - Possbility of high voltage applicatios, 2011 1st International Conference on Electric Power Equipment - Switching Technology, ICEPE2011, 2011.10, As widely known, diamond has a higher break-down voltage than other semiconductor materials, 30 times than silicon and 3 times than silicon-carbide. Because of its superior property, diamond has a high potential of high voltage power devices. In addition diamond has unique properties, namely transport property of heavily doped material over 10 20 cm -3, high density exciton being stable even at room temperature, negative electron affinity with hydrogen terminated surface, etc. We have fabricated diamond devices using these properties, such as ultraviolet light emitting diodes, a new type of diode with high breakdown voltage and low ON resistance, high current density flow diode using heavily doped layers, and so on. In this key note lecture, we show the recent achievements of these electronic devices and discuss the potential of diamond semiconductor as a high voltage power device..
94. Koichi Kakimoto, Bing Gao, Takuya Shiramomo, Satoshi Nakano, Shinichi Nishizawa, Analysis of growth velocity of SiC growth by the physical vapor transport method, 14th International Conference on Silicon Carbide and Related Materials 2011, ICSCRM 2011, 2011.09, Crystal growth velocity of SiC in a process of physical vapor transport was studied on the basis of numerical calculation including the effect of compressibility, convection and buoyancy effects, flow coupling between argon gas and species of Si, Si 2C and SiC 2, and the Stefan effect. Calculation in a 2D configuration was performed to clarify the effect of pressure on growth velocity. The results revealed that convection plays a role in the measured values that growers interpret as growth velocity based on a diffusion process of argon gas and species of Si, Si 2C and SiC 2..
95. Frédéric Mercier, Shinichi Nishizawa, Bulk and surface effects on the polytype stability in SiC crystals, 14th International Conference on Silicon Carbide and Related Materials 2011, ICSCRM 2011, 2011.09, We investigated with ab initio calculations the 3C-, 6H-, 4H- and 2H-SiC polytypes. We discuss the geometry and the energetics of bulk and surface relaxed structures ((0001) Si face and the (000̄1) C face surfaces). The polytype stability is discussed regarding the bulk and surface effects..
96. Masato Ando, Keiji Wada, Kazuto Takao, Takeo Kanai, Shinichi Nishizawa, Hiromichi Ohashi, Design and analysis of a bus bar structure for a medium voltage inverter, 2011 14th European Conference on Power Electronics and Applications, EPE 2011, 2011.08, In order to suppress overvoltage of power devices and noise voltages of inverters, it is essential to analyze the DC-side inductance of the inverter. This paper presents a design procedure of an optimum structure for a 10-kV, 400-kVA three-level inverter. Rather than using 3D-FEM software, the bus bar inductance for the medium voltage inverter is calculated based on a partial inductance method. An inductance map is useful for determining the relationship between the bus bar structure and the inductance value and for designing the low-inductance structure. In addition, the calculation results of the bus bar inductance correspond to the measurement results, confirming the validity of the proposed method..
97. Frédéric Mercier, Shinichi Nishizawa, Effect of low frequency magnetic field on SiC solution growth, 8th European Conference on Silicon Carbide and Related Materials, ECSCRM 2010, 2010.08, We investigated numerically fluid dynamics and carbon transport in a 2 inches SiC solution growth with the presence of alternative magnetic fields. Buoyancy and Marangoni convection are taken into account. Our numerical results revealed that the magnetic field parameters have a strong impact on the melt convection. We also propose a solution to increase the mass transfer at the crystal growth front..
98. Tsubasa Matsumoto, Shinichi Nishizawa, Satoshi Yamasaki, Calculation of lattice constant of 4H-SiC as a function of impurity concentration, 13th International Conference on Silicon Carbide and Related Materials 2009, ICSCRM 2009, 2009.10, Calculations of lattice constant of 4H-SiC and diamond have been carried out. Lattice constant of 4H-SiC trends to decrease when nitrogen concentration increases. On the other hand, lattice constant of 4H-SiC trends to increase when aluminum concentration increases. Lattice constant of boron and phosphorus doped diamond trends to increase when impurity concentration increases. The effect of phosphorus on diamond lattice constant is about six times larger than that of boron..
99. C. Ota, J. Nishio, K. Takao, T. Hatakeyama, T. Shinohe, K. Kojima, Shinichi Nishizawa, H. Ohashi, Doping concentration optimization for ultra-low-loss 4H-SiC floating junction Schottky barrier diode (Super-SBD), 7th European Conference on Silicon Carbide and Related Materials, ECSCRM 2008, 2008.09, Previous simulation works and experiments on the loss of 4H-SiC floating junction Schottky barrier diodes (Super-SBDs) show that the loss is related to the doping concentration in the drift region and the pattern of the floating layer. The effect of the doping concentration for lowering the loss is characterized the breakdown voltage (Vbd) and the on-state resistances (RonS) of the Super-SBDs based on Baliga's figure of Merit (BFOM). Experimental devices with two doping concentrations in the drift region are fabricated to investigate the static characteristics: Vbd and RonS. The Vbd of the Super-SBDs is close to the simulation result, near 3000 V. However the tendency of the Vbd by the doping concentration is not similar to the simulation result. And the RonS are about 3.22 mΩcm2 which is higher than that of simulation result. The doping concentration optimized in this study does not show significant lowering loss and the design of the floating layer in the termination region affect the low-loss static characteristics of the Super-SBD. In addition, adopting PiN structure with floating layer (Super-PiN) affects the low-loss dynamic characteristics, optimizing the doping concentration in the drift region. We conclude that the fabricated Super-SBDs with the floating layer in the termination region, the drift region with a doping concentration of 1.0×1016 cm-3 and mesa-shaped termination structure, have excellent Vbd of 2990 V which is almost same as that of simulation result and RonS of 3.22 mΩcm2..
100. S. Harada, Y. Hayashi, K. Takao, A. Kinoshita, M. Kato, M. Okamoto, T. Kato, Shinichi Nishizawa, T. Yatsuo, K. Fukuda, H. Ohashi, K. Arai, Demonstration of motor drive with SiC normally-off IEMOSFET/ SBD power converter, 19th International Symposium on Power Semiconductor Devices and ICs, ISPSD'07, 2007.05, Normally-off power MOSFET with low Rons has been developed. IEMOSFET on 4H-SiC carbon-face wafer exhibits an extremely low Rons of 1.8 mωcm2 with a blocking voltage of 660 V. The effective channel mobility of this device is 90 cm2/Vs which corresponds to the channel resistance of 0.8 mωcm2. A step-down converter was fabricated with the normally-off IEMOSFET and SBD, and the operation of 400 W DC motor drive was successfully observed at room temperature..
101. Shinichi Nishizawa, Shin Ichi Nakashima, Tomohisa Kato, Effect of radiation in solid during SiC sublimation growth, 2006 MRS Spring Meeting, 2006.04, The effect of infrared absorption on SiC sublimation growth was numerically investigated. At first, absorption coefficient was estimated as function of doping concentration. Then temperature distribution inside a crucible was numerically analyzed with taking account of absorption in growing crystal. It was pointed out that temperature distribution in a growing crystal strongly depends on absorption coefficient, i.e. doping concentration. As increasing the absorption coefficient, the growth front temperature and temperature gradient inside a growing crystal increase. It might cause large thermal stress and affect the grown crystal quality. This agrees well with growth features in experiment. The growth condition should be determined with taking account of absorption coefficient, i.e. doping concentration..
102. Michel Pons, Shinichi Nishizawa, Peter Wellmann, Elisabeth Blanquet, Didier Chaussende, Jean Marc Dedulle, Silicon carbide growth C/Si ratio evaluation and modeling, 2006 MRS Spring Meeting, 2006.04, Modeling and simulation of the SiC growth processes, Physical Vapor Transport (PVT), Chemical Vapor Deposition (CVD) and hybrid techniques, are sufficiently mature to be used as a training tool for engineers as well as a growth machine design tool, e.g. when building new process equipment or up-scaling old ones. It is possible (i) to simulate accurately temperature and deposition distributions, as well as doping (ii) to quantify the limiting phenomena, (iii) to understand the important role of different precursors in CVD and hydrogen additions in PVT. The first conclusion of this paper is the importance of the "effective" C/Si ratio during CVD epitaxy in hot-wall reactors and its capability to explain the doping concentrations. The second conclusion is the influence of the C/Si ratio in alternative bulk growth technique involving gas additions. Preliminary results show that fine tuning of H2 or precursor additions allow a better control of concentrations of residual and intentional doping..
103. Akimasa Kinoshita, Junji Senzaki, Makoto Katou, Shinsuke Harada, Mitsuo Okamato, Shinichi Nishizawa, Kenji Fukuda, Fukuyoshi Morigasa, Tomoyoshi Endou, Takuo Isii, Teruyuki Yashima, Activation treatment of ion implanted dopants using hybrid super RTA equipment, International Conference on Silicon Carbide and Related Materials 2005, (ICSCRM 2005), 2005.09, We perform rapid thermal annealing (RTA) on areas as large as 2-inch φ (diameter) at high temperature using the hybrid super RTA (HS-RTA) equipment. The HS-RTA equipment consists of an infrared annealing unit and a RF induction annealing unit in order to uniformly anneal over 2-inch φ susceptor. As a result of annealing by the HS-RTA equipment, the temperature is elevated from RT to peak temperature (∼1800°C) for less than 1 min, remain stable at annealing temperature for 30s and falls from peak temperature to 1000°C within less than 20s. The temperature distributions on a 2-inch φ susceptor are ±10°C, ±33°C and ±55°C at 1565°C, 1671°C and 1752°C, respectively. Phosphorus (P) ion implanted silicon carbide (SiC) samples are used to evaluate the performance of the HS-RTA equipment. The five implanted samples placed on the 2-inch φ susceptor are annealed for 30s at 1565°C, 1671°C and 1752°C. The mean sheet resistances of the 5 samples annealed at 1565°C, 1671°C and 1752°C are 92.6Ω/□, 82.6Ω/□ and 75.50/□, respectively. The sheet resistance uniformities are 9.9%, 7.9% and 9.3%. The average roughness (Ra) is calculated from 10 μm square Atomic Force Microscopy (AFM) image. Ra values of the samples annealed at 1565°C, 1671°C and 1752°C are 2.399 nm, 2.408 nm and 3.282 nm, respectively..
104. C. Ota, J. Nishio, T. Hatakeyama, T. Shinohe, K. Kojima, Shinichi Nishizawa, H. Ohashi, Fabrication of 4H-SiC floating junction Schottky barrier diodes (Super-SBDs) and their electrical properties, International Conference on Silicon Carbide and Related Materials 2005, (ICSCRM 2005), 2005.09, 4H-SiC floating junction Schottky barrier diodes (Super-SBDs) were fabricated. It was found that their properties are closest to the theoretical limitation, defined by the relationship between specific on-state resistance and breakdown voltage of 4H SiC-unipolar devices. They have a p-type floating layer designed as line-and-spacing. The specific on-state resistances of Super-SBDs with a few micrometers of spacing width were found to be nearly equal to those of conventional SBDs without p-type floating layer. The breakdown voltages of Super-SBDs were higher than those of conventional SBDs. Accordingly the properties of Super-SBDs have improved the trade-off between specific on-state resistance and breakdown voltage, and the highest value to date for Baliga's Figure of Merit (BFOM) has been obtained..
105. Shinichi Nishizawa, Michel Pons, Recent progress of SiC hot-wall epitaxy and its modeling, International Conference on Silicon Carbide and Related Materials 2005, (ICSCRM 2005), 2005.09, From the engineering point of view, SiC hot-wall epitaxy is a very important process in SiC semiconductor processes. There are lots of experimental reports on SiC hot-wall epitaxy. They discussed the growth rate, surface morphology, doping concentration, etc. Recently, the effect of face polarity is also made clear. However, each report mentioned the particular results that strongly depend on the experimental conditions and reactor design. In addition, the discussion with inlet condition such as source gas C/Si ratio, not the depositing surface condition, leads to the confusion. In order to understand and try to design and optimize the hot-wall CVD reactor, a numerical approach is attempted. The authors have tried to make it clear that depositing surface condition might be a universal parameter of SiC CVD, and the numerical simulation could predict the growth rate, surface morphology and doping concentration by taking account of the depositing surface condition. In this study, at first, the recent progress of SiC hot-wall epitaxy in experiment is summarized. Then, the present status of its numerical modeling is explained..
106. M. Pons, Shinichi Nishizawa, P. Wellmann, M. Ucar, E. Blanquet, J. M. Dedulle, F. Baillet, D. Chaussende, C. Bernard, R. Madar, Numerical simulation of SIC processes A characterization tool for the design of epitaxial structures in electronics, 15th European Conference on Chemical Vapor Deposition, EUROCVD-15, 2005.09, Modeling and simulation of the SiC growth processes, Physical Vapor Transport (PVT) and Chemical Vapor Deposition (CVD), are sufficiently mature to be used as a training tool for engineers as well as a growth machine design tool, e.g. when building new process equipment or up-scaling old ones. It is possible to simulate accurately temperature and deposition distributions, as well as doping. The key of success would be the combined use of simulation, experiments and characterization in a "daily interaction". The different presented examples have the aim to show that this approach has the potential of a characterization tool which could be of great importance in the optimization of epitaxial structures used for the fabrication of SiC-based devices..
107. Tomohisa Kato, Kazutoshi Kojima, Shinichi Nishizawa, Kazuo Arai, Defect characterization of 4H-SiC bulk crystals grown on micropipe filled seed crystals, 5th European Conference on Silicon Carbide and Related Materials, ECRSCRM2004, 2004.08, We report defects study in 4H-SiC bulk crystals grown by sublimation method on micropipe filled seed crystals oriented (0001) on-axis. The seed crystals of 1-3 inch in diameter were prepared from the large 4H-SiC bulk crystals. Before the sublimation growth, micropipes of the seed crystals were filled with epilayers grown by micropipe filling technique of CVD method. We confirmed about 95% of micropipes perfectly disappeared in the grown crystal. The mechanism of the micropipe extinction was also defined by defect analysis..
108. Shinichi Nishizawa, Michel Pons, Numerical analysis of growth condition on SiC-CVD in the horizontal hot-wall reactor, 5th European Conference on Silicon Carbide and Related Materials, ECRSCRM2004, 2004.08, Growth, etching, and doping features of SiC-CVD in a horizontal hot-wall reactor were numerically analyzed using the improved heterogeneous model. The improved model was able to explain the growth and etching features accurately. In addition, we propose the surface flux, surface carbon and silicon concentration, and its ratio as the universal parameter of the SiC-CVD process. Concerning doping features, the improved model showed that nitrogen and aluminum doping incorporation could be explained by the site competition model, while taking into account the amount of surface silicon and surface carbon, respectively..

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