| 1. |
Tesshu Nakamura, Makoto Miyamura, Koji Inoue, Satoshi Kawakami, Toshitsugu Sakamoto, Munehiro Tada, Teruo Tanimoto, Dynamically Reconfigurable Decoder Architecture for Adaptive Error Correction Using Cryogenic Non-Volatile FPGAs, Workshop and Tutorial: I too can Quantum! (I2Q), 2023.06. |
| 2. |
Masamitsu Tanaka, Ikki Nagaoka, Satoshi Kawakami, Teruo Tanimoto, Takatugu Ono, Koji Inou, and Akira Fujimaki, High-Throughput Single-Flux-Quantum Circuits Based on Gate- Level-Pipelining toward Artificial Intelligence Applications, The Superconducting SFQ VLSI Workshop, 2022.11. |
| 3. |
Kuan Yi Ng, Aalaa M.A. Babai, Satoshi Kawakami, Teruo Tanimoto, Koji Inoue, Layer-wise power/performance modelling for single-board CNN inference, SIG Technical Reports, Vol.2022-ARC-248 No.13, pp.1-11, 2022.03. |
| 4. |
Kuan Yi Ng, Aalaa M.A. Babai, Satoshi Kawakami, Teruo Tanimoto, Koji Inoue, Layer-wise power/performance analysis for single-board CNN inference, cross-disciplinary workshop on computing Systems, Infrastructures, and programminG (xSIG), 2022.07. |
| 5. |
M.A. Babai Aalaa, Ng Kuan Yi, Tanimoto Teruo, Kawakami Satoshi, Inoue Koji, Non-Volatile FPGA-based Intermittent Computing and Its Performance Analysis, SIG Technical Reports, Vol.2022-ARC-250 No.14, pp.1-7, 2022.10. |
| 6. |
Teruo Tanimoto, Research Activities toward Larger-Scale Cryogenic Quantum Computer Systems, Designers’ Forum in conjunction with ASP-DAC 2023, 2023.01. |
